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ARM: SoC fixes for 5.15, part 3 

One last set of small fixes for the soc tree:
 
  - Incorrect ethernet phy settings found on i.mx and
    allwinner platforms
 
  - a revert for a Qualcomm DT change that caused a boot
    regression
 
  - four patches for incorrect settings in i.MX DT files
 
  - new MAINTAINER file entries for dhcom boards
 
  - a Kconfig fix for a reset driver that became unselectable
 
  - three more code changes for bugs in reset drivers
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Merge tag 'arm-soc-fixes-5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "One last set of small fixes for the soc tree:

   - Incorrect ethernet phy settings found on i.mx and allwinner
     platforms

   - a revert for a Qualcomm DT change that caused a boot regression

   - four patches for incorrect settings in i.MX DT files

   - new MAINTAINER file entries for dhcom boards

   - a Kconfig fix for a reset driver that became unselectable

   - three more code changes for bugs in reset drivers"

* tag 'arm-soc-fixes-5.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  MAINTAINERS: Add maintainers for DHCOM i.MX6 and DHCOM/DHCOR STM32MP1
  Revert "arm64: dts: qcom: sm8250: remove bus clock from the mdss node for sm8250 target"
  arm64: dts: imx8mm-kontron: Fix connection type for VSC8531 RGMII PHY
  arm64: dts: imx8mm-kontron: Fix CAN SPI clock frequency
  arm64: dts: imx8mm-kontron: Fix polarity of reg_rst_eth2
  arm64: dts: imx8mm-kontron: Set lower limit of VDD_SNVS to 800 mV
  arm64: dts: imx8mm-kontron: Make sure SOC and DRAM supply voltages are correct
  reset: socfpga: add empty driver allowing consumers to probe
  reset: tegra-bpmp: Handle errors in BPMP response
  reset: pistachio: Re-enable driver selection
  reset: brcmstb-rescal: fix incorrect polarity of status bit
  ARM: dts: sun7i: A20-olinuxino-lime2: Fix ethernet phy-mode
  arm64: dts: allwinner: h5: NanoPI Neo 2: Fix ethernet node
This commit is contained in:
Linus Torvalds 2021-10-26 15:24:33 -07:00
parent 3906fe9bb7 05d5da3cb1
commit d25f27432f
10 changed files with 64 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
MAINTAINERS
View File

@ -5458,6 +5458,19 @@ F: include/net/devlink.h
F: include/uapi/linux/devlink.h
F: net/core/devlink.c
DH ELECTRONICS IMX6 DHCOM BOARD SUPPORT
M: Christoph Niedermaier <cniedermaier@dh-electronics.com>
L: kernel@dh-electronics.com
S: Maintained
F: arch/arm/boot/dts/imx6*-dhcom-*
DH ELECTRONICS STM32MP1 DHCOM/DHCOR BOARD SUPPORT
M: Marek Vasut <marex@denx.de>
L: kernel@dh-electronics.com
S: Maintained
F: arch/arm/boot/dts/stm32mp1*-dhcom-*
F: arch/arm/boot/dts/stm32mp1*-dhcor-*
DIALOG SEMICONDUCTOR DRIVERS
M: Support Opensource <support.opensource@diasemi.com>
S: Supported

2
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
View File

@ -112,7 +112,7 @@
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
View File

@ -75,7 +75,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};

8
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
View File

@ -70,7 +70,9 @@
regulator-name = "rst-usb-eth2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth2>;
gpio = <&gpio3 2 GPIO_ACTIVE_LOW>;
gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_vdd_5v: regulator-5v {
@ -95,7 +97,7 @@
clocks = <&osc_can>;
interrupt-parent = <&gpio4>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <100000>;
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_vdd_5v>;
};
@ -111,7 +113,7 @@
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rgmii";
phy-connection-type = "rgmii-rxid";
phy-handle = <&ethphy>;
status = "okay";

8
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
View File

@ -91,10 +91,12 @@
reg_vdd_soc: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <800000>;
};
reg_vdd_arm: BUCK2 {
@ -111,7 +113,7 @@
reg_vdd_dram: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <900000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
};
@ -150,7 +152,7 @@
reg_vdd_snvs: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <850000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;

3
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -2590,9 +2590,10 @@
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "nrt_bus", "core";
clock-names = "iface", "bus", "nrt_bus", "core";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
assigned-clock-rates = <460000000>;

4
drivers/reset/Kconfig
View File

@ -147,8 +147,8 @@ config RESET_OXNAS
bool
config RESET_PISTACHIO
bool "Pistachio Reset Driver" if COMPILE_TEST
default MACH_PISTACHIO
bool "Pistachio Reset Driver"
depends on MIPS || COMPILE_TEST
help
This enables the reset driver for ImgTec Pistachio SoCs.

2
drivers/reset/reset-brcmstb-rescal.c
View File

@ -38,7 +38,7 @@ static int brcm_rescal_reset_set(struct reset_controller_dev *rcdev,
}
ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg,
!(reg & BRCM_RESCAL_STATUS_BIT), 100, 1000);
(reg & BRCM_RESCAL_STATUS_BIT), 100, 1000);
if (ret) {
dev_err(data->dev, "time out on SATA/PCIe rescal\n");
return ret;

26
drivers/reset/reset-socfpga.c
View File

@ -92,3 +92,29 @@ void __init socfpga_reset_init(void)
for_each_matching_node(np, socfpga_early_reset_dt_ids)
a10_reset_init(np);
}
/*
* The early driver is problematic, because it doesn't register
* itself as a driver. This causes certain device links to prevent
* consumer devices from probing. The hacky solution is to register
* an empty driver, whose only job is to attach itself to the reset
* manager and call probe.
*/
static const struct of_device_id socfpga_reset_dt_ids[] = {
{ .compatible = "altr,rst-mgr", },
{ /* sentinel */ },
};
static int reset_simple_probe(struct platform_device *pdev)
{
return 0;
}
static struct platform_driver reset_socfpga_driver = {
.probe = reset_simple_probe,
.driver = {
.name = "socfpga-reset",
.of_match_table = socfpga_reset_dt_ids,
},
};
builtin_platform_driver(reset_socfpga_driver);

9
drivers/reset/tegra/reset-bpmp.c
View File

@ -20,6 +20,7 @@ static int tegra_bpmp_reset_common(struct reset_controller_dev *rstc,
struct tegra_bpmp *bpmp = to_tegra_bpmp(rstc);
struct mrq_reset_request request;
struct tegra_bpmp_message msg;
int err;
memset(&request, 0, sizeof(request));
request.cmd = command;
@ -30,7 +31,13 @@ static int tegra_bpmp_reset_common(struct reset_controller_dev *rstc,
msg.tx.data = &request;
msg.tx.size = sizeof(request);
return tegra_bpmp_transfer(bpmp, &msg);
err = tegra_bpmp_transfer(bpmp, &msg);
if (err)
return err;
if (msg.rx.ret)
return -EINVAL;
return 0;
}
static int tegra_bpmp_reset_module(struct reset_controller_dev *rstc,