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Merge branch 'dt/irq-fix' into fixes 

* dt/irq-fix:
  arm64: dts: Fix broken architected timer interrupt trigger
This commit is contained in:
Arnd Bergmann 2016-09-14 22:47:36 +02:00
parent 7ccb8e633c f2a89d3b2b
commit d20ced23c7
11 changed files with 44 additions and 44 deletions
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8
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
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@ -255,10 +255,10 @@
/* Local timer */ /* Local timer */
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xf01>, interrupts = <1 13 0xf08>,
<1 14 0xf01>, <1 14 0xf08>,
<1 11 0xf01>, <1 11 0xf08>,
<1 10 0xf01>; <1 10 0xf08>;
}; };
timer0: timer0@ffc03000 { timer0: timer0@ffc03000 {

8
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
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@ -102,13 +102,13 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 <GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 <GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 <GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
}; };
xtal: xtal-clk { xtal: xtal-clk {

8
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -110,10 +110,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ interrupts = <1 0 0xff08>, /* Secure Phys IRQ */
<1 13 0xff01>, /* Non-secure Phys IRQ */ <1 13 0xff08>, /* Non-secure Phys IRQ */
<1 14 0xff01>, /* Virt IRQ */ <1 14 0xff08>, /* Virt IRQ */
<1 15 0xff01>; /* Hyp IRQ */ <1 15 0xff08>; /* Hyp IRQ */
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };

8
arch/arm64/boot/dts/broadcom/ns2.dtsi
View File

@ -88,13 +88,13 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>, IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>, IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>, IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
IRQ_TYPE_EDGE_RISING)>; IRQ_TYPE_LEVEL_LOW)>;
}; };
pmu { pmu {

8
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
View File

@ -354,10 +354,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <1 13 4>,
<1 14 0xff01>, <1 14 4>,
<1 11 0xff01>, <1 11 4>,
<1 10 0xff01>; <1 10 4>;
}; };
pmu { pmu {

8
arch/arm64/boot/dts/exynos/exynos7.dtsi
View File

@ -473,10 +473,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xff01>, interrupts = <1 13 0xff08>,
<1 14 0xff01>, <1 14 0xff08>,
<1 11 0xff01>, <1 11 0xff08>,
<1 10 0xff01>; <1 10 0xff08>;
}; };
pmu_system_controller: system-controller@105c0000 { pmu_system_controller: system-controller@105c0000 {

8
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -119,10 +119,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x1>, /* Physical Secure PPI */ interrupts = <1 13 0xf08>, /* Physical Secure PPI */
<1 14 0x1>, /* Physical Non-Secure PPI */ <1 14 0xf08>, /* Physical Non-Secure PPI */
<1 11 0x1>, /* Virtual PPI */ <1 11 0xf08>, /* Virtual PPI */
<1 10 0x1>; /* Hypervisor PPI */ <1 10 0xf08>; /* Hypervisor PPI */
}; };
pmu { pmu {

8
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View File

@ -191,10 +191,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */ <1 14 4>, /* Physical Non-Secure PPI, active-low */
<1 11 0x8>, /* Virtual PPI, active-low */ <1 11 4>, /* Virtual PPI, active-low */
<1 10 0x8>; /* Hypervisor PPI, active-low */ <1 10 4>; /* Hypervisor PPI, active-low */
}; };
pmu { pmu {

8
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -122,10 +122,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
odmi: odmi@300000 { odmi: odmi@300000 {

8
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
View File

@ -129,10 +129,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts = <1 13 0xf01>, interrupts = <1 13 4>,
<1 14 0xf01>, <1 14 4>,
<1 11 0xf01>, <1 11 4>,
<1 10 0xf01>; <1 10 4>;
}; };
soc { soc {

8
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -65,10 +65,10 @@
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <1 13 0xf01>, interrupts = <1 13 0xf08>,
<1 14 0xf01>, <1 14 0xf08>,
<1 11 0xf01>, <1 11 0xf08>,
<1 10 0xf01>; <1 10 0xf08>;
}; };
amba_apu { amba_apu {