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mtd: spi-nor: Fix wrong TB selection of GD25Q256 

For GD25Q256, wrong SR bit for top/bottom selection is being used.
Fix it to use appropriate bit.

Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Jungseung Lee 2019-12-02 15:35:07 +09:00 committed by Tudor Ambarus
parent adf1092fa8
commit d1f4acb89c
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1 changed files with 2 additions and 1 deletions
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3
drivers/mtd/spi-nor/spi-nor.c
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@ -2395,7 +2395,8 @@ static const struct flash_info spi_nor_ids[] = {
{
"gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_TB_SR_BIT6)
.fixups = &gd25q256_fixups,
},