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perf tools fixes and improvements for v6.2: 2nd batch 

- Don't stop building perf if python setuptools isn't installed, just
   disable the affected perf feature.
 
 - Remove explicit reference to python 2.x devel files, that warning is
   about python-devel, no matter what version, being unavailable and thus
   disabling the linking with libpython.
 
 - Don't use -Werror=switch-enum when building the python support that
   handles libtraceevent enumerations, as there is no good way to test
   if some specific enum entry is available with the libtraceevent
   installed on the system.
 
 - Introduce 'perf lock contention' --type-filter and --lock-filter, to
   filter by lock type and lock name:
 
   $ sudo ./perf lock record -a -- ./perf bench sched messaging
 
   $ sudo ./perf lock contention -E 5 -Y spinlock
    contended  total wait   max wait  avg wait      type  caller
 
          802     1.26 ms   11.73 us   1.58 us  spinlock  __wake_up_common_lock+0x62
           13   787.16 us  105.44 us  60.55 us  spinlock  remove_wait_queue+0x14
           12   612.96 us   78.70 us  51.08 us  spinlock  prepare_to_wait+0x27
          114   340.68 us   12.61 us   2.99 us  spinlock  try_to_wake_up+0x1f5
           83   226.38 us    9.15 us   2.73 us  spinlock  folio_lruvec_lock_irqsave+0x5e
 
   $ sudo ./perf lock contention -l
    contended  total wait  max wait  avg wait           address  symbol
 
           57     1.11 ms  42.83 us  19.54 us  ffff9f4140059000
           15   280.88 us  23.51 us  18.73 us  ffffffff9d007a40  jiffies_lock
            1    20.49 us  20.49 us  20.49 us  ffffffff9d0d50c0  rcu_state
            1     9.02 us   9.02 us   9.02 us  ffff9f41759e9ba0
 
   $ sudo ./perf lock contention -L jiffies_lock,rcu_state
    contended  total wait  max wait  avg wait      type  caller
 
           15   280.88 us  23.51 us  18.73 us  spinlock  tick_sched_do_timer+0x93
            1    20.49 us  20.49 us  20.49 us  spinlock  __softirqentry_text_start+0xeb
 
   $ sudo ./perf lock contention -L ffff9f4140059000
    contended  total wait  max wait  avg wait      type  caller
 
           38   779.40 us  42.83 us  20.51 us  spinlock  worker_thread+0x50
           11   216.30 us  39.87 us  19.66 us  spinlock  queue_work_on+0x39
            8   118.13 us  20.51 us  14.77 us  spinlock  kthread+0xe5
 
 - Fix splitting CC into compiler and options when checking if a option
   is present in clang to build the python binding, needed in systems
   such as yocto that set CC to, e.g.: "gcc --sysroot=/a/b/c".
 
 - Refresh metris and events for Intel systems: alderlake.  alderlake-n,
   bonnell, broadwell, broadwellde, broadwellx, cascadelakex,
   elkhartlake, goldmont, goldmontplus, haswell, haswellx, icelake,
   icelakex, ivybridge, ivytown, jaketown, knightslanding, meteorlake,
   nehalemep, nehalemex, sandybridge, sapphirerapids, silvermont, skylake,
   skylakex, snowridgex, tigerlake, westmereep-dp, westmereep-sp,
   westmereex.
 
 - Add vendor events files (JSON) for AMD Zen 4, from sections 2.1.15.4
   "Core Performance Monitor Counters", 2.1.15.5 "L3 Cache Performance
   Monitor Counter"s and Section 7.1 "Fabric Performance Monitor Counter
   (PMC) Events" in the Processor Programming Reference (PPR) for AMD
   Family 19h Model 11h Revision B1 processors.
 
   This constitutes events which capture op dispatch, execution and
   retirement, branch prediction, L1 and L2 cache activity, TLB activity,
   L3 cache activity and data bandwidth for various links and interfaces in
   the Data Fabric.
 
 - Also, from the same PPR are metrics taken from Section 2.1.15.2
   "Performance Measurement", including pipeline utilization, which are
   new to Zen 4 processors and useful for finding performance bottlenecks
   by analyzing activity at different stages of the pipeline.
 
 - Greatly improve the 'srcline', 'srcline_from', 'srcline_to' and
   'srcfile' sort keys performance by postponing calling the external
   addr2line utility to the collapse phase of histogram bucketing.
 
 - Fix 'perf test' "all PMU test" to skip parametrized events, that
   requires setting up and are not supported by this test.
 
 - Update tools/ copies of kernel headers: features, disabled-features,
   fscrypt.h, i915_drm.h, msr-index.h, power pc syscall table and kvm.h.
 
 - Add .DELETE_ON_ERROR special Makefile target to clean up partially
   updated files on error.
 
 - Simplify the mksyscalltbl script for arm64 by avoiding to run the host
   compiler to create the syscall table, do it all just with the shell
   script.
 
 - Further fixes to honour quiet mode (-q).
 
 Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Merge tag 'perf-tools-for-v6.2-2-2022-12-22' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

Pull more perf tools updates from Arnaldo Carvalho de Melo:
 "perf tools fixes and improvements:

   - Don't stop building perf if python setuptools isn't installed, just
     disable the affected perf feature.

   - Remove explicit reference to python 2.x devel files, that warning
     is about python-devel, no matter what version, being unavailable
     and thus disabling the linking with libpython.

   - Don't use -Werror=switch-enum when building the python support that
     handles libtraceevent enumerations, as there is no good way to test
     if some specific enum entry is available with the libtraceevent
     installed on the system.

   - Introduce 'perf lock contention' --type-filter and --lock-filter,
     to filter by lock type and lock name:

        $ sudo ./perf lock record -a -- ./perf bench sched messaging

        $ sudo ./perf lock contention -E 5 -Y spinlock
         contended  total wait   max wait  avg wait      type  caller

               802     1.26 ms   11.73 us   1.58 us  spinlock  __wake_up_common_lock+0x62
                13   787.16 us  105.44 us  60.55 us  spinlock  remove_wait_queue+0x14
                12   612.96 us   78.70 us  51.08 us  spinlock  prepare_to_wait+0x27
               114   340.68 us   12.61 us   2.99 us  spinlock  try_to_wake_up+0x1f5
                83   226.38 us    9.15 us   2.73 us  spinlock  folio_lruvec_lock_irqsave+0x5e

        $ sudo ./perf lock contention -l
         contended  total wait  max wait  avg wait           address  symbol

                57     1.11 ms  42.83 us  19.54 us  ffff9f4140059000
                15   280.88 us  23.51 us  18.73 us  ffffffff9d007a40  jiffies_lock
                 1    20.49 us  20.49 us  20.49 us  ffffffff9d0d50c0  rcu_state
                 1     9.02 us   9.02 us   9.02 us  ffff9f41759e9ba0

        $ sudo ./perf lock contention -L jiffies_lock,rcu_state
         contended  total wait  max wait  avg wait      type  caller

                15   280.88 us  23.51 us  18.73 us  spinlock  tick_sched_do_timer+0x93
                 1    20.49 us  20.49 us  20.49 us  spinlock  __softirqentry_text_start+0xeb

        $ sudo ./perf lock contention -L ffff9f4140059000
         contended  total wait  max wait  avg wait      type  caller

                38   779.40 us  42.83 us  20.51 us  spinlock  worker_thread+0x50
                11   216.30 us  39.87 us  19.66 us  spinlock  queue_work_on+0x39
                 8   118.13 us  20.51 us  14.77 us  spinlock  kthread+0xe5

   - Fix splitting CC into compiler and options when checking if a
     option is present in clang to build the python binding, needed in
     systems such as yocto that set CC to, e.g.: "gcc --sysroot=/a/b/c".

   - Refresh metris and events for Intel systems: alderlake.
     alderlake-n, bonnell, broadwell, broadwellde, broadwellx,
     cascadelakex, elkhartlake, goldmont, goldmontplus, haswell,
     haswellx, icelake, icelakex, ivybridge, ivytown, jaketown,
     knightslanding, meteorlake, nehalemep, nehalemex, sandybridge,
     sapphirerapids, silvermont, skylake, skylakex, snowridgex,
     tigerlake, westmereep-dp, westmereep-sp, westmereex.

   - Add vendor events files (JSON) for AMD Zen 4, from sections
     2.1.15.4 "Core Performance Monitor Counters", 2.1.15.5 "L3 Cache
     Performance Monitor Counter"s and Section 7.1 "Fabric Performance
     Monitor Counter (PMC) Events" in the Processor Programming
     Reference (PPR) for AMD Family 19h Model 11h Revision B1
     processors.

     This constitutes events which capture op dispatch, execution and
     retirement, branch prediction, L1 and L2 cache activity, TLB
     activity, L3 cache activity and data bandwidth for various links
     and interfaces in the Data Fabric.

   - Also, from the same PPR are metrics taken from Section 2.1.15.2
     "Performance Measurement", including pipeline utilization, which
     are new to Zen 4 processors and useful for finding performance
     bottlenecks by analyzing activity at different stages of the
     pipeline.

   - Greatly improve the 'srcline', 'srcline_from', 'srcline_to' and
     'srcfile' sort keys performance by postponing calling the external
     addr2line utility to the collapse phase of histogram bucketing.

   - Fix 'perf test' "all PMU test" to skip parametrized events, that
     requires setting up and are not supported by this test.

   - Update tools/ copies of kernel headers: features,
     disabled-features, fscrypt.h, i915_drm.h, msr-index.h, power pc
     syscall table and kvm.h.

   - Add .DELETE_ON_ERROR special Makefile target to clean up partially
     updated files on error.

   - Simplify the mksyscalltbl script for arm64 by avoiding to run the
     host compiler to create the syscall table, do it all just with the
     shell script.

   - Further fixes to honour quiet mode (-q)"

* tag 'perf-tools-for-v6.2-2-2022-12-22' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (67 commits)
  perf python: Fix splitting CC into compiler and options
  perf scripting python: Don't be strict at handling libtraceevent enumerations
  perf arm64: Simplify mksyscalltbl
  perf build: Remove explicit reference to python 2.x devel files
  perf vendor events amd: Add Zen 4 mapping
  perf vendor events amd: Add Zen 4 metrics
  perf vendor events amd: Add Zen 4 uncore events
  perf vendor events amd: Add Zen 4 core events
  perf vendor events intel: Refresh westmereex events
  perf vendor events intel: Refresh westmereep-sp events
  perf vendor events intel: Refresh westmereep-dp events
  perf vendor events intel: Refresh tigerlake metrics and events
  perf vendor events intel: Refresh snowridgex events
  perf vendor events intel: Refresh skylakex metrics and events
  perf vendor events intel: Refresh skylake metrics and events
  perf vendor events intel: Refresh silvermont events
  perf vendor events intel: Refresh sapphirerapids metrics and events
  perf vendor events intel: Refresh sandybridge metrics and events
  perf vendor events intel: Refresh nehalemex events
  perf vendor events intel: Refresh nehalemep events
  ...
This commit is contained in:
Linus Torvalds 2022-12-22 11:07:29 -08:00
parent 9d2f6060fe 09e6f9f983
commit d1ac1a2b14
318 changed files with 131081 additions and 163760 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
tools/arch/x86/include/asm/cpufeatures.h
View File

@ -304,10 +304,16 @@
#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
#define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
#define X86_FEATURE_SGX_EDECCSSA (11*32+18) /* "" SGX EDECCSSA user leaf function */
#define X86_FEATURE_CALL_DEPTH (11*32+19) /* "" Call depth tracking for RSB stuffing */
#define X86_FEATURE_MSR_TSX_CTRL (11*32+20) /* "" MSR IA32_TSX_CTRL (Intel) implemented */
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */
#define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */
#define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */

17
tools/arch/x86/include/asm/disabled-features.h
View File

@ -69,6 +69,12 @@
# define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31))
#endif
#ifdef CONFIG_CALL_DEPTH_TRACKING
# define DISABLE_CALL_DEPTH_TRACKING 0
#else
# define DISABLE_CALL_DEPTH_TRACKING (1 << (X86_FEATURE_CALL_DEPTH & 31))
#endif
#ifdef CONFIG_INTEL_IOMMU_SVM
# define DISABLE_ENQCMD 0
#else
@ -81,6 +87,12 @@
# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31))
#endif
#ifdef CONFIG_XEN_PV
# define DISABLE_XENPV 0
#else
# define DISABLE_XENPV (1 << (X86_FEATURE_XENPV & 31))
#endif
#ifdef CONFIG_INTEL_TDX_GUEST
# define DISABLE_TDX_GUEST 0
#else
@ -98,10 +110,11 @@
#define DISABLED_MASK5 0
#define DISABLED_MASK6 0
#define DISABLED_MASK7 (DISABLE_PTI)
#define DISABLED_MASK8 (DISABLE_TDX_GUEST)
#define DISABLED_MASK8 (DISABLE_XENPV|DISABLE_TDX_GUEST)
#define DISABLED_MASK9 (DISABLE_SGX)
#define DISABLED_MASK10 0
#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET)
#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \
DISABLE_CALL_DEPTH_TRACKING)
#define DISABLED_MASK12 0
#define DISABLED_MASK13 0
#define DISABLED_MASK14 0

24
tools/arch/x86/include/asm/msr-index.h
View File

@ -4,12 +4,7 @@
#include <linux/bits.h>
/*
* CPU model specific register (MSR) numbers.
*
* Do not add new entries to this file unless the definitions are shared
* between multiple compilation units.
*/
/* CPU model specific register (MSR) numbers. */
/* x86-64 specific MSRs */
#define MSR_EFER 0xc0000080 /* extended feature register */
@ -537,7 +532,7 @@
#define MSR_AMD64_DC_CFG 0xc0011022
#define MSR_AMD64_DE_CFG 0xc0011029
#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
#define MSR_AMD64_BU_CFG2 0xc001102a
@ -798,6 +793,7 @@
#define ENERGY_PERF_BIAS_PERFORMANCE 0
#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
#define ENERGY_PERF_BIAS_NORMAL 6
#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7
#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
#define ENERGY_PERF_BIAS_POWERSAVE 15
@ -1052,6 +1048,20 @@
#define VMX_BASIC_MEM_TYPE_WB 6LLU
#define VMX_BASIC_INOUT 0x0040000000000000LLU
/* Resctrl MSRs: */
/* - Intel: */
#define MSR_IA32_L3_QOS_CFG 0xc81
#define MSR_IA32_L2_QOS_CFG 0xc82
#define MSR_IA32_QM_EVTSEL 0xc8d
#define MSR_IA32_QM_CTR 0xc8e
#define MSR_IA32_PQR_ASSOC 0xc8f
#define MSR_IA32_L3_CBM_BASE 0xc90
#define MSR_IA32_L2_CBM_BASE 0xd10
#define MSR_IA32_MBA_THRTL_BASE 0xd50
/* - AMD: */
#define MSR_IA32_MBA_BW_BASE 0xc0000200
/* MSR_IA32_VMX_MISC bits */
#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)

62
tools/include/uapi/drm/i915_drm.h
View File

@ -645,6 +645,22 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
/*
* Query the status of HuC load.
*
* The query can fail in the following scenarios with the listed error codes:
* -ENODEV if HuC is not present on this platform,
* -EOPNOTSUPP if HuC firmware usage is disabled,
* -ENOPKG if HuC firmware fetch failed,
* -ENOEXEC if HuC firmware is invalid or mismatched,
* -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
* -EIO if the FW transfer or the FW authentication failed.
*
* If the IOCTL is successful, the returned parameter will be set to one of the
* following values:
* * 0 if HuC firmware load is not complete,
* * 1 if HuC firmware is authenticated and running.
*/
#define I915_PARAM_HUC_STATUS 42
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
@ -749,6 +765,12 @@ typedef struct drm_i915_irq_wait {
/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
#define I915_PARAM_HAS_USERPTR_PROBE 56
/*
* Frequency of the timestamps in OA reports. This used to be the same as the CS
* timestamp frequency, but differs on some platforms.
*/
#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
/* Must be kept compact -- no holes and well documented */
/**
@ -2650,6 +2672,10 @@ enum drm_i915_oa_format {
I915_OA_FORMAT_A12_B8_C8,
I915_OA_FORMAT_A32u40_A4u32_B8_C8,
/* DG2 */
I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
I915_OA_FORMAT_A24u40_A14u32_B8_C8,
I915_OA_FORMAT_MAX /* non-ABI */
};
@ -3493,27 +3519,13 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
* DG2 64K min page size implications:
* On platforms like DG2/ATS the kernel will always use 64K or larger
* pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
* minimum of 64K GTT alignment for such objects.
*
* On discrete platforms, starting from DG2, we have to contend with GTT
* page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
* objects. Specifically the hardware only supports 64K or larger GTT
* page sizes for such memory. The kernel will already ensure that all
* I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
* sizes underneath.
*
* Note that the returned size here will always reflect any required
* rounding up done by the kernel, i.e 4K will now become 64K on devices
* such as DG2. The kernel will always select the largest minimum
* page-size for the set of possible placements as the value to use when
* rounding up the @size.
*
* Special DG2 GTT address alignment requirement:
*
* The GTT alignment will also need to be at least 2M for such objects.
*
* Note that due to how the hardware implements 64K GTT page support, we
* have some further complications:
* NOTE: Previously the ABI here required a minimum GTT alignment of 2M
* on DG2/ATS, due to how the hardware implemented 64K GTT page support,
* where we had the following complications:
*
* 1) The entire PDE (which covers a 2MB virtual address range), must
* contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
@ -3522,12 +3534,10 @@ struct drm_i915_gem_create_ext {
* 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
* objects.
*
* To keep things simple for userland, we mandate that any GTT mappings
* must be aligned to and rounded up to 2MB. The kernel will internally
* pad them out to the next 2MB boundary. As this only wastes virtual
* address space and avoids userland having to copy any needlessly
* complicated PDE sharing scheme (coloring) and only affects DG2, this
* is deemed to be a good compromise.
* However on actual production HW this was completely changed to now
* allow setting a TLB hint at the PTE level (see PS64), which is a lot
* more flexible than the above. With this the 2M restriction was
* dropped where we now only require 64K.
*/
__u64 size;

4
tools/include/uapi/linux/fscrypt.h
View File

@ -26,6 +26,8 @@
#define FSCRYPT_MODE_AES_256_CTS 4
#define FSCRYPT_MODE_AES_128_CBC 5
#define FSCRYPT_MODE_AES_128_CTS 6
#define FSCRYPT_MODE_SM4_XTS 7
#define FSCRYPT_MODE_SM4_CTS 8
#define FSCRYPT_MODE_ADIANTUM 9
#define FSCRYPT_MODE_AES_256_HCTR2 10
/* If adding a mode number > 10, update FSCRYPT_MODE_MAX in fscrypt_private.h */
@ -185,8 +187,6 @@ struct fscrypt_get_key_status_arg {
#define FS_ENCRYPTION_MODE_AES_256_CTS FSCRYPT_MODE_AES_256_CTS
#define FS_ENCRYPTION_MODE_AES_128_CBC FSCRYPT_MODE_AES_128_CBC
#define FS_ENCRYPTION_MODE_AES_128_CTS FSCRYPT_MODE_AES_128_CTS
#define FS_ENCRYPTION_MODE_SPECK128_256_XTS 7 /* removed */
#define FS_ENCRYPTION_MODE_SPECK128_256_CTS 8 /* removed */
#define FS_ENCRYPTION_MODE_ADIANTUM FSCRYPT_MODE_ADIANTUM
#define FS_KEY_DESC_PREFIX FSCRYPT_KEY_DESC_PREFIX
#define FS_KEY_DESC_PREFIX_SIZE FSCRYPT_KEY_DESC_PREFIX_SIZE

13
tools/include/uapi/linux/kvm.h
View File

@ -98,7 +98,7 @@ struct kvm_userspace_memory_region {
/*
* The bit 0 ~ bit 15 of kvm_userspace_memory_region::flags are visible for
* userspace, other bits are reserved for kvm internal use which are defined
*in include/linux/kvm_host.h.
* in include/linux/kvm_host.h.
*/
#define KVM_MEM_LOG_DIRTY_PAGES (1UL << 0)
#define KVM_MEM_READONLY (1UL << 1)
@ -477,6 +477,9 @@ struct kvm_run {
#define KVM_MSR_EXIT_REASON_INVAL (1 << 0)
#define KVM_MSR_EXIT_REASON_UNKNOWN (1 << 1)
#define KVM_MSR_EXIT_REASON_FILTER (1 << 2)
#define KVM_MSR_EXIT_REASON_VALID_MASK (KVM_MSR_EXIT_REASON_INVAL | \
KVM_MSR_EXIT_REASON_UNKNOWN | \
KVM_MSR_EXIT_REASON_FILTER)
__u32 reason; /* kernel -> user */
__u32 index; /* kernel -> user */
__u64 data; /* kernel <-> user */
@ -1170,6 +1173,8 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_S390_ZPCI_OP 221
#define KVM_CAP_S390_CPU_TOPOLOGY 222
#define KVM_CAP_DIRTY_LOG_RING_ACQ_REL 223
#define KVM_CAP_S390_PROTECTED_ASYNC_DISABLE 224
#define KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP 225
#ifdef KVM_CAP_IRQ_ROUTING
@ -1259,6 +1264,7 @@ struct kvm_x86_mce {
#define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3)
#define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4)
#define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5)
#define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG (1 << 6)
struct kvm_xen_hvm_config {
__u32 flags;
@ -1726,6 +1732,8 @@ enum pv_cmd_id {
KVM_PV_UNSHARE_ALL,
KVM_PV_INFO,
KVM_PV_DUMP,
KVM_PV_ASYNC_CLEANUP_PREPARE,
KVM_PV_ASYNC_CLEANUP_PERFORM,
};
struct kvm_pv_cmd {
@ -1756,6 +1764,7 @@ struct kvm_xen_hvm_attr {
union {
__u8 long_mode;
__u8 vector;
__u8 runstate_update_flag;
struct {
__u64 gfn;
} shared_info;
@ -1796,6 +1805,8 @@ struct kvm_xen_hvm_attr {
/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */
#define KVM_XEN_ATTR_TYPE_EVTCHN 0x3
#define KVM_XEN_ATTR_TYPE_XEN_VERSION 0x4
/* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG */
#define KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG 0x5
/* Per-vCPU Xen attributes */
#define KVM_XEN_VCPU_GET_ATTR _IOWR(KVMIO, 0xca, struct kvm_xen_vcpu_attr)

27
tools/perf/Documentation/perf-lock.txt
View File

@ -143,25 +143,25 @@ CONTENTION OPTIONS
System-wide collection from all CPUs.
-C::
--cpu::
--cpu=<value>::
Collect samples only on the list of CPUs provided. Multiple CPUs can be
provided as a comma-separated list with no space: 0,1. Ranges of CPUs
are specified with -: 0-2. Default is to monitor all CPUs.
-p::
--pid=::
--pid=<value>::
Record events on existing process ID (comma separated list).
--tid=::
--tid=<value>::
Record events on existing thread ID (comma separated list).
--map-nr-entries::
--map-nr-entries=<value>::
Maximum number of BPF map entries (default: 10240).
--max-stack::
--max-stack=<value>::
Maximum stack depth when collecting lock contention (default: 8).
--stack-skip
--stack-skip=<value>::
Number of stack depth to skip when finding a lock caller (default: 3).
-E::
@ -172,6 +172,21 @@ CONTENTION OPTIONS
--lock-addr::
Show lock contention stat by address
-Y::
--type-filter=<value>::
Show lock contention only for given lock types (comma separated list).
Available values are:
semaphore, spinlock, rwlock, rwlock:R, rwlock:W, rwsem, rwsem:R, rwsem:W,
rtmutex, rwlock-rt, rwlock-rt:R, rwlock-rt:W, pcpu-sem, pcpu-sem:R, pcpu-sem:W,
mutex
Note that RW-variant of locks have :R and :W suffix. Names without the
suffix are shortcuts for the both variants. Ex) rwsem = rwsem:R + rwsem:W.
-L::
--lock-filter=<value>::
Show lock contention only for given lock addresses or names (comma separated list).
SEE ALSO
--------

11
tools/perf/Makefile.config
View File

@ -886,12 +886,17 @@ else
else
ifneq ($(feature-libpython), 1)
$(call disable-python,No 'Python.h' (for Python 2.x support) was found: disables Python support - please install python-devel/python-dev)
$(call disable-python,No 'Python.h' was found: disables Python support - please install python-devel/python-dev)
else
LDFLAGS += $(PYTHON_EMBED_LDFLAGS)
EXTLIBS += $(PYTHON_EMBED_LIBADD)
PYTHON_EXTENSION_SUFFIX := $(shell $(PYTHON) -c 'from importlib import machinery; print(machinery.EXTENSION_SUFFIXES[0])')
LANG_BINDINGS += $(obj-perf)python/perf$(PYTHON_EXTENSION_SUFFIX)
PYTHON_SETUPTOOLS_INSTALLED := $(shell $(PYTHON) -c 'import setuptools;' 2> /dev/null && echo "yes" || echo "no")
ifeq ($(PYTHON_SETUPTOOLS_INSTALLED), yes)
PYTHON_EXTENSION_SUFFIX := $(shell $(PYTHON) -c 'from importlib import machinery; print(machinery.EXTENSION_SUFFIXES[0])')
LANG_BINDINGS += $(obj-perf)python/perf$(PYTHON_EXTENSION_SUFFIX)
else
msg := $(warning Missing python setuptools, the python binding won't be built, please install python3-setuptools or equivalent);
endif
CFLAGS += -DHAVE_LIBPYTHON_SUPPORT
$(call detected,CONFIG_LIBPYTHON)
endif

3
tools/perf/Makefile.perf
View File

@ -1151,3 +1151,6 @@ FORCE:
.PHONY: archheaders
endif # force_fixdep
# Delete partially updated (corrupted) files on error
.DELETE_ON_ERROR:

23
tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
View File

@ -23,34 +23,17 @@ create_table_from_c()
{
local sc nr last_sc
create_table_exe=`mktemp ${TMPDIR:-/tmp}/create-table-XXXXXX`
{
cat <<-_EoHEADER
#include <stdio.h>
#include "$input"
int main(int argc, char *argv[])
{
_EoHEADER
while read sc nr; do
printf "%s\n" " printf(\"\\t[%d] = \\\"$sc\\\",\\n\", __NR_$sc);"
printf "%s\n" " [$nr] = \"$sc\","
last_sc=$sc
done
printf "%s\n" " printf(\"#define SYSCALLTBL_ARM64_MAX_ID %d\\n\", __NR_$last_sc);"
printf "}\n"
} | $hostcc -I $incpath/include/uapi -o $create_table_exe -x c -
$create_table_exe
rm -f $create_table_exe
printf "%s\n" "#define SYSCALLTBL_ARM64_MAX_ID __NR_$last_sc"
}
create_table()
{
echo "#include \"$input\""
echo "static const char *syscalltbl_arm64[] = {"
create_table_from_c
echo "};"

7
tools/perf/arch/powerpc/entry/syscalls/syscall.tbl
View File

@ -394,8 +394,11 @@
305 common signalfd sys_signalfd compat_sys_signalfd
306 common timerfd_create sys_timerfd_create
307 common eventfd sys_eventfd
308 common sync_file_range2 sys_sync_file_range2 compat_sys_ppc_sync_file_range2
309 nospu fallocate sys_fallocate compat_sys_fallocate
308 32 sync_file_range2 sys_ppc_sync_file_range2 compat_sys_ppc_sync_file_range2
308 64 sync_file_range2 sys_sync_file_range2
308 spu sync_file_range2 sys_sync_file_range2
309 32 fallocate sys_ppc_fallocate compat_sys_fallocate
309 64 fallocate sys_fallocate
310 nospu subpage_prot sys_subpage_prot
311 32 timerfd_settime sys_timerfd_settime32
311 64 timerfd_settime sys_timerfd_settime

311
tools/perf/builtin-lock.c
View File

@ -32,6 +32,7 @@
#include <semaphore.h>
#include <math.h>
#include <limits.h>
#include <ctype.h>
#include <linux/list.h>
#include <linux/hash.h>
@ -63,6 +64,8 @@ static int max_stack_depth = CONTENTION_STACK_DEPTH;
static int stack_skip = CONTENTION_STACK_SKIP;
static int print_nr_entries = INT_MAX / 2;
static struct lock_filter filters;
static enum lock_aggr_mode aggr_mode = LOCK_AGGR_ADDR;
static struct thread_stat *thread_stat_find(u32 tid)
@ -990,27 +993,55 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
struct thread_stat *ts;
struct lock_seq_stat *seq;
u64 addr = evsel__intval(evsel, sample, "lock_addr");
unsigned int flags = evsel__intval(evsel, sample, "flags");
u64 key;
int ret;
int i, ret;
static bool kmap_loaded;
struct machine *machine = &session->machines.host;
struct map *kmap;
struct symbol *sym;
ret = get_key_by_aggr_mode(&key, addr, evsel, sample);
if (ret < 0)
return ret;
if (!kmap_loaded) {
unsigned long *addrs;
/* make sure it loads the kernel map to find lock symbols */
map__load(machine__kernel_map(machine));
kmap_loaded = true;
/* convert (kernel) symbols to addresses */
for (i = 0; i < filters.nr_syms; i++) {
sym = machine__find_kernel_symbol_by_name(machine,
filters.syms[i],
&kmap);
if (sym == NULL) {
pr_warning("ignore unknown symbol: %s\n",
filters.syms[i]);
continue;
}
addrs = realloc(filters.addrs,
(filters.nr_addrs + 1) * sizeof(*addrs));
if (addrs == NULL) {
pr_warning("memory allocation failure\n");
return -ENOMEM;
}
addrs[filters.nr_addrs++] = kmap->unmap_ip(kmap, sym->start);
filters.addrs = addrs;
}
}
ls = lock_stat_find(key);
if (!ls) {
char buf[128];
const char *name = "";
unsigned int flags = evsel__intval(evsel, sample, "flags");
struct machine *machine = &session->machines.host;
struct map *kmap;
struct symbol *sym;
switch (aggr_mode) {
case LOCK_AGGR_ADDR:
/* make sure it loads the kernel map to find lock symbols */
map__load(machine__kernel_map(machine));
sym = machine__find_kernel_symbol(machine, key, &kmap);
if (sym)
name = sym->name;
@ -1029,13 +1060,41 @@ static int report_lock_contention_begin_event(struct evsel *evsel,
if (!ls)
return -ENOMEM;
if (aggr_mode == LOCK_AGGR_CALLER && verbose) {
if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) {
ls->callstack = get_callstack(sample, max_stack_depth);
if (ls->callstack == NULL)
return -ENOMEM;
}
}
if (filters.nr_types) {
bool found = false;
for (i = 0; i < filters.nr_types; i++) {
if (flags == filters.types[i]) {
found = true;
break;
}
}
if (!found)
return 0;
}
if (filters.nr_addrs) {
bool found = false;
for (i = 0; i < filters.nr_addrs; i++) {
if (addr == filters.addrs[i]) {
found = true;
break;
}
}
if (!found)
return 0;
}
ts = thread_stat_findnew(sample->tid);
if (!ts)
return -ENOMEM;
@ -1214,7 +1273,7 @@ static void print_bad_events(int bad, int total)
for (i = 0; i < BROKEN_MAX; i++)
broken += bad_hist[i];
if (quiet || (broken == 0 && !verbose))
if (quiet || (broken == 0 && verbose <= 0))
return;
pr_info("\n=== output for debug===\n\n");
@ -1437,34 +1496,60 @@ static void sort_result(void)
}
}
static const char *get_type_str(struct lock_stat *st)
{
static const struct {
unsigned int flags;
const char *name;
} table[] = {
{ 0, "semaphore" },
{ LCB_F_SPIN, "spinlock" },
{ LCB_F_SPIN | LCB_F_READ, "rwlock:R" },
{ LCB_F_SPIN | LCB_F_WRITE, "rwlock:W"},
{ LCB_F_READ, "rwsem:R" },
{ LCB_F_WRITE, "rwsem:W" },
{ LCB_F_RT, "rtmutex" },
{ LCB_F_RT | LCB_F_READ, "rwlock-rt:R" },
{ LCB_F_RT | LCB_F_WRITE, "rwlock-rt:W"},
{ LCB_F_PERCPU | LCB_F_READ, "pcpu-sem:R" },
{ LCB_F_PERCPU | LCB_F_WRITE, "pcpu-sem:W" },
{ LCB_F_MUTEX, "mutex" },
{ LCB_F_MUTEX | LCB_F_SPIN, "mutex" },
};
static const struct {
unsigned int flags;
const char *name;
} lock_type_table[] = {
{ 0, "semaphore" },
{ LCB_F_SPIN, "spinlock" },
{ LCB_F_SPIN | LCB_F_READ, "rwlock:R" },
{ LCB_F_SPIN | LCB_F_WRITE, "rwlock:W"},
{ LCB_F_READ, "rwsem:R" },
{ LCB_F_WRITE, "rwsem:W" },
{ LCB_F_RT, "rtmutex" },
{ LCB_F_RT | LCB_F_READ, "rwlock-rt:R" },
{ LCB_F_RT | LCB_F_WRITE, "rwlock-rt:W"},
{ LCB_F_PERCPU | LCB_F_READ, "pcpu-sem:R" },
{ LCB_F_PERCPU | LCB_F_WRITE, "pcpu-sem:W" },
{ LCB_F_MUTEX, "mutex" },
{ LCB_F_MUTEX | LCB_F_SPIN, "mutex" },
/* alias for get_type_flag() */
{ LCB_F_MUTEX | LCB_F_SPIN, "mutex-spin" },
};
for (unsigned int i = 0; i < ARRAY_SIZE(table); i++) {
if (table[i].flags == st->flags)
return table[i].name;
static const char *get_type_str(unsigned int flags)
{
for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) {
if (lock_type_table[i].flags == flags)
return lock_type_table[i].name;
}
return "unknown";
}
static unsigned int get_type_flag(const char *str)
{
for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) {
if (!strcmp(lock_type_table[i].name, str))
return lock_type_table[i].flags;
}
return UINT_MAX;
}
static void lock_filter_finish(void)
{
zfree(&filters.types);
filters.nr_types = 0;
zfree(&filters.addrs);
filters.nr_addrs = 0;
for (int i = 0; i < filters.nr_syms; i++)
free(filters.syms[i]);
zfree(&filters.syms);
filters.nr_syms = 0;
}
static void sort_contention_result(void)
{
sort_result();
@ -1507,6 +1592,9 @@ static void print_contention_result(struct lock_contention *con)
if (st->broken)
bad++;
if (!st->wait_time_total)
continue;
list_for_each_entry(key, &lock_keys, list) {
key->print(key, st);
pr_info(" ");
@ -1514,7 +1602,7 @@ static void print_contention_result(struct lock_contention *con)
switch (aggr_mode) {
case LOCK_AGGR_CALLER:
pr_info(" %10s %s\n", get_type_str(st), st->name);
pr_info(" %10s %s\n", get_type_str(st->flags), st->name);
break;
case LOCK_AGGR_TASK:
pid = st->addr;
@ -1529,7 +1617,7 @@ static void print_contention_result(struct lock_contention *con)
break;
}
if (aggr_mode == LOCK_AGGR_CALLER && verbose) {
if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) {
struct map *kmap;
struct symbol *sym;
char buf[128];
@ -1653,6 +1741,7 @@ static int __cmd_contention(int argc, const char **argv)
.map_nr_entries = bpf_map_entries,
.max_stack = max_stack_depth,
.stack_skip = stack_skip,
.filters = &filters,
};
session = perf_session__new(use_bpf ? NULL : &data, &eops);
@ -1753,6 +1842,7 @@ static int __cmd_contention(int argc, const char **argv)
print_contention_result(&con);
out_delete:
lock_filter_finish();
evlist__delete(con.evlist);
lock_contention_finish();
perf_session__delete(session);
@ -1884,6 +1974,153 @@ static int parse_max_stack(const struct option *opt, const char *str,
return 0;
}
static bool add_lock_type(unsigned int flags)
{
unsigned int *tmp;
tmp = realloc(filters.types, (filters.nr_types + 1) * sizeof(*filters.types));
if (tmp == NULL)
return false;
tmp[filters.nr_types++] = flags;
filters.types = tmp;
return true;
}
static int parse_lock_type(const struct option *opt __maybe_unused, const char *str,
int unset __maybe_unused)
{
char *s, *tmp, *tok;
int ret = 0;
s = strdup(str);
if (s == NULL)
return -1;
for (tok = strtok_r(s, ", ", &tmp); tok; tok = strtok_r(NULL, ", ", &tmp)) {
unsigned int flags = get_type_flag(tok);
if (flags == -1U) {
char buf[32];
if (strchr(tok, ':'))
continue;
/* try :R and :W suffixes for rwlock, rwsem, ... */
scnprintf(buf, sizeof(buf), "%s:R", tok);
flags = get_type_flag(buf);
if (flags != UINT_MAX) {
if (!add_lock_type(flags)) {
ret = -1;
break;
}
}
scnprintf(buf, sizeof(buf), "%s:W", tok);
flags = get_type_flag(buf);
if (flags != UINT_MAX) {
if (!add_lock_type(flags)) {
ret = -1;
break;
}
}
continue;
}
if (!add_lock_type(flags)) {
ret = -1;
break;
}
if (!strcmp(tok, "mutex")) {
flags = get_type_flag("mutex-spin");
if (flags != UINT_MAX) {
if (!add_lock_type(flags)) {
ret = -1;
break;
}
}
}
}
free(s);
return ret;
}
static bool add_lock_addr(unsigned long addr)
{
unsigned long *tmp;
tmp = realloc(filters.addrs, (filters.nr_addrs + 1) * sizeof(*filters.addrs));
if (tmp == NULL) {
pr_err("Memory allocation failure\n");
return false;
}
tmp[filters.nr_addrs++] = addr;
filters.addrs = tmp;
return true;
}
static bool add_lock_sym(char *name)
{
char **tmp;
char *sym = strdup(name);
if (sym == NULL) {
pr_err("Memory allocation failure\n");
return false;
}
tmp = realloc(filters.syms, (filters.nr_syms + 1) * sizeof(*filters.syms));
if (tmp == NULL) {
pr_err("Memory allocation failure\n");
free(sym);
return false;
}
tmp[filters.nr_syms++] = sym;
filters.syms = tmp;
return true;
}
static int parse_lock_addr(const struct option *opt __maybe_unused, const char *str,
int unset __maybe_unused)
{
char *s, *tmp, *tok;
int ret = 0;
u64 addr;
s = strdup(str);
if (s == NULL)
return -1;
for (tok = strtok_r(s, ", ", &tmp); tok; tok = strtok_r(NULL, ", ", &tmp)) {
char *end;
addr = strtoul(tok, &end, 16);
if (*end == '\0') {
if (!add_lock_addr(addr)) {
ret = -1;
break;
}
continue;
}
/*
* At this moment, we don't have kernel symbols. Save the symbols
* in a separate list and resolve them to addresses later.
*/
if (!add_lock_sym(tok)) {
ret = -1;
break;
}
}
free(s);
return ret;
}
int cmd_lock(int argc, const char **argv)
{
const struct option lock_options[] = {
@ -1947,6 +2184,10 @@ int cmd_lock(int argc, const char **argv)
"Default: " __stringify(CONTENTION_STACK_SKIP)),
OPT_INTEGER('E', "entries", &print_nr_entries, "display this many functions"),
OPT_BOOLEAN('l', "lock-addr", &show_lock_addrs, "show lock stats by address"),
OPT_CALLBACK('Y', "type-filter", NULL, "FLAGS",
"Filter specific type of locks", parse_lock_type),
OPT_CALLBACK('L', "lock-filter", NULL, "ADDRS/NAMES",
"Filter specific address/symbol of locks", parse_lock_addr),
OPT_PARENT(lock_options)
};

17
tools/perf/builtin-probe.c
View File

@ -612,6 +612,15 @@ __cmd_probe(int argc, const char **argv)
argc = parse_options(argc, argv, options, probe_usage,
PARSE_OPT_STOP_AT_NON_OPTION);
if (quiet) {
if (verbose != 0) {
pr_err(" Error: -v and -q are exclusive.\n");
return -EINVAL;
}
verbose = -1;
}
if (argc > 0) {
if (strcmp(argv[0], "-") == 0) {
usage_with_options_msg(probe_usage, options,
@ -633,14 +642,6 @@ __cmd_probe(int argc, const char **argv)
if (ret)
return ret;
if (quiet) {
if (verbose != 0) {
pr_err(" Error: -v and -q are exclusive.\n");
return -EINVAL;
}
verbose = -1;
}
if (probe_conf.max_probes == 0)
probe_conf.max_probes = MAX_PROBES;

4
tools/perf/builtin-record.c
View File

@ -3629,7 +3629,7 @@ static int record__init_thread_cpu_masks(struct record *rec, struct perf_cpu_map
for (t = 0; t < rec->nr_threads; t++) {
__set_bit(perf_cpu_map__cpu(cpus, t).cpu, rec->thread_masks[t].maps.bits);
__set_bit(perf_cpu_map__cpu(cpus, t).cpu, rec->thread_masks[t].affinity.bits);
if (verbose) {
if (verbose > 0) {
pr_debug("thread_masks[%d]: ", t);
mmap_cpu_mask__scnprintf(&rec->thread_masks[t].maps, "maps");
pr_debug("thread_masks[%d]: ", t);
@ -3726,7 +3726,7 @@ static int record__init_thread_masks_spec(struct record *rec, struct perf_cpu_ma
}
rec->thread_masks = thread_masks;
rec->thread_masks[t] = thread_mask;
if (verbose) {
if (verbose > 0) {
pr_debug("thread_masks[%d]: ", t);
mmap_cpu_mask__scnprintf(&rec->thread_masks[t].maps, "maps");
pr_debug("thread_masks[%d]: ", t);

2
tools/perf/builtin-script.c
View File

@ -2233,7 +2233,7 @@ static void process_event(struct perf_script *script,
if (PRINT_FIELD(METRIC))
perf_sample__fprint_metric(script, thread, evsel, sample, fp);
if (verbose)
if (verbose > 0)
fflush(fp);
}

4
tools/perf/builtin-stat.c
View File

@ -266,7 +266,7 @@ static void evlist__check_cpu_maps(struct evlist *evlist)
evsel__group_desc(leader, buf, sizeof(buf));
pr_warning(" %s\n", buf);
if (verbose) {
if (verbose > 0) {
cpu_map__snprint(leader->core.cpus, buf, sizeof(buf));
pr_warning(" %s: %s\n", leader->name, buf);
cpu_map__snprint(evsel->core.cpus, buf, sizeof(buf));
@ -2493,7 +2493,7 @@ int cmd_stat(int argc, const char **argv)
if (iostat_mode == IOSTAT_LIST) {
iostat_list(evsel_list, &stat_config);
goto out;
} else if (verbose)
} else if (verbose > 0)
iostat_list(evsel_list, &stat_config);
if (iostat_mode == IOSTAT_RUN && !target__has_cpu(&target))
target.system_wide = true;

2
tools/perf/dlfilters/dlfilter-test-api-v0.c
View File

@ -119,7 +119,7 @@ struct perf_dlfilter_fns perf_dlfilter_fns;
static int verbose;
#define pr_debug(fmt, ...) do { \
if (verbose) \
if (verbose > 0) \
fprintf(stderr, fmt, ##__VA_ARGS__); \
} while (0)

116
tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json
View File

@ -10,7 +10,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
"MetricExpr": "(topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS)",
"MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS",
"MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
"MetricName": "tma_fetch_latency",
"PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
@ -46,7 +46,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
"MetricExpr": "(tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_mispredicts_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@ -55,7 +55,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
"MetricExpr": "(1 - (tma_branch_mispredicts / tma_bad_speculation)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
"MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
"MetricName": "tma_clears_resteers",
"PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
@ -153,7 +153,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
"MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
@ -171,7 +171,7 @@
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
"MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_backend_bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
@ -180,7 +180,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
"MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@ -232,7 +232,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
"MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@ -277,7 +277,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
"MetricExpr": "((25 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (24 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
"MetricExpr": "(25 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 24 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@ -286,7 +286,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
"MetricExpr": "(24 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
"MetricExpr": "24 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@ -295,7 +295,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
"MetricExpr": "(9 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
"MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@ -313,7 +313,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
"MetricExpr": "(MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS)",
"MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@ -340,7 +340,7 @@
},
{
"BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
"MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
"MetricExpr": "tma_st_buffer",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_store_bound",
"PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
@ -349,7 +349,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
"MetricExpr": "((MEM_STORE_RETIRED.L2_HIT * 10 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@ -358,7 +358,7 @@
},
{
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
"MetricExpr": "(28 * Average_Frequency) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
"MetricExpr": "28 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
"MetricName": "tma_false_sharing",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
@ -428,7 +428,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
"MetricExpr": "(cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS",
"MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS)",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@ -556,7 +556,7 @@
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
"MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS",
@ -704,7 +704,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0*SLOTS",
"MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS",
"MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
"MetricName": "tma_heavy_operations",
"PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY",
@ -722,7 +722,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
"MetricExpr": "UOPS_RETIRED.MS / SLOTS",
"MetricExpr": "tma_ms_uops",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
@ -782,21 +782,21 @@
},
{
"BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
"MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
"MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "Memory_Bandwidth",
"Unit": "cpu_core"
},
{
"BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
"MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)))",
"MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))",
"MetricGroup": "Mem;MemoryLat;Offcore",
"MetricName": "Memory_Latency",
"Unit": "cpu_core"
},
{
"BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
"MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores))) ",
"MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
"MetricGroup": "Mem;MemoryTLB;Offcore",
"MetricName": "Memory_Data_TLBs",
"Unit": "cpu_core"
@ -831,14 +831,14 @@
},
{
"BriefDescription": "Uops Per Instruction",
"MetricExpr": "(tma_retiring * SLOTS) / INST_RETIRED.ANY",
"MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI",
"Unit": "cpu_core"
},
{
"BriefDescription": "Instruction per taken branch",
"MetricExpr": "(tma_retiring * SLOTS) / BR_INST_RETIRED.NEAR_TAKEN",
"MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "UpTB",
"Unit": "cpu_core"
@ -866,7 +866,7 @@
},
{
"BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
"MetricExpr": "SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1",
"MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)",
"MetricGroup": "SMT;tma_L1_group",
"MetricName": "Slots_Utilization",
"Unit": "cpu_core"
@ -888,7 +888,7 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc",
"Unit": "cpu_core"
@ -903,14 +903,14 @@
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
"MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
"MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP",
"Unit": "cpu_core"
},
{
"BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
"MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
"MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
"MetricGroup": "Cor;SMT",
"MetricName": "Core_Bound_Likely",
"Unit": "cpu_core"
@ -966,14 +966,14 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP",
"Unit": "cpu_core"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW.",
@ -1027,7 +1027,7 @@
},
{
"BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
"MetricExpr": "(tma_retiring * SLOTS) / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
"MetricExpr": "tma_retiring * SLOTS / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@",
"MetricGroup": "Pipeline;Ret",
"MetricName": "Retire",
"Unit": "cpu_core"
@ -1104,7 +1104,7 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost",
"Unit": "cpu_core"
@ -1160,63 +1160,63 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI",
"Unit": "cpu_core"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI_Load",
"Unit": "cpu_core"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI",
"Unit": "cpu_core"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All",
"Unit": "cpu_core"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load",
"Unit": "cpu_core"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All",
"Unit": "cpu_core"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load",
"Unit": "cpu_core"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI",
"Unit": "cpu_core"
},
{
"BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
"MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "FB_HPKI",
"Unit": "cpu_core"
@ -1231,28 +1231,28 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW",
"Unit": "cpu_core"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW",
"Unit": "cpu_core"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW",
"Unit": "cpu_core"
},
{
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW;Offcore",
"MetricName": "L3_Cache_Access_BW",
"Unit": "cpu_core"
@ -1294,14 +1294,14 @@
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "Turbo_Utilization * TSC / 1000000000 / duration_time",
"MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency",
"Unit": "cpu_core"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.",
@ -1316,7 +1316,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0",
"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization",
"Unit": "cpu_core"
@ -1337,7 +1337,7 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1000000 / duration_time / 1000",
"MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use",
"Unit": "cpu_core"
@ -1365,7 +1365,7 @@
},
{
"BriefDescription": "Uncore frequency per die [GHZ]",
"MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
"MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
"MetricGroup": "SoC",
"MetricName": "UNCORE_FREQ"
},
@ -1558,7 +1558,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ",
"MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)",
"MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)",
"MetricGroup": "TopdownL2;tma_backend_bound_group",
"MetricName": "tma_load_store_bound",
"ScaleUnit": "100%",
@ -1566,7 +1566,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
"MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
"MetricExpr": "tma_st_buffer",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_store_bound",
"ScaleUnit": "100%",
@ -1614,7 +1614,7 @@
},
{
"BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
"MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_l2_bound",
"ScaleUnit": "100%",
@ -1622,7 +1622,7 @@
},
{
"BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_l3_bound",
"ScaleUnit": "100%",
@ -1630,7 +1630,7 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_dram_bound",
"ScaleUnit": "100%",
@ -1939,25 +1939,25 @@
},
{
"BriefDescription": "Percent of instruction miss cost that hit in the L2",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "Inst_Miss_Cost_L2Hit_Percent",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in the L3",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "Inst_Miss_Cost_L3Hit_Percent",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in DRAM",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "Inst_Miss_Cost_DRAMHit_Percent",
"Unit": "cpu_atom"
},
{
"BriefDescription": "load ops retired per 1000 instruction",
"MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
"MetricName": "MemLoadPKI",
"Unit": "cpu_atom"
},

18
tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json
View File

@ -165,14 +165,14 @@
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ",
"MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)",
"MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)",
"MetricGroup": "TopdownL2;tma_backend_bound_group",
"MetricName": "tma_load_store_bound",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.",
"MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)",
"MetricExpr": "tma_st_buffer",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_store_bound",
"ScaleUnit": "100%"
@ -214,21 +214,21 @@
},
{
"BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.",
"MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_l2_bound",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",
"MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_l3_bound",
"ScaleUnit": "100%"
},
{
"BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
"MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)",
"MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD",
"MetricGroup": "TopdownL3;tma_load_store_bound_group",
"MetricName": "tma_dram_bound",
"ScaleUnit": "100%"
@ -492,22 +492,22 @@
},
{
"BriefDescription": "Percent of instruction miss cost that hit in the L2",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "Inst_Miss_Cost_L2Hit_Percent"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in the L3",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "Inst_Miss_Cost_L3Hit_Percent"
},
{
"BriefDescription": "Percent of instruction miss cost that hit in DRAM",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)",
"MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH",
"MetricName": "Inst_Miss_Cost_DRAMHit_Percent"
},
{
"BriefDescription": "load ops retired per 1000 instruction",
"MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
"MetricName": "MemLoadPKI"
},
{

82
tools/perf/pmu-events/arch/x86/amdzen4/branch.json Normal file
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@ -0,0 +1,82 @@
[
{
"EventName": "bp_l2_btb_correct",
"EventCode": "0x8b",
"BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
},
{
"EventName": "bp_dyn_ind_pred",
"EventCode": "0x8e",
"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
},
{
"EventName": "bp_de_redirect",
"EventCode": "0x91",
"BriefDescription": "Instruction decoder corrects the predicted target and resteers the branch predictor."
},
{
"EventName": "ex_ret_brn",
"EventCode": "0xc2",
"BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
},
{
"EventName": "ex_ret_brn_misp",
"EventCode": "0xc3",
"BriefDescription": "Retired branch instructions mispredicted."
},
{
"EventName": "ex_ret_brn_tkn",
"EventCode": "0xc4",
"BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
},
{
"EventName": "ex_ret_brn_tkn_misp",
"EventCode": "0xc5",
"BriefDescription": "Retired taken branch instructions mispredicted."
},
{
"EventName": "ex_ret_brn_far",
"EventCode": "0xc6",
"BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
},
{
"EventName": "ex_ret_near_ret",
"EventCode": "0xc8",
"BriefDescription": "Retired near returns (RET or RET Iw)."
},
{
"EventName": "ex_ret_near_ret_mispred",
"EventCode": "0xc9",
"BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
},
{
"EventName": "ex_ret_brn_ind_misp",
"EventCode": "0xca",
"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
},
{
"EventName": "ex_ret_ind_brch_instr",
"EventCode": "0xcc",
"BriefDescription": "Retired indirect branch instructions."
},
{
"EventName": "ex_ret_cond",
"EventCode": "0xd1",
"BriefDescription": "Retired conditional branch instructions."
},
{
"EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
"EventCode": "0x1c7",
"BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
},
{
"EventName": "ex_ret_uncond_brnch_instr_mispred",
"EventCode": "0x1c8",
"BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
},
{
"EventName": "ex_ret_uncond_brnch_instr",
"EventCode": "0x1c9",
"BriefDescription": "Retired unconditional branch instructions."
}
]

772
tools/perf/pmu-events/arch/x86/amdzen4/cache.json Normal file
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@ -0,0 +1,772 @@
[
{
"EventName": "ls_mab_alloc.load_store_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
"UMask": "0x3f"
},
{
"EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
"UMask": "0x40"
},
{
"EventName": "ls_mab_alloc.all_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
"UMask": "0x7f"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_l2",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_ccx",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_dmnd_fills_from_sys.near_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_near",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_dmnd_fills_from_sys.far_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_far",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_dmnd_fills_from_sys.alternate_memories",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_dmnd_fills_from_sys.all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_any_fills_from_sys.local_l2",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_any_fills_from_sys.local_ccx",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_any_fills_from_sys.local_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_any_fills_from_sys.near_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_near",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_any_fills_from_sys.far_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_any_fills_from_sys.remote_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_far",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.far_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_any_fills_from_sys.all_dram_io",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.alternate_memories",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_any_fills_from_sys.all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_pref_instr_disp.prefetch",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
"UMask": "0x01"
},
{
"EventName": "ls_pref_instr_disp.prefetch_w",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
"UMask": "0x02"
},
{
"EventName": "ls_pref_instr_disp.prefetch_nta",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
"UMask": "0x04"
},
{
"EventName": "ls_pref_instr_disp.all",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
"UMask": "0x07"
},
{
"EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
"UMask": "0x01"
},
{
"EventName": "ls_inef_sw_pref.mab_mch_cnt",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB).",
"UMask": "0x02"
},
{
"EventName": "ls_inef_sw_pref.all",
"EventCode": "0x52",
"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
"UMask": "0x03"
},
{
"EventName": "ls_sw_pf_dc_fills.local_l2",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_sw_pf_dc_fills.local_ccx",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_sw_pf_dc_fills.near_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_near",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_sw_pf_dc_fills.far_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_far",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_sw_pf_dc_fills.alternate_memories",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_sw_pf_dc_fills.all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_hw_pf_dc_fills.local_l2",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_hw_pf_dc_fills.local_ccx",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_hw_pf_dc_fills.near_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_near",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_hw_pf_dc_fills.far_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_far",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_hw_pf_dc_fills.alternate_memories",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_hw_pf_dc_fills.all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_alloc_mab_count",
"EventCode": "0x5f",
"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
},
{
"EventName": "l2_request_g1.group2",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
"UMask": "0x01"
},
{
"EventName": "l2_request_g1.l2_hw_pf",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss).",
"UMask": "0x02"
},
{
"EventName": "l2_request_g1.prefetch_l2_cmd",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: prefetch directly into L2.",
"UMask": "0x04"
},
{
"EventName": "l2_request_g1.change_to_x",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache state change to writable, check L2 for current state.",
"UMask": "0x08"
},
{
"EventName": "l2_request_g1.cacheable_ic_read",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: instruction cache reads.",
"UMask": "0x10"
},
{
"EventName": "l2_request_g1.ls_rd_blk_c_s",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache shared reads.",
"UMask": "0x20"
},
{
"EventName": "l2_request_g1.rd_blk_x",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache stores.",
"UMask": "0x40"
},
{
"EventName": "l2_request_g1.rd_blk_l",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.",
"UMask": "0x80"
},
{
"EventName": "l2_request_g1.all_dc",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
"UMask": "0xe8"
},
{
"EventName": "l2_request_g1.all_no_prefetch",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of common types not including prefetches.",
"UMask": "0xf9"
},
{
"EventName": "l2_request_g1.all",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of all types.",
"UMask": "0xff"
},
{
"EventName": "l2_cache_req_stat.ic_fill_miss",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2.",
"UMask": "0x01"
},
{
"EventName": "l2_cache_req_stat.ic_fill_hit_s",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2.",
"UMask": "0x02"
},
{
"EventName": "l2_cache_req_stat.ic_fill_hit_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2.",
"UMask": "0x04"
},
{
"EventName": "l2_cache_req_stat.ic_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache hits.",
"UMask": "0x06"
},
{
"EventName": "l2_cache_req_stat.ic_access_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache access.",
"UMask": "0x07"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_c",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2.",
"UMask": "0x08"
},
{
"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
"UMask": "0x09"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2.",
"UMask": "0x10"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2.",
"UMask": "0x20"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2.",
"UMask": "0x40"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_cs",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2.",
"UMask": "0x80"
},
{
"EventName": "l2_cache_req_stat.dc_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
"UMask": "0xf0"
},
{
"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
"UMask": "0xf6"
},
{
"EventName": "l2_cache_req_stat.dc_access_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
"UMask": "0xf8"
},
{
"EventName": "l2_cache_req_stat.all",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_hit_l2.l2_stream",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
"UMask": "0x01"
},
{
"EventName": "l2_pf_hit_l2.l2_next_line",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache).",
"UMask": "0x02"
},
{
"EventName": "l2_pf_hit_l2.l2_up_down",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
"UMask": "0x04"
},
{
"EventName": "l2_pf_hit_l2.l2_burst",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
"UMask": "0x08"
},
{
"EventName": "l2_pf_hit_l2.l2_stride",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous).",
"UMask": "0x10"
},
{
"EventName": "l2_pf_hit_l2.l1_stream",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
"UMask": "0x20"
},
{
"EventName": "l2_pf_hit_l2.l1_stride",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
"UMask": "0x40"
},
{
"EventName": "l2_pf_hit_l2.l1_region",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
"UMask": "0x80"
},
{
"EventName": "l2_pf_hit_l2.all",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_stream",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
"UMask": "0x01"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_next_line",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache).",
"UMask": "0x02"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_up_down",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
"UMask": "0x04"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_burst",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
"UMask": "0x08"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_stride",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous).",
"UMask": "0x10"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_stream",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
"UMask": "0x20"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_stride",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
"UMask": "0x40"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_region",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
"UMask": "0x80"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.all",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_stream",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache).",
"UMask": "0x01"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_next_line",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache).",
"UMask": "0x02"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_up_down",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
"UMask": "0x04"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_burst",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
"UMask": "0x08"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_stride",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous).",
"UMask": "0x10"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_stream",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache).",
"UMask": "0x20"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_stride",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
"UMask": "0x40"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_region",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
"UMask": "0x80"
},
{
"EventName": "l2_pf_miss_l2_l3.all",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types.",
"UMask": "0xff"
},
{
"EventName": "ic_cache_fill_l2",
"EventCode": "0x82",
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
},
{
"EventName": "ic_cache_fill_sys",
"EventCode": "0x83",
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."
},
{
"EventName": "ic_tag_hit_miss.instruction_cache_hit",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache hits.",
"UMask": "0x07"
},
{
"EventName": "ic_tag_hit_miss.instruction_cache_miss",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache misses.",
"UMask": "0x18"
},
{
"EventName": "ic_tag_hit_miss.all_instruction_cache_accesses",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache accesses of all types.",
"UMask": "0x1f"
},
{
"EventName": "op_cache_hit_miss.op_cache_hit",
"EventCode": "0x28f",
"BriefDescription": "Op cache hits.",
"UMask": "0x03"
},
{
"EventName": "op_cache_hit_miss.op_cache_miss",
"EventCode": "0x28f",
"BriefDescription": "Op cache misses.",
"UMask": "0x04"
},
{
"EventName": "op_cache_hit_miss.all_op_cache_accesses",
"EventCode": "0x28f",
"BriefDescription": "Op cache accesses of all types.",
"UMask": "0x07"
},
{
"EventName": "l3_lookup_state.l3_miss",
"EventCode": "0x04",
"BriefDescription": "L3 cache misses.",
"UMask": "0x01",
"Unit": "L3PMC"
},
{
"EventName": "l3_lookup_state.l3_hit",
"EventCode": "0x04",
"BriefDescription": "L3 cache hits.",
"UMask": "0xfe",
"Unit": "L3PMC"
},
{
"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
"EventCode": "0x04",
"BriefDescription": "L3 cache requests for all coherent accesses.",
"UMask": "0xff",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.dram_near",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
"UMask": "0x01",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.dram_far",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
"UMask": "0x02",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.near_cache",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
"UMask": "0x04",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.far_cache",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
"UMask": "0x08",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.ext_near",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
"UMask": "0x10",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.ext_far",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
"UMask": "0x20",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.all",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency from all data sources.",
"UMask": "0x3f",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.dram_near",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
"UMask": "0x01",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.dram_far",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
"UMask": "0x02",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.near_cache",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
"UMask": "0x04",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.far_cache",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
"UMask": "0x08",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.ext_near",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
"UMask": "0x10",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.ext_far",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
"UMask": "0x20",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.all",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from all data sources.",
"UMask": "0x3f",
"Unit": "L3PMC"
}
]

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[
{
"EventName": "ls_locks.bus_lock",
"EventCode": "0x25",
"BriefDescription": "Retired Lock instructions which caused a bus lock.",
"UMask": "0x01"
},
{
"EventName": "ls_ret_cl_flush",
"EventCode": "0x26",
"BriefDescription": "Retired CLFLUSH instructions."
},
{
"EventName": "ls_ret_cpuid",
"EventCode": "0x27",
"BriefDescription": "Retired CPUID instructions."
},
{
"EventName": "ls_smi_rx",
"EventCode": "0x2b",
"BriefDescription": "SMIs received."
},
{
"EventName": "ls_int_taken",
"EventCode": "0x2c",
"BriefDescription": "Interrupts taken."
},
{
"EventName": "ls_not_halted_cyc",
"EventCode": "0x76",
"BriefDescription": "Core cycles not in halt."
},
{
"EventName": "ex_ret_instr",
"EventCode": "0xc0",
"BriefDescription": "Retired instructions."
},
{
"EventName": "ex_ret_ops",
"EventCode": "0xc1",
"BriefDescription": "Retired macro-ops."
},
{
"EventName": "ex_div_busy",
"EventCode": "0xd3",
"BriefDescription": "Number of cycles the divider is busy."
},
{
"EventName": "ex_div_count",
"EventCode": "0xd4",
"BriefDescription": "Divide ops executed."
},
{
"EventName": "ex_no_retire.empty",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
"UMask": "0x01"
},
{
"EventName": "ex_no_retire.not_complete",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
"UMask": "0x02"
},
{
"EventName": "ex_no_retire.other",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
"UMask": "0x08"
},
{
"EventName": "ex_no_retire.thread_not_selected",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
"UMask": "0x10"
},
{
"EventName": "ex_no_retire.load_not_complete",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
"UMask": "0xa2"
},
{
"EventName": "ex_no_retire.all",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire for any reason.",
"UMask": "0x1b"
},
{
"EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
"EventCode": "0x120",
"BriefDescription": "Reference cycles (P0 frequency) not in halt .",
"UMask": "0x1"
},
{
"EventName": "ex_ret_ucode_instr",
"EventCode": "0x1c1",
"BriefDescription": "Retired microcoded instructions."
},
{
"EventName": "ex_ret_ucode_ops",
"EventCode": "0x1c2",
"BriefDescription": "Retired microcode ops."
},
{
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
"EventCode": "0x1cf",
"BriefDescription": "Ops tagged by IBS.",
"UMask": "0x01"
},
{
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
"EventCode": "0x1cf",
"BriefDescription": "Ops tagged by IBS that retired.",
"UMask": "0x02"
},
{
"EventName": "ex_ret_fused_instr",
"EventCode": "0x1d0",
"BriefDescription": "Retired fused instructions."
}
]

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[
{
"EventName": "fp_ret_x87_fp_ops.add_sub_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point add and subtract ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ret_x87_fp_ops.mul_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point multiply ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ret_x87_fp_ops.div_sqrt_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point divide and square root ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ret_x87_fp_ops.all",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point ops of all types.",
"UMask": "0x07"
},
{
"EventName": "fp_ret_sse_avx_ops.add_sub_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point add and subtract ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ret_sse_avx_ops.mult_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point multiply ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ret_sse_avx_ops.div_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point divide and square root ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ret_sse_avx_ops.mac_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops).",
"UMask": "0x08"
},
{
"EventName": "fp_ret_sse_avx_ops.bfloat_mac_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops).",
"UMask": "0x10"
},
{
"EventName": "fp_ret_sse_avx_ops.all",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point ops of all types.",
"UMask": "0x1f"
},
{
"EventName": "fp_retired_ser_ops.x87_ctrl_ret",
"EventCode": "0x05",
"BriefDescription": "Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits.",
"UMask": "0x01"
},
{
"EventName": "fp_retired_ser_ops.x87_bot_ret",
"EventCode": "0x05",
"BriefDescription": "Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing.",
"UMask": "0x02"
},
{
"EventName": "fp_retired_ser_ops.sse_ctrl_ret",
"EventCode": "0x05",
"BriefDescription": "Retired SSE and AVX control word mispredict traps.",
"UMask": "0x04"
},
{
"EventName": "fp_retired_ser_ops.sse_bot_ret",
"EventCode": "0x05",
"BriefDescription": "Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing.",
"UMask": "0x08"
},
{
"EventName": "fp_retired_ser_ops.all",
"EventCode": "0x05",
"BriefDescription": "Retired SSE and AVX serializing ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_ops_retired_by_width.x87_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired x87 floating-point ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ops_retired_by_width.mmx_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired MMX floating-point ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ops_retired_by_width.scalar_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired scalar floating-point ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ops_retired_by_width.pack_128_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 128-bit floating-point ops.",
"UMask": "0x08"
},
{
"EventName": "fp_ops_retired_by_width.pack_256_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 256-bit floating-point ops.",
"UMask": "0x10"
},
{
"EventName": "fp_ops_retired_by_width.pack_512_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 512-bit floating-point ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ops_retired_by_width.all",
"EventCode": "0x08",
"BriefDescription": "Retired floating-point ops of all widths.",
"UMask": "0x3f"
},
{
"EventName": "fp_ops_retired_by_type.scalar_add",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point add ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ops_retired_by_type.scalar_sub",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point subtract ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ops_retired_by_type.scalar_mul",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point multiply ops.",
"UMask": "0x03"
},
{
"EventName": "fp_ops_retired_by_type.scalar_mac",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ops_retired_by_type.scalar_div",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point divide ops.",
"UMask": "0x05"
},
{
"EventName": "fp_ops_retired_by_type.scalar_sqrt",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point square root ops.",
"UMask": "0x06"
},
{
"EventName": "fp_ops_retired_by_type.scalar_cmp",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point compare ops.",
"UMask": "0x07"
},
{
"EventName": "fp_ops_retired_by_type.scalar_cvt",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point convert ops.",
"UMask": "0x08"
},
{
"EventName": "fp_ops_retired_by_type.scalar_blend",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point blend ops.",
"UMask": "0x09"
},
{
"EventName": "fp_ops_retired_by_type.scalar_other",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "fp_ops_retired_by_type.scalar_all",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_ops_retired_by_type.vector_add",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point add ops.",
"UMask": "0x10"
},
{
"EventName": "fp_ops_retired_by_type.vector_sub",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point subtract ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ops_retired_by_type.vector_mul",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point multiply ops.",
"UMask": "0x30"
},
{
"EventName": "fp_ops_retired_by_type.vector_mac",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "fp_ops_retired_by_type.vector_div",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point divide ops.",
"UMask": "0x50"
},
{
"EventName": "fp_ops_retired_by_type.vector_sqrt",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point square root ops.",
"UMask": "0x60"
},
{
"EventName": "fp_ops_retired_by_type.vector_cmp",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point compare ops.",
"UMask": "0x70"
},
{
"EventName": "fp_ops_retired_by_type.vector_cvt",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point convert ops.",
"UMask": "0x80"
},
{
"EventName": "fp_ops_retired_by_type.vector_blend",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point blend ops.",
"UMask": "0x90"
},
{
"EventName": "fp_ops_retired_by_type.vector_shuffle",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "fp_ops_retired_by_type.vector_logical",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point logical ops.",
"UMask": "0xd0"
},
{
"EventName": "fp_ops_retired_by_type.vector_other",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "fp_ops_retired_by_type.vector_all",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "fp_ops_retired_by_type.all",
"EventCode": "0x0a",
"BriefDescription": "Retired floating-point ops of all types.",
"UMask": "0xff"
},
{
"EventName": "sse_avx_ops_retired.mmx_add",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer add.",
"UMask": "0x01"
},
{
"EventName": "sse_avx_ops_retired.mmx_sub",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer subtract ops.",
"UMask": "0x02"
},
{
"EventName": "sse_avx_ops_retired.mmx_mul",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply ops.",
"UMask": "0x03"
},
{
"EventName": "sse_avx_ops_retired.mmx_mac",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "sse_avx_ops_retired.mmx_cmp",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer compare ops.",
"UMask": "0x07"
},
{
"EventName": "sse_avx_ops_retired.mmx_shift",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer shift ops.",
"UMask": "0x09"
},
{
"EventName": "sse_avx_ops_retired.mmx_mov",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer MOV ops.",
"UMask": "0x0a"
},
{
"EventName": "sse_avx_ops_retired.mmx_shuffle",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "sse_avx_ops_retired.mmx_pack",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer pack ops.",
"UMask": "0x0c"
},
{
"EventName": "sse_avx_ops_retired.mmx_logical",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer logical ops.",
"UMask": "0x0d"
},
{
"EventName": "sse_avx_ops_retired.mmx_other",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "sse_avx_ops_retired.mmx_all",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_add",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer add ops.",
"UMask": "0x10"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_sub",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer subtract ops.",
"UMask": "0x20"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mul",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer multiply ops.",
"UMask": "0x30"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mac",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_aes",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer AES ops.",
"UMask": "0x50"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_sha",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer SHA ops.",
"UMask": "0x60"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_cmp",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer compare ops.",
"UMask": "0x70"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_clm",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer CLM ops.",
"UMask": "0x80"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_shift",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer shift ops.",
"UMask": "0x90"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mov",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer MOV ops.",
"UMask": "0xa0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_shuffle",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_pack",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer pack ops.",
"UMask": "0xc0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_logical",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer logical ops.",
"UMask": "0xd0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_other",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_all",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "sse_avx_ops_retired.all",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE, AVX and MMX integer ops of all types.",
"UMask": "0xff"
},
{
"EventName": "fp_pack_ops_retired.fp128_add",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point add ops.",
"UMask": "0x01"
},
{
"EventName": "fp_pack_ops_retired.fp128_sub",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point subtract ops.",
"UMask": "0x02"
},
{
"EventName": "fp_pack_ops_retired.fp128_mul",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point multiply ops.",
"UMask": "0x03"
},
{
"EventName": "fp_pack_ops_retired.fp128_mac",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "fp_pack_ops_retired.fp128_div",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point divide ops.",
"UMask": "0x05"
},
{
"EventName": "fp_pack_ops_retired.fp128_sqrt",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point square root ops.",
"UMask": "0x06"
},
{
"EventName": "fp_pack_ops_retired.fp128_cmp",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point compare ops.",
"UMask": "0x07"
},
{
"EventName": "fp_pack_ops_retired.fp128_cvt",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point convert ops.",
"UMask": "0x08"
},
{
"EventName": "fp_pack_ops_retired.fp128_blend",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point blend ops.",
"UMask": "0x09"
},
{
"EventName": "fp_pack_ops_retired.fp128_shuffle",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "fp_pack_ops_retired.fp128_logical",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point logical ops.",
"UMask": "0x0d"
},
{
"EventName": "fp_pack_ops_retired.fp128_other",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "fp_pack_ops_retired.fp128_all",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_pack_ops_retired.fp256_add",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point add ops.",
"UMask": "0x10"
},
{
"EventName": "fp_pack_ops_retired.fp256_sub",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point subtract ops.",
"UMask": "0x20"
},
{
"EventName": "fp_pack_ops_retired.fp256_mul",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point multiply ops.",
"UMask": "0x30"
},
{
"EventName": "fp_pack_ops_retired.fp256_mac",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "fp_pack_ops_retired.fp256_div",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point divide ops.",
"UMask": "0x50"
},
{
"EventName": "fp_pack_ops_retired.fp256_sqrt",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point square root ops.",
"UMask": "0x60"
},
{
"EventName": "fp_pack_ops_retired.fp256_cmp",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point compare ops.",
"UMask": "0x70"
},
{
"EventName": "fp_pack_ops_retired.fp256_cvt",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point convert ops.",
"UMask": "0x80"
},
{
"EventName": "fp_pack_ops_retired.fp256_blend",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point blend ops.",
"UMask": "0x90"
},
{
"EventName": "fp_pack_ops_retired.fp256_shuffle",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "fp_pack_ops_retired.fp256_logical",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point logical ops.",
"UMask": "0xd0"
},
{
"EventName": "fp_pack_ops_retired.fp256_other",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "fp_pack_ops_retired.fp256_all",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "fp_pack_ops_retired.all",
"EventCode": "0x0c",
"BriefDescription": "Retired packed floating-point ops of all types.",
"UMask": "0xff"
},
{
"EventName": "packed_int_op_type.int128_add",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer add ops.",
"UMask": "0x01"
},
{
"EventName": "packed_int_op_type.int128_sub",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer subtract ops.",
"UMask": "0x02"
},
{
"EventName": "packed_int_op_type.int128_mul",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer multiply ops.",
"UMask": "0x03"
},
{
"EventName": "packed_int_op_type.int128_mac",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "packed_int_op_type.int128_aes",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer AES ops.",
"UMask": "0x05"
},
{
"EventName": "packed_int_op_type.int128_sha",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer SHA ops.",
"UMask": "0x06"
},
{
"EventName": "packed_int_op_type.int128_cmp",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer compare ops.",
"UMask": "0x07"
},
{
"EventName": "packed_int_op_type.int128_clm",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer CLM ops.",
"UMask": "0x08"
},
{
"EventName": "packed_int_op_type.int128_shift",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer shift ops.",
"UMask": "0x09"
},
{
"EventName": "packed_int_op_type.int128_mov",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer MOV ops.",
"UMask": "0x0a"
},
{
"EventName": "packed_int_op_type.int128_shuffle",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "packed_int_op_type.int128_pack",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer pack ops.",
"UMask": "0x0c"
},
{
"EventName": "packed_int_op_type.int128_logical",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer logical ops.",
"UMask": "0x0d"
},
{
"EventName": "packed_int_op_type.int128_other",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "packed_int_op_type.int128_all",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "packed_int_op_type.int256_add",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer add ops.",
"UMask": "0x10"
},
{
"EventName": "packed_int_op_type.int256_sub",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer subtract ops.",
"UMask": "0x20"
},
{
"EventName": "packed_int_op_type.int256_mul",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer multiply ops.",
"UMask": "0x30"
},
{
"EventName": "packed_int_op_type.int256_mac",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "packed_int_op_type.int256_cmp",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer compare ops.",
"UMask": "0x70"
},
{
"EventName": "packed_int_op_type.int256_shift",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer shift ops.",
"UMask": "0x90"
},
{
"EventName": "packed_int_op_type.int256_mov",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer MOV ops.",
"UMask": "0xa0"
},
{
"EventName": "packed_int_op_type.int256_shuffle",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "packed_int_op_type.int256_pack",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer pack ops.",
"UMask": "0xc0"
},
{
"EventName": "packed_int_op_type.int256_logical",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer logical ops.",
"UMask": "0xd0"
},
{
"EventName": "packed_int_op_type.int256_other",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "packed_int_op_type.int256_all",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "packed_int_op_type.all",
"EventCode": "0x0d",
"BriefDescription": "Retired packed integer ops of all types.",
"UMask": "0xff"
},
{
"EventName": "fp_disp_faults.x87_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for x87 fills.",
"UMask": "0x01"
},
{
"EventName": "fp_disp_faults.xmm_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for XMM fills.",
"UMask": "0x02"
},
{
"EventName": "fp_disp_faults.ymm_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for YMM fills.",
"UMask": "0x04"
},
{
"EventName": "fp_disp_faults.ymm_spill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for YMM spills.",
"UMask": "0x08"
},
{
"EventName": "fp_disp_faults.sse_avx_all",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults of all types for SSE and AVX ops.",
"UMask": "0x0e"
},
{
"EventName": "fp_disp_faults.all",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults of all types.",
"UMask": "0x0f"
}
]

174
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[
{
"EventName": "ls_bad_status2.stli_other",
"EventCode": "0x24",
"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
"UMask": "0x02"
},
{
"EventName": "ls_dispatch.ld_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
"UMask": "0x01"
},
{
"EventName": "ls_dispatch.store_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
"UMask": "0x02"
},
{
"EventName": "ls_dispatch.ld_st_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
"UMask": "0x04"
},
{
"EventName": "ls_stlf",
"EventCode": "0x35",
"BriefDescription": "Store-to-load-forward (STLF) hits."
},
{
"EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
"EventCode": "0x37",
"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
"UMask": "0x01"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x02"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
"UMask": "0x04"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
"UMask": "0x08"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
"UMask": "0x10"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x20"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
"UMask": "0x40"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
"UMask": "0x80"
},
{
"EventName": "ls_l1_d_tlb_miss.all_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
"UMask": "0xf0"
},
{
"EventName": "ls_l1_d_tlb_miss.all",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses for all page sizes.",
"UMask": "0xff"
},
{
"EventName": "ls_misal_loads.ma64",
"EventCode": "0x47",
"BriefDescription": "64B misaligned (cacheline crossing) loads.",
"UMask": "0x01"
},
{
"EventName": "ls_misal_loads.ma4k",
"EventCode": "0x47",
"BriefDescription": "4kB misaligned (page crossing) loads.",
"UMask": "0x02"
},
{
"EventName": "ls_tlb_flush.all",
"EventCode": "0x78",
"BriefDescription": "All TLB Flushes.",
"UMask": "0xff"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
"EventCode": "0x84",
"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
"UMask": "0x02"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
"UMask": "0x04"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x08"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
"UMask": "0x0f"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if4k",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x01"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if2m",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
"UMask": "0x02"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if1g",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
"UMask": "0x04"
},
{
"EventName": "bp_l1_tlb_fetch_hit.all",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
"UMask": "0x07"
}
]

138
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[
{
"EventName": "resyncs_or_nc_redirects",
"EventCode": "0x96",
"BriefDescription": "Pipeline restarts not caused by branch mispredicts."
},
{
"EventName": "de_op_queue_empty",
"EventCode": "0xa9",
"BriefDescription": "Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough."
},
{
"EventName": "de_src_op_disp.decoder",
"EventCode": "0xaa",
"BriefDescription": "Ops fetched from instruction cache and dispatched.",
"UMask": "0x01"
},
{
"EventName": "de_src_op_disp.op_cache",
"EventCode": "0xaa",
"BriefDescription": "Ops fetched from op cache and dispatched.",
"UMask": "0x02"
},
{
"EventName": "de_src_op_disp.loop_buffer",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from loop buffer.",
"UMask": "0x04"
},
{
"EventName": "de_src_op_disp.all",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from any source.",
"UMask": "0x07"
},
{
"EventName": "de_dis_ops_from_decoder.any_fp_dispatch",
"EventCode": "0xab",
"BriefDescription": "Number of ops dispatched to the floating-point unit.",
"UMask": "0x04"
},
{
"EventName": "de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch",
"EventCode": "0xab",
"BriefDescription": "Number of ops dispatched to the integer execution unit.",
"UMask": "0x08"
},
{
"EventName": "de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for integer physical register file tokens.",
"UMask": "0x01"
},
{
"EventName": "de_dis_dispatch_token_stalls1.load_queue_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for Load queue token.",
"UMask": "0x02"
},
{
"EventName": "de_dis_dispatch_token_stalls1.store_queue_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for store queue tokens.",
"UMask": "0x04"
},
{
"EventName": "de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for taken branch buffer tokens.",
"UMask": "0x10"
},
{
"EventName": "de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for floating-point register file tokens.",
"UMask": "0x20"
},
{
"EventName": "de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for floating-point scheduler tokens.",
"UMask": "0x40"
},
{
"EventName": "de_dis_dispatch_token_stalls1.fp_flush_recovery_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for floating-point flush recovery.",
"UMask": "0x80"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch0_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 0 tokens.",
"UMask": "0x01"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch1_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 1 tokens.",
"UMask": "0x02"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch2_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 2 tokens.",
"UMask": "0x04"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch3_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 3 tokens.",
"UMask": "0x08"
},
{
"EventName": "de_dis_dispatch_token_stalls2.retire_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for retire queue tokens.",
"UMask": "0x20"
},
{
"EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts dispatch slots left empty because the front-end did not supply ops.",
"UMask": "0x01"
},
{
"EventName": "de_no_dispatch_per_slot.backend_stalls",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts ops unable to dispatch because of back-end stalls.",
"UMask": "0x1e"
},
{
"EventName": "de_no_dispatch_per_slot.smt_contention",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread.",
"UMask": "0x60"
}
]

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[
{
"MetricName": "total_dispatch_slots",
"BriefDescription": "Total dispatch slots (upto 6 instructions can be dispatched in each cycle).",
"MetricExpr": "6 * ls_not_halted_cyc"
},
{
"MetricName": "frontend_bound",
"BriefDescription": "Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "bad_speculation",
"BriefDescription": "Fraction of dispatched ops that did not retire.",
"MetricExpr": "d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_bound",
"BriefDescription": "Fraction of dispatch slots that remained unused because of backend stalls.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "smt_contention",
"BriefDescription": "Fraction of dispatch slots that remained unused because the other thread was selected.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "retiring",
"BriefDescription": "Fraction of dispatch slots used by ops that retired.",
"MetricExpr": "d_ratio(ex_ret_ops, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "frontend_bound_latency",
"BriefDescription": "Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses).",
"MetricExpr": "d_ratio((6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x6@), total_dispatch_slots)",
"MetricGroup": "PipelineL2;frontend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "frontend_bound_bandwidth",
"BriefDescription": "Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth).",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x6@), total_dispatch_slots)",
"MetricGroup": "PipelineL2;frontend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "bad_speculation_mispredicts",
"BriefDescription": "Fraction of dispatched ops that were flushed due to branch mispredicts.",
"MetricExpr": "d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects)",
"MetricGroup": "PipelineL2;bad_speculation_group",
"ScaleUnit": "100%"
},
{
"MetricName": "bad_speculation_pipeline_restarts",
"BriefDescription": "Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs).",
"MetricExpr": "d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects)",
"MetricGroup": "PipelineL2;bad_speculation_group",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_bound_memory",
"BriefDescription": "Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem.",
"MetricExpr": "backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)",
"MetricGroup": "PipelineL2;backend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_bound_cpu",
"BriefDescription": "Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem.",
"MetricExpr": "backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))",
"MetricGroup": "PipelineL2;backend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "retiring_fastpath",
"BriefDescription": "Fraction of dispatch slots used by fastpath ops that retired.",
"MetricExpr": "retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))",
"MetricGroup": "PipelineL2;retiring_group",
"ScaleUnit": "100%"
},
{
"MetricName": "retiring_microcode",
"BriefDescription": "Fraction of dispatch slots used by microcode ops that retired.",
"MetricExpr": "retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)",
"MetricGroup": "PipelineL2;retiring_group",
"ScaleUnit": "100%"
}
]

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[
{
"MetricName": "branch_misprediction_ratio",
"BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
"MetricGroup": "branch_prediction",
"ScaleUnit": "100%"
},
{
"EventName": "all_data_cache_accesses",
"EventCode": "0x29",
"BriefDescription": "All data cache accesses.",
"UMask": "0x07"
},
{
"MetricName": "all_l2_cache_accesses",
"BriefDescription": "All L2 cache accesses.",
"MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_accesses_from_l1_ic_misses",
"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
"MetricExpr": "l2_request_g1.cacheable_ic_read",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_accesses_from_l1_dc_misses",
"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
"MetricExpr": "l2_request_g1.all_dc",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_accesses_from_l2_hwpf",
"BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher.",
"MetricExpr": "l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "all_l2_cache_misses",
"BriefDescription": "All L2 cache misses.",
"MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_misses_from_l1_ic_miss",
"BriefDescription": "L2 cache misses from L1 instruction cache misses.",
"MetricExpr": "l2_cache_req_stat.ic_fill_miss",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_misses_from_l1_dc_miss",
"BriefDescription": "L2 cache misses from L1 data cache misses.",
"MetricExpr": "l2_cache_req_stat.ls_rd_blk_c",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_misses_from_l2_hwpf",
"BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.",
"MetricExpr": "l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "all_l2_cache_hits",
"BriefDescription": "All L2 cache hits.",
"MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_hits_from_l1_ic_miss",
"BriefDescription": "L2 cache hits from L1 instruction cache misses.",
"MetricExpr": "l2_cache_req_stat.ic_hit_in_l2",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_hits_from_l1_dc_miss",
"BriefDescription": "L2 cache hits from L1 data cache misses.",
"MetricExpr": "l2_cache_req_stat.dc_hit_in_l2",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_hits_from_l2_hwpf",
"BriefDescription": "L2 cache hits from L2 cache hardware prefetcher.",
"MetricExpr": "l2_pf_hit_l2.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l3_cache_accesses",
"BriefDescription": "L3 cache accesses.",
"MetricExpr": "l3_lookup_state.all_coherent_accesses_to_l3",
"MetricGroup": "l3_cache"
},
{
"MetricName": "l3_misses",
"BriefDescription": "L3 misses (including cacheline state change requests).",
"MetricExpr": "l3_lookup_state.l3_miss",
"MetricGroup": "l3_cache"
},
{
"MetricName": "l3_read_miss_latency",
"BriefDescription": "Average L3 read miss latency (in core clocks).",
"MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
"MetricGroup": "l3_cache",
"ScaleUnit": "1core clocks"
},
{
"MetricName": "op_cache_fetch_miss_ratio",
"BriefDescription": "Op cache miss ratio for all fetches.",
"MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
"ScaleUnit": "100%"
},
{
"MetricName": "ic_fetch_miss_ratio",
"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit.",
"MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
"ScaleUnit": "100%"
},
{
"MetricName": "l1_data_cache_fills_from_memory",
"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
"MetricExpr": "ls_any_fills_from_sys.dram_io_all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_data_cache_fills_from_remote_node",
"BriefDescription": "L1 data cache fills from a different NUMA node.",
"MetricExpr": "ls_any_fills_from_sys.far_all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_data_cache_fills_from_same_ccx",
"BriefDescription": "L1 data cache fills from within the same CCX.",
"MetricExpr": "ls_any_fills_from_sys.local_all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_data_cache_fills_from_different_ccx",
"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
"MetricExpr": "ls_any_fills_from_sys.remote_cache",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "all_l1_data_cache_fills",
"BriefDescription": "All L1 data cache fills.",
"MetricExpr": "ls_any_fills_from_sys.all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_local_l2",
"BriefDescription": "L1 demand data cache fills from local L2 cache.",
"MetricExpr": "ls_dmnd_fills_from_sys.local_l2",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_same_ccx",
"BriefDescription": "L1 demand data cache fills from within the same CCX.",
"MetricExpr": "ls_dmnd_fills_from_sys.local_ccx",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_near_cache",
"BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.near_cache",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_near_memory",
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_near",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_far_cache",
"BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.far_cache",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_far_memory",
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_far",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_itlb_misses",
"BriefDescription": "L1 instruction TLB misses.",
"MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all",
"MetricGroup": "tlb"
},
{
"MetricName": "l2_itlb_misses",
"BriefDescription": "L2 instruction TLB misses and instruction page walks.",
"MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all",
"MetricGroup": "tlb"
},
{
"MetricName": "l1_dtlb_misses",
"BriefDescription": "L1 data TLB misses.",
"MetricExpr": "ls_l1_d_tlb_miss.all",
"MetricGroup": "tlb"
},
{
"MetricName": "l2_dtlb_misses",
"BriefDescription": "L2 data TLB misses and data page walks.",
"MetricExpr": "ls_l1_d_tlb_miss.all_l2_miss",
"MetricGroup": "tlb"
},
{
"MetricName": "all_tlbs_flushed",
"BriefDescription": "All TLBs flushed.",
"MetricExpr": "ls_tlb_flush.all",
"MetricGroup": "tlb"
},
{
"MetricName": "macro_ops_dispatched",
"BriefDescription": "Macro-ops dispatched.",
"MetricExpr": "de_src_op_disp.all",
"MetricGroup": "decoder"
},
{
"MetricName": "sse_avx_stalls",
"BriefDescription": "Mixed SSE/AVX stalls.",
"MetricExpr": "fp_disp_faults.sse_avx_all"
},
{
"MetricName": "macro_ops_retired",
"BriefDescription": "Macro-ops retired.",
"MetricExpr": "ex_ret_ops"
},
{
"MetricName": "dram_read_data_for_local_processor",
"BriefDescription": "DRAM read data for local processor.",
"MetricExpr": "local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "dram_write_data_for_local_processor",
"BriefDescription": "DRAM write data for local processor.",
"MetricExpr": "local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "dram_read_data_for_remote_processor",
"BriefDescription": "DRAM read data for remote processor.",
"MetricExpr": "remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "dram_write_data_for_remote_processor",
"BriefDescription": "DRAM write data for remote processor.",
"MetricExpr": "remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_upstream_dma_read_data",
"BriefDescription": "Local socket upstream DMA read data.",
"MetricExpr": "local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_upstream_dma_write_data",
"BriefDescription": "Local socket upstream DMA write data.",
"MetricExpr": "local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "remote_socket_upstream_dma_read_data",
"BriefDescription": "Remote socket upstream DMA read data.",
"MetricExpr": "remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "remote_socket_upstream_dma_write_data",
"BriefDescription": "Remote socket upstream DMA write data.",
"MetricExpr": "remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_inbound_data_to_cpu",
"BriefDescription": "Local socket inbound data to the CPU (e.g. read data).",
"MetricExpr": "local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "3.0517578125e-5MiB"
},
{
"MetricName": "local_socket_outbound_data_from_cpu",
"BriefDescription": "Local socket outbound data from the CPU (e.g. write data).",
"MetricExpr": "local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "remote_socket_inbound_data_to_cpu",
"BriefDescription": "Remote socket inbound data to the CPU (e.g. read data).",
"MetricExpr": "remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "3.0517578125e-5MiB"
},
{
"MetricName": "remote_socket_outbound_data_from_cpu",
"BriefDescription": "Remote socket outbound data from the CPU (e.g. write data).",
"MetricExpr": "remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_outbound_data_from_all_links",
"BriefDescription": "Outbound data from all links (local socket).",
"MetricExpr": "local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
}
]

93
tools/perf/pmu-events/arch/x86/bonnell/cache.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "L1 Data Cacheable reads and writes",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ALL_CACHE_REF",
"SampleAfterValue": "2000000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "L1 Data reads and writes",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ALL_REF",
"SampleAfterValue": "2000000",
@ -17,7 +15,6 @@
},
{
"BriefDescription": "Modified cache lines evicted from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.EVICT",
"SampleAfterValue": "200000",
@ -25,7 +22,6 @@
},
{
"BriefDescription": "L1 Cacheable Data Reads",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.LD",
"SampleAfterValue": "2000000",
@ -33,7 +29,6 @@
},
{
"BriefDescription": "L1 Data line replacements",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.REPL",
"SampleAfterValue": "200000",
@ -41,7 +36,6 @@
},
{
"BriefDescription": "Modified cache lines allocated in the L1 data cache",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.REPLM",
"SampleAfterValue": "200000",
@ -49,7 +43,6 @@
},
{
"BriefDescription": "L1 Cacheable Data Writes",
"Counter": "0,1",
"EventCode": "0x40",
"EventName": "L1D_CACHE.ST",
"SampleAfterValue": "2000000",
@ -57,7 +50,6 @@
},
{
"BriefDescription": "Cycles L2 address bus is in use.",
"Counter": "0,1",
"EventCode": "0x21",
"EventName": "L2_ADS.SELF",
"SampleAfterValue": "200000",
@ -65,7 +57,6 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -73,7 +64,6 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -81,7 +71,6 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.MESI",
"SampleAfterValue": "200000",
@ -89,7 +78,6 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -97,7 +85,6 @@
},
{
"BriefDescription": "All data requests from the L1 data cache",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "L2_DATA_RQSTS.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -105,7 +92,6 @@
},
{
"BriefDescription": "Cycles the L2 cache data bus is busy.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "L2_DBUS_BUSY.SELF",
"SampleAfterValue": "200000",
@ -113,7 +99,6 @@
},
{
"BriefDescription": "Cycles the L2 transfers data to the core.",
"Counter": "0,1",
"EventCode": "0x23",
"EventName": "L2_DBUS_BUSY_RD.SELF",
"SampleAfterValue": "200000",
@ -121,7 +106,6 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -129,7 +113,6 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -137,7 +120,6 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
@ -145,7 +127,6 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -153,7 +134,6 @@
},
{
"BriefDescription": "L2 cacheable instruction fetch requests",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "L2_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -161,7 +141,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@ -169,7 +148,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@ -177,7 +155,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@ -185,7 +162,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@ -193,7 +169,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@ -201,7 +176,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@ -209,7 +183,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@ -217,7 +190,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@ -225,7 +197,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@ -233,7 +204,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@ -241,7 +211,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@ -249,7 +218,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@ -257,7 +225,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@ -265,7 +232,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@ -273,7 +239,6 @@
},
{
"BriefDescription": "L2 cache reads",
"Counter": "0,1",
"EventCode": "0x29",
"EventName": "L2_LD.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@ -281,7 +246,6 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -289,7 +253,6 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -297,7 +260,6 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.MESI",
"SampleAfterValue": "200000",
@ -305,7 +267,6 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -313,7 +274,6 @@
},
{
"BriefDescription": "All read requests from L1 instruction and data caches",
"Counter": "0,1",
"EventCode": "0x2D",
"EventName": "L2_LD_IFETCH.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -321,7 +281,6 @@
},
{
"BriefDescription": "L2 cache misses.",
"Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.ANY",
"SampleAfterValue": "200000",
@ -329,7 +288,6 @@
},
{
"BriefDescription": "L2 cache misses.",
"Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.DEMAND",
"SampleAfterValue": "200000",
@ -337,7 +295,6 @@
},
{
"BriefDescription": "L2 cache misses.",
"Counter": "0,1",
"EventCode": "0x24",
"EventName": "L2_LINES_IN.SELF.PREFETCH",
"SampleAfterValue": "200000",
@ -345,7 +302,6 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
@ -353,7 +309,6 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
@ -361,7 +316,6 @@
},
{
"BriefDescription": "L2 cache lines evicted.",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "L2_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
@ -369,7 +323,6 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -377,7 +330,6 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -385,7 +337,6 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.MESI",
"SampleAfterValue": "200000",
@ -393,7 +344,6 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -401,7 +351,6 @@
},
{
"BriefDescription": "L2 locked accesses",
"Counter": "0,1",
"EventCode": "0x2B",
"EventName": "L2_LOCK.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -409,7 +358,6 @@
},
{
"BriefDescription": "L2 cache line modifications.",
"Counter": "0,1",
"EventCode": "0x25",
"EventName": "L2_M_LINES_IN.SELF",
"SampleAfterValue": "200000",
@ -417,7 +365,6 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.ANY",
"SampleAfterValue": "200000",
@ -425,7 +372,6 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.DEMAND",
"SampleAfterValue": "200000",
@ -433,7 +379,6 @@
},
{
"BriefDescription": "Modified lines evicted from the L2 cache",
"Counter": "0,1",
"EventCode": "0x27",
"EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
"SampleAfterValue": "200000",
@ -441,7 +386,6 @@
},
{
"BriefDescription": "Cycles no L2 cache requests are pending",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "L2_NO_REQ.SELF",
"SampleAfterValue": "200000",
@ -449,7 +393,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@ -457,7 +400,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@ -465,7 +407,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@ -473,7 +414,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@ -481,7 +421,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@ -489,7 +428,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@ -497,7 +435,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@ -505,7 +442,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@ -513,7 +449,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@ -521,7 +456,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@ -529,7 +463,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@ -537,7 +470,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@ -545,7 +477,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@ -553,7 +484,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@ -561,7 +491,6 @@
},
{
"BriefDescription": "Rejected L2 cache requests",
"Counter": "0,1",
"EventCode": "0x30",
"EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@ -569,7 +498,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.E_STATE",
"SampleAfterValue": "200000",
@ -577,7 +505,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.I_STATE",
"SampleAfterValue": "200000",
@ -585,7 +512,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.MESI",
"SampleAfterValue": "200000",
@ -593,7 +519,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.M_STATE",
"SampleAfterValue": "200000",
@ -601,7 +526,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.ANY.S_STATE",
"SampleAfterValue": "200000",
@ -609,7 +533,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
"SampleAfterValue": "200000",
@ -617,7 +540,6 @@
},
{
"BriefDescription": "L2 cache demand requests from this core that missed the L2",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
"SampleAfterValue": "200000",
@ -625,7 +547,6 @@
},
{
"BriefDescription": "L2 cache demand requests from this core",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.MESI",
"SampleAfterValue": "200000",
@ -633,7 +554,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
"SampleAfterValue": "200000",
@ -641,7 +561,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
"SampleAfterValue": "200000",
@ -649,7 +568,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
"SampleAfterValue": "200000",
@ -657,7 +575,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
"SampleAfterValue": "200000",
@ -665,7 +582,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
"SampleAfterValue": "200000",
@ -673,7 +589,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
"SampleAfterValue": "200000",
@ -681,7 +596,6 @@
},
{
"BriefDescription": "L2 cache requests",
"Counter": "0,1",
"EventCode": "0x2E",
"EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
"SampleAfterValue": "200000",
@ -689,7 +603,6 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.E_STATE",
"SampleAfterValue": "200000",
@ -697,7 +610,6 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.I_STATE",
"SampleAfterValue": "200000",
@ -705,7 +617,6 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.MESI",
"SampleAfterValue": "200000",
@ -713,7 +624,6 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.M_STATE",
"SampleAfterValue": "200000",
@ -721,7 +631,6 @@
},
{
"BriefDescription": "L2 store requests",
"Counter": "0,1",
"EventCode": "0x2A",
"EventName": "L2_ST.SELF.S_STATE",
"SampleAfterValue": "200000",
@ -729,7 +638,6 @@
},
{
"BriefDescription": "Retired loads that hit the L2 cache (precise event).",
"Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"SampleAfterValue": "200000",
@ -737,7 +645,6 @@
},
{
"BriefDescription": "Retired loads that miss the L2 cache",
"Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"SampleAfterValue": "10000",

47
tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "Floating point assists for retired operations.",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "FP_ASSIST.AR",
"SampleAfterValue": "10000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "Floating point assists.",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "FP_ASSIST.S",
"SampleAfterValue": "10000",
@ -17,15 +15,12 @@
},
{
"BriefDescription": "SIMD assists invoked.",
"Counter": "0,1",
"EventCode": "0xCD",
"EventName": "SIMD_ASSIST",
"SampleAfterValue": "100000",
"UMask": "0x0"
"SampleAfterValue": "100000"
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
@ -33,7 +28,6 @@
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
@ -41,7 +35,6 @@
},
{
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
"EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
@ -49,15 +42,12 @@
},
{
"BriefDescription": "SIMD Instructions retired.",
"Counter": "0,1",
"EventCode": "0xCE",
"EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000",
@ -65,7 +55,6 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000",
@ -73,7 +62,6 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000",
@ -81,7 +69,6 @@
},
{
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
"Counter": "0,1",
"EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000",
@ -89,15 +76,12 @@
},
{
"BriefDescription": "Saturated arithmetic instructions retired.",
"Counter": "0,1",
"EventCode": "0xCF",
"EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000",
@ -105,15 +89,12 @@
},
{
"BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
"Counter": "0,1",
"EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD micro-ops retired (excluding stores).",
"Counter": "0,1",
"EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.AR",
"PEBS": "2",
@ -122,15 +103,12 @@
},
{
"BriefDescription": "SIMD micro-ops executed (excluding stores).",
"Counter": "0,1",
"EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "SIMD packed arithmetic micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000",
@ -138,7 +116,6 @@
},
{
"BriefDescription": "SIMD packed arithmetic micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000",
@ -146,7 +123,6 @@
},
{
"BriefDescription": "SIMD packed logical micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000",
@ -154,7 +130,6 @@
},
{
"BriefDescription": "SIMD packed logical micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000",
@ -162,7 +137,6 @@
},
{
"BriefDescription": "SIMD packed multiply micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000",
@ -170,7 +144,6 @@
},
{
"BriefDescription": "SIMD packed multiply micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000",
@ -178,7 +151,6 @@
},
{
"BriefDescription": "SIMD packed micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000",
@ -186,7 +158,6 @@
},
{
"BriefDescription": "SIMD packed micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000",
@ -194,7 +165,6 @@
},
{
"BriefDescription": "SIMD packed shift micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000",
@ -202,7 +172,6 @@
},
{
"BriefDescription": "SIMD packed shift micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000",
@ -210,7 +179,6 @@
},
{
"BriefDescription": "SIMD unpacked micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000",
@ -218,7 +186,6 @@
},
{
"BriefDescription": "SIMD unpacked micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000",
@ -226,7 +193,6 @@
},
{
"BriefDescription": "Floating point computational micro-ops retired.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.AR",
"PEBS": "2",
@ -235,7 +201,6 @@
},
{
"BriefDescription": "Floating point computational micro-ops executed.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.S",
"SampleAfterValue": "2000000",
@ -243,7 +208,6 @@
},
{
"BriefDescription": "FXCH uops retired.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.AR",
"PEBS": "2",
@ -252,7 +216,6 @@
},
{
"BriefDescription": "FXCH uops executed.",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000",

11
tools/perf/pmu-events/arch/x86/bonnell/frontend.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "BACLEARS asserted.",
"Counter": "0,1",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "2000000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "Cycles during which instruction fetches are stalled.",
"Counter": "0,1",
"EventCode": "0x86",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "2000000",
@ -17,7 +15,6 @@
},
{
"BriefDescription": "Decode stall due to IQ full",
"Counter": "0,1",
"EventCode": "0x87",
"EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
@ -25,7 +22,6 @@
},
{
"BriefDescription": "Decode stall due to PFB empty",
"Counter": "0,1",
"EventCode": "0x87",
"EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000",
@ -33,7 +29,6 @@
},
{
"BriefDescription": "Instruction fetches.",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200000",
@ -41,7 +36,6 @@
},
{
"BriefDescription": "Icache hit",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200000",
@ -49,7 +43,6 @@
},
{
"BriefDescription": "Icache miss",
"Counter": "0,1",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200000",
@ -57,7 +50,6 @@
},
{
"BriefDescription": "All Instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000",
@ -65,7 +57,6 @@
},
{
"BriefDescription": "CISC macro instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000",
@ -73,7 +64,6 @@
},
{
"BriefDescription": "Non-CISC nacro instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA",
"EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000",
@ -81,7 +71,6 @@
},
{
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
"Counter": "0,1",
"CounterMask": "1",
"EventCode": "0xA9",
"EventName": "UOPS.MS_CYCLES",

19
tools/perf/pmu-events/arch/x86/bonnell/memory.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "Nonzero segbase 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "Nonzero segbase load 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000",
@ -17,7 +15,6 @@
},
{
"BriefDescription": "Load splits",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000",
@ -25,7 +22,6 @@
},
{
"BriefDescription": "Load splits (At Retirement)",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000",
@ -33,7 +29,6 @@
},
{
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000",
@ -41,7 +36,6 @@
},
{
"BriefDescription": "ld-op-st splits",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000",
@ -49,7 +43,6 @@
},
{
"BriefDescription": "Memory references that cross an 8-byte boundary.",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000",
@ -57,7 +50,6 @@
},
{
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000",
@ -65,7 +57,6 @@
},
{
"BriefDescription": "Nonzero segbase store 1 bubble",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000",
@ -73,7 +64,6 @@
},
{
"BriefDescription": "Store splits",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000",
@ -81,7 +71,6 @@
},
{
"BriefDescription": "Store splits (Ar Retirement)",
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000",
@ -89,7 +78,6 @@
},
{
"BriefDescription": "L1 hardware prefetch request",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "2000000",
@ -97,7 +85,6 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000",
@ -105,7 +92,6 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000",
@ -113,7 +99,6 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000",
@ -121,7 +106,6 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "200000",
@ -129,7 +113,6 @@
},
{
"BriefDescription": "Any Software prefetch",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000",
@ -137,7 +120,6 @@
},
{
"BriefDescription": "Any Software prefetch",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000",
@ -145,7 +127,6 @@
},
{
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000",

74
tools/perf/pmu-events/arch/x86/bonnell/other.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "Bus queue is empty.",
"Counter": "0,1",
"EventCode": "0x7D",
"EventName": "BUSQ_EMPTY.SELF",
"SampleAfterValue": "200000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "Number of Bus Not Ready signals asserted.",
"Counter": "0,1",
"EventCode": "0x61",
"EventName": "BUS_BNR_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -17,15 +15,12 @@
},
{
"BriefDescription": "Number of Bus Not Ready signals asserted.",
"Counter": "0,1",
"EventCode": "0x61",
"EventName": "BUS_BNR_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Bus cycles while processor receives data.",
"Counter": "0,1",
"EventCode": "0x64",
"EventName": "BUS_DATA_RCV.SELF",
"SampleAfterValue": "200000",
@ -33,7 +28,6 @@
},
{
"BriefDescription": "Bus cycles when data is sent on the bus.",
"Counter": "0,1",
"EventCode": "0x62",
"EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -41,15 +35,12 @@
},
{
"BriefDescription": "Bus cycles when data is sent on the bus.",
"Counter": "0,1",
"EventCode": "0x62",
"EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "HITM signal asserted.",
"Counter": "0,1",
"EventCode": "0x7B",
"EventName": "BUS_HITM_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -57,15 +48,12 @@
},
{
"BriefDescription": "HITM signal asserted.",
"Counter": "0,1",
"EventCode": "0x7B",
"EventName": "BUS_HITM_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "HIT signal asserted.",
"Counter": "0,1",
"EventCode": "0x7A",
"EventName": "BUS_HIT_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -73,15 +61,12 @@
},
{
"BriefDescription": "HIT signal asserted.",
"Counter": "0,1",
"EventCode": "0x7A",
"EventName": "BUS_HIT_DRV.THIS_AGENT",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "IO requests waiting in the bus queue.",
"Counter": "0,1",
"EventCode": "0x7F",
"EventName": "BUS_IO_WAIT.SELF",
"SampleAfterValue": "200000",
@ -89,7 +74,6 @@
},
{
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
"Counter": "0,1",
"EventCode": "0x63",
"EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -97,7 +81,6 @@
},
{
"BriefDescription": "Bus cycles when a LOCK signal is asserted.",
"Counter": "0,1",
"EventCode": "0x63",
"EventName": "BUS_LOCK_CLOCKS.SELF",
"SampleAfterValue": "200000",
@ -105,7 +88,6 @@
},
{
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
"Counter": "0,1",
"EventCode": "0x60",
"EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -113,7 +95,6 @@
},
{
"BriefDescription": "Outstanding cacheable data read bus requests duration.",
"Counter": "0,1",
"EventCode": "0x60",
"EventName": "BUS_REQUEST_OUTSTANDING.SELF",
"SampleAfterValue": "200000",
@ -121,7 +102,6 @@
},
{
"BriefDescription": "All bus transactions.",
"Counter": "0,1",
"EventCode": "0x70",
"EventName": "BUS_TRANS_ANY.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -129,7 +109,6 @@
},
{
"BriefDescription": "All bus transactions.",
"Counter": "0,1",
"EventCode": "0x70",
"EventName": "BUS_TRANS_ANY.SELF",
"SampleAfterValue": "200000",
@ -137,7 +116,6 @@
},
{
"BriefDescription": "Burst read bus transactions.",
"Counter": "0,1",
"EventCode": "0x65",
"EventName": "BUS_TRANS_BRD.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -145,7 +123,6 @@
},
{
"BriefDescription": "Burst read bus transactions.",
"Counter": "0,1",
"EventCode": "0x65",
"EventName": "BUS_TRANS_BRD.SELF",
"SampleAfterValue": "200000",
@ -153,7 +130,6 @@
},
{
"BriefDescription": "Burst (full cache-line) bus transactions.",
"Counter": "0,1",
"EventCode": "0x6E",
"EventName": "BUS_TRANS_BURST.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -161,7 +137,6 @@
},
{
"BriefDescription": "Burst (full cache-line) bus transactions.",
"Counter": "0,1",
"EventCode": "0x6E",
"EventName": "BUS_TRANS_BURST.SELF",
"SampleAfterValue": "200000",
@ -169,7 +144,6 @@
},
{
"BriefDescription": "Deferred bus transactions.",
"Counter": "0,1",
"EventCode": "0x6D",
"EventName": "BUS_TRANS_DEF.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -177,7 +151,6 @@
},
{
"BriefDescription": "Deferred bus transactions.",
"Counter": "0,1",
"EventCode": "0x6D",
"EventName": "BUS_TRANS_DEF.SELF",
"SampleAfterValue": "200000",
@ -185,7 +158,6 @@
},
{
"BriefDescription": "Instruction-fetch bus transactions.",
"Counter": "0,1",
"EventCode": "0x68",
"EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -193,7 +165,6 @@
},
{
"BriefDescription": "Instruction-fetch bus transactions.",
"Counter": "0,1",
"EventCode": "0x68",
"EventName": "BUS_TRANS_IFETCH.SELF",
"SampleAfterValue": "200000",
@ -201,7 +172,6 @@
},
{
"BriefDescription": "Invalidate bus transactions.",
"Counter": "0,1",
"EventCode": "0x69",
"EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -209,7 +179,6 @@
},
{
"BriefDescription": "Invalidate bus transactions.",
"Counter": "0,1",
"EventCode": "0x69",
"EventName": "BUS_TRANS_INVAL.SELF",
"SampleAfterValue": "200000",
@ -217,7 +186,6 @@
},
{
"BriefDescription": "IO bus transactions.",
"Counter": "0,1",
"EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -225,7 +193,6 @@
},
{
"BriefDescription": "IO bus transactions.",
"Counter": "0,1",
"EventCode": "0x6C",
"EventName": "BUS_TRANS_IO.SELF",
"SampleAfterValue": "200000",
@ -233,7 +200,6 @@
},
{
"BriefDescription": "Memory bus transactions.",
"Counter": "0,1",
"EventCode": "0x6F",
"EventName": "BUS_TRANS_MEM.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -241,7 +207,6 @@
},
{
"BriefDescription": "Memory bus transactions.",
"Counter": "0,1",
"EventCode": "0x6F",
"EventName": "BUS_TRANS_MEM.SELF",
"SampleAfterValue": "200000",
@ -249,7 +214,6 @@
},
{
"BriefDescription": "Partial bus transactions.",
"Counter": "0,1",
"EventCode": "0x6B",
"EventName": "BUS_TRANS_P.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -257,7 +221,6 @@
},
{
"BriefDescription": "Partial bus transactions.",
"Counter": "0,1",
"EventCode": "0x6B",
"EventName": "BUS_TRANS_P.SELF",
"SampleAfterValue": "200000",
@ -265,7 +228,6 @@
},
{
"BriefDescription": "Partial write bus transaction.",
"Counter": "0,1",
"EventCode": "0x6A",
"EventName": "BUS_TRANS_PWR.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -273,7 +235,6 @@
},
{
"BriefDescription": "Partial write bus transaction.",
"Counter": "0,1",
"EventCode": "0x6A",
"EventName": "BUS_TRANS_PWR.SELF",
"SampleAfterValue": "200000",
@ -281,7 +242,6 @@
},
{
"BriefDescription": "RFO bus transactions.",
"Counter": "0,1",
"EventCode": "0x66",
"EventName": "BUS_TRANS_RFO.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -289,7 +249,6 @@
},
{
"BriefDescription": "RFO bus transactions.",
"Counter": "0,1",
"EventCode": "0x66",
"EventName": "BUS_TRANS_RFO.SELF",
"SampleAfterValue": "200000",
@ -297,7 +256,6 @@
},
{
"BriefDescription": "Explicit writeback bus transactions.",
"Counter": "0,1",
"EventCode": "0x67",
"EventName": "BUS_TRANS_WB.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -305,7 +263,6 @@
},
{
"BriefDescription": "Explicit writeback bus transactions.",
"Counter": "0,1",
"EventCode": "0x67",
"EventName": "BUS_TRANS_WB.SELF",
"SampleAfterValue": "200000",
@ -313,7 +270,6 @@
},
{
"BriefDescription": "Cycles during which interrupts are disabled.",
"Counter": "0,1",
"EventCode": "0xC6",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
"SampleAfterValue": "2000000",
@ -321,7 +277,6 @@
},
{
"BriefDescription": "Cycles during which interrupts are pending and disabled.",
"Counter": "0,1",
"EventCode": "0xC6",
"EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
"SampleAfterValue": "2000000",
@ -329,7 +284,6 @@
},
{
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
"Counter": "0,1",
"EventCode": "0x9",
"EventName": "DISPATCH_BLOCKED.ANY",
"SampleAfterValue": "200000",
@ -337,15 +291,12 @@
},
{
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
"Counter": "0,1",
"EventCode": "0x3A",
"EventName": "EIST_TRANS",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
"SampleAfterValue": "200000",
@ -353,7 +304,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
"SampleAfterValue": "200000",
@ -361,7 +311,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
"SampleAfterValue": "200000",
@ -369,7 +318,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
"SampleAfterValue": "200000",
@ -377,7 +325,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.ANY",
"SampleAfterValue": "200000",
@ -385,7 +332,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
"SampleAfterValue": "200000",
@ -393,7 +339,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.HIT",
"SampleAfterValue": "200000",
@ -401,7 +346,6 @@
},
{
"BriefDescription": "External snoops.",
"Counter": "0,1",
"EventCode": "0x77",
"EventName": "EXT_SNOOP.THIS_AGENT.HITM",
"SampleAfterValue": "200000",
@ -409,15 +353,12 @@
},
{
"BriefDescription": "Hardware interrupts received.",
"Counter": "0,1",
"EventCode": "0xC8",
"EventName": "HW_INT_RCV",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Number of segment register loads.",
"Counter": "0,1",
"EventCode": "0x6",
"EventName": "SEGMENT_REG_LOADS.ANY",
"SampleAfterValue": "200000",
@ -425,7 +366,6 @@
},
{
"BriefDescription": "Bus stalled for snoops.",
"Counter": "0,1",
"EventCode": "0x7E",
"EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
"SampleAfterValue": "200000",
@ -433,7 +373,6 @@
},
{
"BriefDescription": "Bus stalled for snoops.",
"Counter": "0,1",
"EventCode": "0x7E",
"EventName": "SNOOP_STALL_DRV.SELF",
"SampleAfterValue": "200000",
@ -441,7 +380,6 @@
},
{
"BriefDescription": "Number of thermal trips",
"Counter": "0,1",
"EventCode": "0x3B",
"EventName": "THERMAL_TRIP",
"SampleAfterValue": "200000",

65
tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "Bogus branches",
"Counter": "0,1",
"EventCode": "0xE4",
"EventName": "BOGUS_BR",
"SampleAfterValue": "2000000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "Branch instructions decoded",
"Counter": "0,1",
"EventCode": "0xE0",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
@ -17,15 +15,12 @@
},
{
"BriefDescription": "Retired branch instructions.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ANY",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Retired branch instructions.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ANY1",
"SampleAfterValue": "2000000",
@ -33,16 +28,13 @@
},
{
"BriefDescription": "Retired mispredicted branch instructions (precise event).",
"Counter": "0,1",
"EventCode": "0xC5",
"EventName": "BR_INST_RETIRED.MISPRED",
"PEBS": "1",
"SampleAfterValue": "200000",
"UMask": "0x0"
"SampleAfterValue": "200000"
},
{
"BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
"SampleAfterValue": "200000",
@ -50,7 +42,6 @@
},
{
"BriefDescription": "Retired branch instructions that were mispredicted taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
"SampleAfterValue": "200000",
@ -58,7 +49,6 @@
},
{
"BriefDescription": "Retired branch instructions that were predicted not-taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
"SampleAfterValue": "2000000",
@ -66,7 +56,6 @@
},
{
"BriefDescription": "Retired branch instructions that were predicted taken.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.PRED_TAKEN",
"SampleAfterValue": "2000000",
@ -74,7 +63,6 @@
},
{
"BriefDescription": "Retired taken branch instructions.",
"Counter": "0,1",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "2000000",
@ -82,7 +70,6 @@
},
{
"BriefDescription": "All macro conditional branch instructions.",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND",
"SampleAfterValue": "2000000",
@ -90,7 +77,6 @@
},
{
"BriefDescription": "Only taken macro conditional branch instructions",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "2000000",
@ -98,7 +84,6 @@
},
{
"BriefDescription": "All non-indirect calls",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
"SampleAfterValue": "2000000",
@ -106,7 +91,6 @@
},
{
"BriefDescription": "All indirect branches that are not calls.",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.IND",
"SampleAfterValue": "2000000",
@ -114,7 +98,6 @@
},
{
"BriefDescription": "All indirect calls, including both register and memory indirect.",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "2000000",
@ -122,7 +105,6 @@
},
{
"BriefDescription": "All indirect branches that have a return mnemonic",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.RET",
"SampleAfterValue": "2000000",
@ -130,7 +112,6 @@
},
{
"BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
"Counter": "0,1",
"EventCode": "0x88",
"EventName": "BR_INST_TYPE_RETIRED.UNCOND",
"SampleAfterValue": "2000000",
@ -138,7 +119,6 @@
},
{
"BriefDescription": "Mispredicted cond branch instructions retired",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND",
"SampleAfterValue": "200000",
@ -146,7 +126,6 @@
},
{
"BriefDescription": "Mispredicted and taken cond branch instructions retired",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
"SampleAfterValue": "200000",
@ -154,7 +133,6 @@
},
{
"BriefDescription": "Mispredicted ind branches that are not calls",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND",
"SampleAfterValue": "200000",
@ -162,7 +140,6 @@
},
{
"BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
"SampleAfterValue": "200000",
@ -170,7 +147,6 @@
},
{
"BriefDescription": "Mispredicted return branches",
"Counter": "0,1",
"EventCode": "0x89",
"EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
"SampleAfterValue": "200000",
@ -178,7 +154,6 @@
},
{
"BriefDescription": "Bus cycles when core is not halted",
"Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.BUS",
"SampleAfterValue": "200000",
@ -186,31 +161,24 @@
},
{
"BriefDescription": "Core cycles when core is not halted",
"Counter": "Fixed counter 2",
"EventCode": "0xA",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Core cycles when core is not halted",
"Counter": "0,1",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Reference cycles when core is not halted.",
"Counter": "Fixed counter 3",
"EventCode": "0xA",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Cycles the divider is busy.",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
@ -218,7 +186,6 @@
},
{
"BriefDescription": "Divide operations retired",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "DIV.AR",
"SampleAfterValue": "2000000",
@ -226,7 +193,6 @@
},
{
"BriefDescription": "Divide operations executed.",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "DIV.S",
"SampleAfterValue": "2000000",
@ -234,24 +200,19 @@
},
{
"BriefDescription": "Instructions retired.",
"Counter": "Fixed counter 1",
"EventCode": "0xA",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Instructions retired (precise event).",
"Counter": "0,1",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "2",
"SampleAfterValue": "2000000",
"UMask": "0x0"
"SampleAfterValue": "2000000"
},
{
"BriefDescription": "Self-Modifying Code detected.",
"Counter": "0,1",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200000",
@ -259,7 +220,6 @@
},
{
"BriefDescription": "Multiply operations retired",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "MUL.AR",
"SampleAfterValue": "2000000",
@ -267,7 +227,6 @@
},
{
"BriefDescription": "Multiply operations executed.",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "MUL.S",
"SampleAfterValue": "2000000",
@ -275,7 +234,6 @@
},
{
"BriefDescription": "Micro-op reissues for any cause",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.ANY",
"SampleAfterValue": "200000",
@ -283,7 +241,6 @@
},
{
"BriefDescription": "Micro-op reissues for any cause (At Retirement)",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.ANY.AR",
"SampleAfterValue": "200000",
@ -291,7 +248,6 @@
},
{
"BriefDescription": "Micro-op reissues on a store-load collision",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.OVERLAP_STORE",
"SampleAfterValue": "200000",
@ -299,7 +255,6 @@
},
{
"BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "REISSUE.OVERLAP_STORE.AR",
"SampleAfterValue": "200000",
@ -307,7 +262,6 @@
},
{
"BriefDescription": "Cycles issue is stalled due to div busy.",
"Counter": "0,1",
"EventCode": "0xDC",
"EventName": "RESOURCE_STALLS.DIV_BUSY",
"SampleAfterValue": "2000000",
@ -315,7 +269,6 @@
},
{
"BriefDescription": "All store forwards",
"Counter": "0,1",
"EventCode": "0x2",
"EventName": "STORE_FORWARDS.ANY",
"SampleAfterValue": "200000",
@ -323,7 +276,6 @@
},
{
"BriefDescription": "Good store forwards",
"Counter": "0,1",
"EventCode": "0x2",
"EventName": "STORE_FORWARDS.GOOD",
"SampleAfterValue": "200000",
@ -331,7 +283,6 @@
},
{
"BriefDescription": "Micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"SampleAfterValue": "2000000",
@ -339,7 +290,6 @@
},
{
"BriefDescription": "Cycles no micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALLED_CYCLES",
"SampleAfterValue": "2000000",
@ -347,7 +297,6 @@
},
{
"BriefDescription": "Periods no micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALLS",
"SampleAfterValue": "2000000",

15
tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "Memory accesses that missed the DTLB.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "DTLB misses due to load operations.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000",
@ -17,7 +15,6 @@
},
{
"BriefDescription": "DTLB misses due to store operations.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000",
@ -25,7 +22,6 @@
},
{
"BriefDescription": "L0 DTLB misses due to load operations.",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000",
@ -33,7 +29,6 @@
},
{
"BriefDescription": "L0 DTLB misses due to store operations",
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000",
@ -41,7 +36,6 @@
},
{
"BriefDescription": "ITLB flushes.",
"Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000",
@ -49,7 +43,6 @@
},
{
"BriefDescription": "ITLB hits.",
"Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.HIT",
"SampleAfterValue": "200000",
@ -57,7 +50,6 @@
},
{
"BriefDescription": "ITLB misses.",
"Counter": "0,1",
"EventCode": "0x82",
"EventName": "ITLB.MISSES",
"PEBS": "2",
@ -66,7 +58,6 @@
},
{
"BriefDescription": "Retired loads that miss the DTLB (precise event).",
"Counter": "0,1",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
@ -75,7 +66,6 @@
},
{
"BriefDescription": "Duration of page-walks in core cycles",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "2000000",
@ -83,7 +73,6 @@
},
{
"BriefDescription": "Duration of D-side only page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000",
@ -91,7 +80,6 @@
},
{
"BriefDescription": "Number of D-side only page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000",
@ -99,7 +87,6 @@
},
{
"BriefDescription": "Duration of I-Side page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "2000000",
@ -107,7 +94,6 @@
},
{
"BriefDescription": "Number of I-Side page walks",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000",
@ -115,7 +101,6 @@
},
{
"BriefDescription": "Number of page-walks executed.",
"Counter": "0,1",
"EventCode": "0xC",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000",

137
tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json
View File

@ -110,7 +110,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@ -118,7 +118,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
@ -142,7 +142,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@ -174,7 +174,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
"MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
@ -214,7 +214,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
"MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@ -222,7 +222,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
"MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
@ -230,7 +230,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
"MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
@ -238,7 +238,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
"MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
@ -246,7 +246,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
"MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@ -254,7 +254,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
"MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
@ -286,7 +286,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
"MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
@ -334,7 +334,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@ -342,7 +342,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@ -350,7 +350,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
@ -358,7 +358,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
@ -366,14 +366,14 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%"
@ -429,7 +429,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
"MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
"MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@ -522,7 +522,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
"MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
@ -595,26 +595,26 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
"MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
"MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
"MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@ -656,13 +656,13 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@ -715,7 +715,7 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
"MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
@ -727,13 +727,13 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
"MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
"MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
@ -745,43 +745,43 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
@ -794,19 +794,19 @@
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
@ -836,19 +836,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
"MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@ -861,7 +861,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@ -879,68 +879,87 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
"MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricExpr": "MEM_Parallel_Requests",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "UNC_CLOCK.SOCKET",
"MetricGroup": "SoC",
"MetricName": "Socket_CLKS"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
{
"BriefDescription": "Uncore frequency per die [GHZ]",
"MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
"MetricGroup": "SoC",
"MetricName": "UNCORE_FREQ"
},
{
"BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C3_Core_Residency"
"MetricName": "C3_Core_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C6_Core_Residency"
"MetricName": "C6_Core_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C7_Core_Residency"
"MetricName": "C7_Core_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency"
"MetricName": "C2_Pkg_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C3_Pkg_Residency"
"MetricName": "C3_Pkg_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency"
"MetricName": "C6_Pkg_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C7_Pkg_Residency"
"MetricName": "C7_Pkg_Residency",
"ScaleUnit": "100%"
}
]

957
tools/perf/pmu-events/arch/x86/broadwell/cache.json
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40
tools/perf/pmu-events/arch/x86/broadwell/floating-point.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@ -10,8 +8,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@ -19,8 +15,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@ -28,8 +22,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@ -37,8 +29,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
@ -46,8 +36,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
@ -55,8 +43,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003",
@ -64,8 +50,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
@ -73,8 +57,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003",
@ -82,8 +64,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
@ -91,8 +71,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@ -102,8 +80,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@ -112,8 +88,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@ -122,8 +96,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@ -132,8 +104,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@ -142,8 +112,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@ -151,8 +119,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@ -160,8 +126,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@ -171,8 +135,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@ -182,8 +144,6 @@
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",

56
tools/perf/pmu-events/arch/x86/broadwell/frontend.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@ -40,8 +32,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@ -50,8 +40,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@ -61,8 +49,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@ -72,8 +58,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@ -83,8 +67,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@ -94,8 +76,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@ -105,8 +85,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@ -115,8 +93,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@ -125,8 +101,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -135,8 +109,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@ -167,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@ -178,8 +144,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -190,8 +154,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@ -200,8 +162,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@ -210,8 +170,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@ -231,8 +187,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@ -241,8 +195,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@ -252,8 +204,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@ -274,8 +222,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

890
tools/perf/pmu-events/arch/x86/broadwell/memory.json
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8
tools/perf/pmu-events/arch/x86/broadwell/other.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",

272
tools/perf/pmu-events/arch/x86/broadwell/pipeline.json
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19
tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json
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@ -1,7 +1,6 @@
[
{
"BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",
"PerPkg": "1",
@ -11,7 +10,6 @@
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in I-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",
"PerPkg": "1",
@ -21,7 +19,6 @@
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in M-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",
"PerPkg": "1",
@ -31,7 +28,6 @@
},
{
"BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",
"PerPkg": "1",
@ -41,7 +37,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",
"PerPkg": "1",
@ -51,7 +46,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in I-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",
"PerPkg": "1",
@ -61,7 +55,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
"PerPkg": "1",
@ -71,7 +64,6 @@
},
{
"BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",
"PerPkg": "1",
@ -81,7 +73,6 @@
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",
"PerPkg": "1",
@ -91,7 +82,6 @@
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
"PerPkg": "1",
@ -101,7 +91,6 @@
},
{
"BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",
"Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",
"PerPkg": "1",
@ -111,41 +100,33 @@
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",
"UMask": "0x48",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"UMask": "0x81",
"Unit": "CBO"
},
{
"BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",
"PerPkg": "1",
"PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",
"UMask": "0x41",
"Unit": "CBO"
}

25
tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json
View File

@ -1,78 +1,65 @@
[
{
"BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"Counter": "0,1",
"EventCode": "0x84",
"EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
"PerPkg": "1",
"PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",
"UMask": "0x01",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
"PerPkg": "1",
"PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
"UMask": "0x01",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
"Counter": "0,",
"CounterMask": "1",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
"PerPkg": "1",
"PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
"UMask": "0x01",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
"Counter": "0,",
"EventCode": "0x80",
"EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
"PerPkg": "1",
"PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
"UMask": "0x02",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.ALL",
"PerPkg": "1",
"PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",
"UMask": "0x01",
"UMask": "0x1",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",
"PerPkg": "1",
"PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",
"UMask": "0x02",
"UMask": "0x2",
"Unit": "ARB"
},
{
"BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"Counter": "0,1",
"EventCode": "0x81",
"EventName": "UNC_ARB_TRK_REQUESTS.WRITES",
"PerPkg": "1",
"PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",
"UMask": "0x20",
"Unit": "ARB"
},
{
"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
"Counter": "FIXED",
"EventCode": "0xff",
"EventName": "UNC_CLOCK.SOCKET",
"PerPkg": "1",

76
tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@ -12,8 +10,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003",
@ -39,8 +31,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@ -49,8 +39,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@ -60,8 +48,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@ -71,8 +57,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@ -93,8 +75,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@ -104,8 +84,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@ -122,8 +98,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@ -131,8 +105,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@ -141,8 +113,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@ -152,8 +122,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@ -163,8 +131,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@ -174,8 +140,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@ -185,8 +149,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@ -195,8 +157,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@ -205,8 +165,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@ -216,8 +174,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -225,8 +181,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@ -234,8 +188,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@ -243,8 +195,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
@ -253,8 +203,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@ -264,8 +212,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@ -275,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@ -286,8 +230,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
@ -297,8 +239,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@ -307,8 +247,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@ -317,8 +255,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@ -327,8 +263,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@ -337,8 +271,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@ -347,8 +279,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@ -357,8 +287,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@ -367,8 +295,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@ -377,8 +303,6 @@
},
{
"BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",

143
tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
View File

@ -113,7 +113,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@ -121,7 +121,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
"MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
"MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
@ -145,7 +145,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@ -177,7 +177,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
"MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@ -217,7 +217,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
"MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@ -225,7 +225,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
"MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@ -233,7 +233,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
"MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@ -241,7 +241,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
"MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@ -249,7 +249,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
"MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@ -257,7 +257,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
"MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@ -289,20 +289,12 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
"MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
"MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
"MetricName": "tma_false_sharing",
"PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"ScaleUnit": "100%"
},
{
"BriefDescription": "This metric represents rate of split store accesses",
"MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
@ -337,7 +329,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@ -345,7 +337,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@ -353,7 +345,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
@ -361,7 +353,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
@ -369,7 +361,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
"MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
@ -377,7 +369,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%"
@ -433,7 +425,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
"MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
"MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@ -526,7 +518,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
"MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
@ -599,26 +591,26 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
"MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
"MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
"MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@ -660,13 +652,13 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@ -719,7 +711,7 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
"MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
@ -731,13 +723,13 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
"MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
"MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
@ -749,68 +741,68 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) if #core_wide < 1 else ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD) )",
"MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "Page_Walks_Utilization"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
"MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
@ -840,19 +832,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
"MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
"MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@ -865,7 +857,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@ -883,22 +875,10 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
"MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Request_Latency"
},
{
"BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
"MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
"MetricGroup": "Mem;SoC",
"MetricName": "MEM_Parallel_Requests"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
@ -907,44 +887,51 @@
},
{
"BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C3_Core_Residency"
"MetricName": "C3_Core_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C6_Core_Residency"
"MetricName": "C6_Core_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C7_Core_Residency"
"MetricName": "C7_Core_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency"
"MetricName": "C2_Pkg_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C3_Pkg_Residency"
"MetricName": "C3_Pkg_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency"
"MetricName": "C6_Pkg_Residency",
"ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
"MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
"MetricName": "C7_Pkg_Residency"
"MetricName": "C7_Pkg_Residency",
"ScaleUnit": "100%"
}
]

153
tools/perf/pmu-events/arch/x86/broadwellde/cache.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
"Counter": "2",
"CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@ -53,8 +43,6 @@
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@ -63,8 +51,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@ -73,8 +59,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@ -83,8 +67,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@ -93,8 +75,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@ -103,8 +83,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@ -112,8 +90,6 @@
},
{
"BriefDescription": "L2 code requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "This event counts the total number of L2 code requests.",
@ -122,8 +98,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@ -132,8 +106,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"SampleAfterValue": "200003",
@ -141,8 +113,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"SampleAfterValue": "200003",
@ -150,8 +120,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@ -160,8 +128,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@ -170,8 +136,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@ -179,8 +143,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@ -188,8 +150,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
@ -198,8 +158,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@ -208,8 +166,6 @@
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@ -218,8 +174,6 @@
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@ -228,8 +182,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200003",
@ -237,8 +189,6 @@
},
{
"BriefDescription": "All L2 requests.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200003",
@ -246,8 +196,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@ -255,8 +203,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@ -264,8 +210,6 @@
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@ -274,8 +218,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@ -284,8 +226,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@ -294,8 +234,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@ -304,8 +242,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@ -314,8 +250,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@ -324,8 +258,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@ -334,8 +266,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@ -344,8 +274,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@ -354,8 +282,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@ -364,8 +290,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@ -374,8 +298,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -387,8 +309,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -400,8 +320,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -413,8 +331,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -425,8 +341,6 @@
"UMask": "0x8"
},
{
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70, BDM100",
"EventCode": "0xD3",
@ -438,8 +352,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@ -450,8 +362,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@ -462,8 +372,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@ -474,8 +382,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@ -486,8 +392,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@ -498,8 +402,6 @@
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@ -510,8 +412,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD1",
@ -523,8 +423,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@ -535,8 +433,6 @@
},
{
"BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD1",
@ -548,8 +444,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100, BDE70",
"EventCode": "0xD1",
@ -560,8 +454,6 @@
},
{
"BriefDescription": "All retired load uops. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@ -572,12 +464,9 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"SampleAfterValue": "2000003",
@ -585,8 +474,6 @@
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD0",
@ -598,8 +485,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@ -610,12 +495,9 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003",
@ -623,8 +505,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@ -635,12 +515,9 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"SampleAfterValue": "100003",
@ -648,8 +525,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@ -658,8 +533,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@ -668,8 +541,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@ -678,8 +549,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@ -688,8 +557,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@ -698,8 +565,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@ -709,8 +574,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@ -721,8 +584,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@ -733,8 +594,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@ -745,8 +604,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@ -756,8 +613,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@ -767,8 +622,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "BDM76",
"EventCode": "0x60",
@ -778,8 +631,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@ -789,8 +640,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
@ -798,8 +647,6 @@
},
{
"BriefDescription": "Split locks in SQ",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "This event counts the number of split locks in the super queue.",

40
tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@ -10,8 +8,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@ -19,8 +15,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@ -28,8 +22,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@ -37,8 +29,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
@ -46,8 +36,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
@ -55,8 +43,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003",
@ -64,8 +50,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
@ -73,8 +57,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003",
@ -82,8 +64,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
@ -91,8 +71,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@ -102,8 +80,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@ -112,8 +88,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@ -122,8 +96,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@ -132,8 +104,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@ -142,8 +112,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@ -151,8 +119,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@ -160,8 +126,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@ -171,8 +135,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@ -182,8 +144,6 @@
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",

56
tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@ -40,8 +32,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@ -50,8 +40,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@ -61,8 +49,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@ -72,8 +58,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@ -83,8 +67,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@ -94,8 +76,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@ -105,8 +85,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@ -115,8 +93,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@ -125,8 +101,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -135,8 +109,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@ -167,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@ -178,8 +144,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -190,8 +154,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@ -200,8 +162,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@ -210,8 +170,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@ -231,8 +187,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@ -241,8 +195,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@ -252,8 +204,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@ -274,8 +222,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

86
tools/perf/pmu-events/arch/x86/broadwellde/memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of times HLE commit succeeded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@ -92,8 +74,6 @@
},
{
"BriefDescription": "Loads with latency value being above 128",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@ -102,13 +82,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 128.",
"SampleAfterValue": "1009",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@ -117,13 +94,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 16.",
"SampleAfterValue": "20011",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@ -132,13 +106,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 256.",
"SampleAfterValue": "503",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@ -147,13 +118,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 32.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@ -162,13 +130,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above four.",
"SampleAfterValue": "100003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@ -177,13 +142,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 512.",
"SampleAfterValue": "101",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@ -192,13 +154,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 64.",
"SampleAfterValue": "2003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
"Counter": "3",
"CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@ -207,13 +166,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above eight.",
"SampleAfterValue": "50021",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@ -222,8 +178,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@ -232,8 +186,6 @@
},
{
"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@ -243,8 +195,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@ -253,8 +203,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@ -263,8 +211,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@ -273,8 +219,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
@ -283,8 +227,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@ -293,8 +235,6 @@
},
{
"BriefDescription": "Number of times RTM commit succeeded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@ -303,8 +243,6 @@
},
{
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@ -313,8 +251,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@ -322,8 +258,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@ -332,8 +266,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@ -342,8 +274,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@ -352,8 +282,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@ -361,8 +289,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@ -371,8 +297,6 @@
},
{
"BriefDescription": "Number of times a TSX line had a cache conflict",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@ -381,8 +305,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@ -391,8 +313,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@ -401,8 +321,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@ -411,8 +329,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@ -421,8 +337,6 @@
},
{
"BriefDescription": "Number of times we could not allocate Lock Buffer",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",

8
tools/perf/pmu-events/arch/x86/broadwellde/other.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",

272
tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
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414
tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
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File diff suppressed because it is too large Load Diff

477
tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
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File diff suppressed because it is too large Load Diff

163
tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
@ -11,7 +10,6 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
"Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
@ -21,7 +19,6 @@
},
{
"BriefDescription": "Clocks in the IRP",
"Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of clocks in the IRP.",
@ -29,7 +26,6 @@
},
{
"BriefDescription": "Coherent Ops; CLFlush",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
@ -39,7 +35,6 @@
},
{
"BriefDescription": "Coherent Ops; CRd",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
@ -49,7 +44,6 @@
},
{
"BriefDescription": "Coherent Ops; DRd",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
@ -59,7 +53,6 @@
},
{
"BriefDescription": "Coherent Ops; PCIDCAHin5t",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
@ -69,7 +62,6 @@
},
{
"BriefDescription": "Coherent Ops; PCIRdCur",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"PerPkg": "1",
@ -79,7 +71,6 @@
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
@ -89,7 +80,6 @@
},
{
"BriefDescription": "Coherent Ops; RFO",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
@ -99,7 +89,6 @@
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
"Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
@ -109,7 +98,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
@ -118,7 +106,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
@ -127,7 +114,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
@ -136,7 +122,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
@ -145,7 +130,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Requests",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
@ -154,7 +138,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
@ -163,7 +146,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
@ -172,7 +154,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
"Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_TIMEOUT",
"PerPkg": "1",
@ -182,7 +163,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Data Throttled",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
@ -192,7 +172,6 @@
},
{
"BriefDescription": "Misc Events - Set 1",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
@ -201,7 +180,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Received Invalid",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
@ -211,7 +189,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Received Valid",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
@ -221,7 +198,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
@ -231,7 +207,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
@ -241,7 +216,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
@ -251,7 +225,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
"Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
@ -261,7 +234,6 @@
},
{
"BriefDescription": "AK Ingress Occupancy",
"Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
@ -269,7 +241,6 @@
"Unit": "IRP"
},
{
"Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
@ -278,7 +249,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
"Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
@ -286,7 +256,6 @@
"Unit": "IRP"
},
{
"Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
@ -294,7 +263,6 @@
"Unit": "IRP"
},
{
"Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
@ -303,7 +271,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
"Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
@ -311,7 +278,6 @@
"Unit": "IRP"
},
{
"Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
@ -319,7 +285,6 @@
"Unit": "IRP"
},
{
"Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
@ -328,7 +293,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
"Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
@ -336,7 +300,6 @@
"Unit": "IRP"
},
{
"Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
@ -345,7 +308,6 @@
},
{
"BriefDescription": "Snoop Responses; Hit E or S",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
@ -354,7 +316,6 @@
},
{
"BriefDescription": "Snoop Responses; Hit I",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
@ -363,7 +324,6 @@
},
{
"BriefDescription": "Snoop Responses; Hit M",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
@ -372,7 +332,6 @@
},
{
"BriefDescription": "Snoop Responses; Miss",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
@ -381,7 +340,6 @@
},
{
"BriefDescription": "Snoop Responses; SnpCode",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
@ -390,7 +348,6 @@
},
{
"BriefDescription": "Snoop Responses; SnpData",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
@ -399,7 +356,6 @@
},
{
"BriefDescription": "Snoop Responses; SnpInv",
"Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
@ -408,7 +364,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Atomic",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
@ -418,7 +373,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Other",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
@ -428,7 +382,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
@ -438,7 +391,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
@ -448,7 +400,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
@ -458,7 +409,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Write Prefetches",
"Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
@ -468,7 +418,6 @@
},
{
"BriefDescription": "No AD Egress Credit Stalls",
"Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@ -477,7 +426,6 @@
},
{
"BriefDescription": "No BL Egress Credit Stalls",
"Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@ -486,7 +434,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
"Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
@ -495,7 +442,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
"Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
@ -504,7 +450,6 @@
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
"Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
@ -513,16 +458,42 @@
},
{
"BriefDescription": "Number of uclks in domain",
"Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R2PCIe"
},
{
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@ -532,7 +503,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@ -542,7 +512,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
"Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@ -552,7 +521,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@ -562,7 +530,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@ -572,7 +539,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
"Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@ -582,27 +548,24 @@
},
{
"BriefDescription": "R2 AD Ring in Use; All",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0xF",
"UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0xC",
"UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@ -612,7 +575,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@ -622,7 +584,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
@ -632,7 +593,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@ -642,7 +602,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@ -652,7 +611,6 @@
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
@ -662,7 +620,6 @@
},
{
"BriefDescription": "AK Ingress Bounced; Up",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
@ -672,27 +629,24 @@
},
{
"BriefDescription": "R2 AK Ring in Use; All",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0xF",
"UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0xC",
"UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@ -702,7 +656,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@ -712,7 +665,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
@ -722,7 +674,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@ -732,7 +683,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@ -742,27 +692,24 @@
},
{
"BriefDescription": "R2 BL Ring in Use; All",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0xF",
"UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0xC",
"UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@ -772,7 +719,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@ -782,7 +728,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
@ -792,7 +737,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@ -802,7 +746,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@ -812,27 +755,24 @@
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
"UMask": "0xF",
"UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
"UMask": "0xC",
"UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Clockwise",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
@ -842,7 +782,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@ -852,7 +791,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
"Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@ -862,7 +800,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCB",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
@ -872,7 +809,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCS",
"Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
@ -891,7 +827,6 @@
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
@ -901,7 +836,6 @@
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
"Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
@ -929,7 +863,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
@ -939,7 +872,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
@ -949,7 +881,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
@ -959,7 +890,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
"Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
@ -1023,7 +953,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
@ -1033,7 +962,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
@ -1043,7 +971,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
@ -1053,7 +980,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
@ -1063,7 +989,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
@ -1073,7 +998,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
"Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
@ -1083,7 +1007,6 @@
},
{
"BriefDescription": "VLW Received",
"Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
@ -1093,7 +1016,6 @@
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
@ -1103,7 +1025,6 @@
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
@ -1113,7 +1034,6 @@
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
@ -1123,7 +1043,6 @@
},
{
"BriefDescription": "Filter Match",
"Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
@ -1133,7 +1052,6 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
"Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
@ -1143,7 +1061,6 @@
},
{
"BriefDescription": "RACU Request",
"Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
@ -1152,7 +1069,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
@ -1162,7 +1078,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
@ -1172,7 +1087,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
@ -1182,7 +1096,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
@ -1192,7 +1105,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
@ -1202,7 +1114,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Other",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
@ -1212,7 +1123,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
@ -1222,7 +1132,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
"Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",

57
tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
View File

@ -1,7 +1,6 @@
[
{
"BriefDescription": "pclk Cycles",
"Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@ -9,7 +8,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
@ -18,7 +16,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
@ -27,7 +24,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
@ -36,7 +32,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
@ -45,7 +40,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
@ -54,7 +48,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
@ -63,7 +56,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
@ -72,7 +64,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
@ -81,7 +72,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
@ -90,7 +80,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
@ -99,7 +88,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
@ -108,7 +96,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
@ -117,7 +104,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
@ -126,7 +112,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
@ -135,7 +120,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
@ -144,7 +128,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
@ -153,7 +136,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
@ -162,7 +144,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
@ -171,7 +152,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
@ -180,7 +160,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
@ -189,7 +168,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
@ -198,7 +176,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
@ -207,7 +184,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
@ -216,7 +192,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
@ -225,7 +200,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
@ -234,7 +208,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
@ -243,7 +216,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
@ -252,7 +224,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
@ -261,7 +232,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
@ -270,7 +240,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
@ -279,7 +248,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
@ -288,7 +256,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
@ -297,7 +264,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
@ -306,7 +272,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
@ -315,7 +280,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
@ -324,7 +288,6 @@
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
@ -333,7 +296,6 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
@ -342,7 +304,6 @@
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
@ -351,7 +312,6 @@
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
@ -360,7 +320,6 @@
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
@ -369,7 +328,6 @@
},
{
"BriefDescription": "Cycles spent changing Frequency",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
@ -378,7 +336,6 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
@ -387,7 +344,6 @@
},
{
"BriefDescription": "Package C State Residency - C0",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
@ -396,7 +352,6 @@
},
{
"BriefDescription": "Package C State Residency - C1E",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
@ -405,7 +360,6 @@
},
{
"BriefDescription": "Package C State Residency - C2E",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
@ -414,7 +368,6 @@
},
{
"BriefDescription": "Package C State Residency - C3",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
@ -423,7 +376,6 @@
},
{
"BriefDescription": "Package C State Residency - C6",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
@ -432,7 +384,6 @@
},
{
"BriefDescription": "Package C7 State Residency",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
@ -441,7 +392,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
@ -450,7 +400,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
@ -459,7 +408,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
@ -468,7 +416,6 @@
},
{
"BriefDescription": "External Prochot",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
@ -477,7 +424,6 @@
},
{
"BriefDescription": "Internal Prochot",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
@ -486,7 +432,6 @@
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
@ -494,7 +439,6 @@
"Unit": "PCU"
},
{
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
@ -503,7 +447,6 @@
},
{
"BriefDescription": "VR Hot",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",

76
tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@ -12,8 +10,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003",
@ -39,8 +31,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@ -49,8 +39,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@ -60,8 +48,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@ -71,8 +57,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@ -93,8 +75,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@ -104,8 +84,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@ -122,8 +98,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@ -131,8 +105,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@ -141,8 +113,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@ -152,8 +122,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@ -163,8 +131,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@ -174,8 +140,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@ -185,8 +149,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@ -195,8 +157,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@ -205,8 +165,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@ -216,8 +174,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -225,8 +181,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@ -234,8 +188,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@ -243,8 +195,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
@ -253,8 +203,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@ -264,8 +212,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@ -275,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@ -286,8 +230,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
@ -297,8 +239,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@ -307,8 +247,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@ -317,8 +255,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@ -327,8 +263,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@ -337,8 +271,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@ -347,8 +279,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@ -357,8 +287,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@ -367,8 +295,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@ -377,8 +303,6 @@
},
{
"BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",

1381
tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
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191
tools/perf/pmu-events/arch/x86/broadwellx/cache.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
"Counter": "2",
"CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@ -53,8 +43,6 @@
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@ -63,8 +51,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@ -73,8 +59,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@ -83,8 +67,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@ -93,8 +75,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@ -103,8 +83,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@ -112,8 +90,6 @@
},
{
"BriefDescription": "L2 code requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "This event counts the total number of L2 code requests.",
@ -122,8 +98,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@ -132,8 +106,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"SampleAfterValue": "200003",
@ -141,8 +113,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"SampleAfterValue": "200003",
@ -150,8 +120,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@ -160,8 +128,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@ -170,8 +136,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@ -179,8 +143,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@ -188,8 +150,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
@ -198,8 +158,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@ -208,8 +166,6 @@
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@ -218,8 +174,6 @@
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@ -228,8 +182,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200003",
@ -237,8 +189,6 @@
},
{
"BriefDescription": "All L2 requests.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200003",
@ -246,8 +196,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@ -255,8 +203,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@ -264,8 +210,6 @@
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@ -274,8 +218,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@ -284,8 +226,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@ -294,8 +234,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@ -304,8 +242,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@ -314,8 +250,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@ -324,8 +258,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@ -334,8 +266,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@ -344,8 +274,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@ -354,8 +282,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@ -364,8 +290,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@ -374,8 +298,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -387,8 +309,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -400,8 +320,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -413,8 +331,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@ -426,8 +342,6 @@
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70, BDM100",
"EventCode": "0xD3",
@ -439,8 +353,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@ -451,8 +363,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@ -463,8 +373,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@ -475,8 +383,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@ -487,8 +393,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@ -499,8 +403,6 @@
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@ -511,8 +413,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD1",
@ -524,8 +424,6 @@
},
{
"BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@ -536,8 +434,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD1",
@ -549,8 +445,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100, BDE70",
"EventCode": "0xD1",
@ -561,8 +455,6 @@
},
{
"BriefDescription": "All retired load uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@ -573,12 +465,9 @@
},
{
"BriefDescription": "All retired store uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"SampleAfterValue": "2000003",
@ -586,8 +475,6 @@
},
{
"BriefDescription": "Retired load uops with locked access.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD0",
@ -599,8 +486,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@ -611,12 +496,9 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003",
@ -624,8 +506,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@ -636,12 +516,9 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"SampleAfterValue": "100003",
@ -649,8 +526,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@ -659,8 +534,6 @@
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.",
@ -669,8 +542,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@ -679,8 +550,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@ -689,8 +558,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@ -699,8 +566,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@ -709,8 +574,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@ -720,8 +583,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@ -732,8 +593,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@ -744,8 +603,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@ -756,8 +613,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@ -767,8 +622,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@ -778,8 +631,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "BDM76",
"EventCode": "0x60",
@ -789,8 +640,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@ -800,8 +649,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
@ -809,152 +656,114 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0244",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests hit in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "This event counts the number of split locks in the super queue.",

40
tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -31,8 +25,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
@ -50,8 +40,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
@ -59,8 +47,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -69,8 +55,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -79,8 +63,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -89,8 +71,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
@ -98,8 +78,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@ -109,8 +87,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@ -119,8 +95,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@ -129,8 +103,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@ -139,8 +111,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@ -149,8 +119,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@ -158,8 +126,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@ -167,8 +133,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@ -178,8 +142,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@ -189,8 +151,6 @@
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",

56
tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@ -40,8 +32,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@ -50,8 +40,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@ -61,8 +49,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@ -72,8 +58,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@ -83,8 +67,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@ -94,8 +76,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@ -105,8 +85,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@ -115,8 +93,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@ -125,8 +101,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -135,8 +109,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@ -167,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@ -178,8 +144,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -190,8 +154,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@ -200,8 +162,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@ -210,8 +170,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@ -231,8 +187,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@ -241,8 +195,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@ -252,8 +204,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@ -274,8 +222,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

143
tools/perf/pmu-events/arch/x86/broadwellx/memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times HLE abort was triggered",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of times HLE commit succeeded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@ -92,8 +74,6 @@
},
{
"BriefDescription": "Randomly selected loads with latency value being above 128",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -103,13 +83,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 128.",
"SampleAfterValue": "1009",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 16",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -119,13 +96,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 16.",
"SampleAfterValue": "20011",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 256",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -135,13 +109,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 256.",
"SampleAfterValue": "503",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 32",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -151,13 +122,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 32.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 4",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -167,13 +135,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above four.",
"SampleAfterValue": "100003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 512",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -183,13 +148,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 512.",
"SampleAfterValue": "101",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 64",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -199,13 +161,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 64.",
"SampleAfterValue": "2003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 8",
"Counter": "3",
"CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@ -215,13 +174,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above eight.",
"SampleAfterValue": "50021",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@ -230,8 +186,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@ -240,236 +194,177 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000244",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63BC00091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87FC00091",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6040007F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63BC007F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87FC007F7",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000122",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times RTM abort was triggered",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@ -479,8 +374,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@ -489,8 +382,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@ -499,8 +390,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@ -509,8 +398,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
@ -519,8 +406,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@ -529,8 +414,6 @@
},
{
"BriefDescription": "Number of times RTM commit succeeded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@ -539,8 +422,6 @@
},
{
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@ -549,8 +430,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@ -558,8 +437,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@ -568,8 +445,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@ -578,8 +453,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@ -588,8 +461,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@ -597,8 +468,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@ -607,8 +476,6 @@
},
{
"BriefDescription": "Number of times a TSX line had a cache conflict",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@ -617,8 +484,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@ -627,8 +492,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@ -637,8 +500,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@ -647,8 +508,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@ -657,8 +516,6 @@
},
{
"BriefDescription": "Number of times we could not allocate Lock Buffer",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",

8
tools/perf/pmu-events/arch/x86/broadwellx/other.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",

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tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
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tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
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tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
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@ -1,457 +1,457 @@
[
{
"BriefDescription": "pclk Cycles",
"Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C7 State Residency",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C1E",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C7 State Residency",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
"PublicDescription": "Ring GV with same final and initial frequency",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
"PublicDescription": "UNC_P_VR_HOT_CYCLES",
"Unit": "PCU"
}
]

76
tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@ -12,8 +10,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003",
@ -39,8 +31,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@ -49,8 +39,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@ -60,8 +48,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@ -71,8 +57,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@ -93,8 +75,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@ -104,8 +84,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@ -122,8 +98,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@ -131,8 +105,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@ -141,8 +113,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@ -152,8 +122,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@ -163,8 +131,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@ -174,8 +140,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@ -185,8 +149,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@ -195,8 +157,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@ -205,8 +165,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@ -216,8 +174,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -225,8 +181,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@ -234,8 +188,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@ -243,8 +195,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
@ -253,8 +203,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@ -264,8 +212,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@ -275,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@ -286,8 +230,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
@ -297,8 +239,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@ -307,8 +247,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@ -317,8 +255,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@ -327,8 +263,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@ -337,8 +271,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@ -347,8 +279,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@ -357,8 +287,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@ -367,8 +295,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@ -377,8 +303,6 @@
},
{
"BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",

3644
tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
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1679
tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
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24
tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -31,8 +25,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -51,8 +41,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -61,8 +49,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -71,8 +57,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@ -81,8 +65,6 @@
},
{
"BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCF",
"EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16",
"PublicDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@ -91,8 +73,6 @@
},
{
"BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCF",
"EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16",
"PublicDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@ -101,8 +81,6 @@
},
{
"BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCF",
"EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16",
"PublicDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@ -111,8 +89,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",

109
tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@ -31,8 +25,6 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@ -40,13 +32,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@ -54,13 +43,10 @@
"PEBS": "1",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@ -68,39 +54,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@ -108,26 +85,20 @@
"PEBS": "2",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x408006",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@ -135,39 +106,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x400206",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x410006",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@ -175,39 +137,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x200206",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
"MSRIndex": "0x3F7",
"MSRValue": "0x300206",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@ -215,52 +168,40 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x400406",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x420006",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x404006",
"PEBS": "1",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@ -268,13 +209,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@ -282,13 +220,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@ -297,8 +232,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
"SampleAfterValue": "200003",
@ -306,8 +239,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
"SampleAfterValue": "200003",
@ -315,8 +246,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
"SampleAfterValue": "200003",
@ -324,8 +253,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@ -335,8 +262,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@ -346,8 +271,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@ -357,8 +280,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@ -368,8 +289,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@ -379,8 +298,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@ -389,8 +306,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@ -400,8 +315,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@ -410,8 +323,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@ -421,8 +332,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@ -432,8 +341,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@ -442,8 +349,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@ -454,8 +359,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@ -464,8 +367,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
@ -474,8 +375,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@ -485,8 +384,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@ -496,8 +393,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@ -507,8 +402,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@ -518,8 +411,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",

2194
tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
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490
tools/perf/pmu-events/arch/x86/cascadelakex/other.json
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194
tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@ -33,8 +27,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
@ -45,8 +37,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
@ -56,8 +46,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
@ -68,8 +56,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
@ -80,8 +66,6 @@
},
{
"BriefDescription": "Return instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
@ -92,8 +76,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@ -104,8 +86,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
@ -115,8 +95,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@ -124,8 +102,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@ -135,8 +111,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@ -146,8 +120,6 @@
},
{
"BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@ -157,8 +129,6 @@
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@ -167,8 +137,6 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@ -178,8 +146,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@ -187,8 +153,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@ -197,8 +161,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@ -206,8 +168,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@ -215,8 +175,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
"Counter": "Fixed counter 2",
"CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@ -224,8 +182,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@ -234,8 +190,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@ -243,8 +197,6 @@
},
{
"BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x3C",
@ -254,8 +206,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
"Counter": "Fixed counter 1",
"CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@ -264,16 +214,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "Fixed counter 1",
"CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@ -282,16 +228,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@ -300,8 +242,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@ -310,8 +250,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@ -320,8 +258,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@ -330,8 +266,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@ -340,8 +274,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "20",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@ -350,8 +282,6 @@
},
{
"BriefDescription": "Total execution stalls.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@ -360,8 +290,6 @@
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@ -370,8 +298,6 @@
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@ -380,8 +306,6 @@
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@ -390,8 +314,6 @@
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@ -400,8 +322,6 @@
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"SampleAfterValue": "2000003",
@ -409,8 +329,6 @@
},
{
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@ -419,8 +337,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@ -429,8 +345,6 @@
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@ -439,8 +353,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
"Counter": "Fixed counter 0",
"CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
@ -448,8 +360,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@ -458,8 +368,6 @@
},
{
"BriefDescription": "Number of all retired NOP instructions.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP",
@ -469,8 +377,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
"Counter": "1",
"CounterHTOff": "1",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@ -481,8 +387,6 @@
},
{
"BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.",
"Counter": "0,2,3",
"CounterHTOff": "0,2,3",
"CounterMask": "10",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
@ -495,8 +399,6 @@
},
{
"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"SampleAfterValue": "2000003",
@ -504,8 +406,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@ -515,8 +415,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003",
@ -524,8 +422,6 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@ -534,8 +430,6 @@
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@ -544,8 +438,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@ -554,8 +446,6 @@
},
{
"BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@ -564,8 +454,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@ -575,8 +463,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@ -586,8 +472,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@ -596,8 +480,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@ -607,8 +489,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@ -617,8 +497,6 @@
},
{
"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY",
"SampleAfterValue": "100003",
@ -626,8 +504,6 @@
},
{
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@ -636,8 +512,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Counts resource-related stall cycles.",
@ -646,8 +520,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@ -656,8 +528,6 @@
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@ -666,8 +536,6 @@
},
{
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.PAUSE_INST",
"SampleAfterValue": "2000003",
@ -675,8 +543,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@ -685,8 +551,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@ -698,8 +562,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@ -708,8 +570,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@ -718,8 +578,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@ -728,8 +586,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@ -738,8 +594,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@ -748,8 +602,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@ -758,8 +610,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@ -768,8 +618,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@ -778,8 +626,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
@ -788,8 +634,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@ -798,8 +642,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@ -808,8 +650,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@ -818,8 +658,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@ -828,8 +666,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@ -839,8 +675,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@ -850,8 +684,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@ -861,8 +693,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@ -872,8 +702,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@ -883,8 +711,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@ -895,8 +721,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
@ -905,8 +729,6 @@
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.",
@ -915,8 +737,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@ -925,8 +745,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
@ -934,8 +752,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@ -946,8 +762,6 @@
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@ -956,8 +770,6 @@
},
{
"BriefDescription": "Number of macro-fused uops retired. (non precise)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@ -966,8 +778,6 @@
},
{
"BriefDescription": "Retirement slots used.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PublicDescription": "Counts the retirement slots used.",
@ -976,8 +786,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@ -988,8 +796,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",

8279
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
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42840
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
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45
tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
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@ -1,14 +1,13 @@
[
{
"BriefDescription": "pclk Cycles",
"Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
"Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
@ -16,7 +15,6 @@
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
@ -24,71 +22,70 @@
},
{
"BriefDescription": "Phase Shed 0 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
"PublicDescription": "Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_MCP_PROCHOT_CYCLES",
"PerPkg": "1",
@ -96,47 +93,46 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
"Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
@ -144,55 +140,54 @@
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
"PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",

56
tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@ -32,8 +26,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -42,8 +34,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 1G page",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -52,8 +42,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -62,8 +50,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 4K page",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -72,8 +58,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@ -82,8 +66,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@ -92,8 +74,6 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@ -102,8 +82,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -123,8 +99,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 1G page",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -133,8 +107,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -143,8 +115,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 4K page",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@ -153,8 +123,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@ -163,8 +131,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@ -173,8 +139,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@ -183,8 +147,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@ -193,8 +155,6 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@ -202,8 +162,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@ -213,8 +171,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -223,8 +179,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -233,8 +187,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -243,8 +195,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@ -253,8 +203,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@ -263,8 +211,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@ -273,8 +219,6 @@
},
{
"BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",

252
tools/perf/pmu-events/arch/x86/elkhartlake/cache.json
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11
tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json
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@ -1,36 +1,25 @@
[
{
"BriefDescription": "Counts the number of cycles the floating point divider is busy.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}

36
tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json
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@ -1,103 +1,67 @@
[
{
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.COND",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.INDIRECT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a return branch.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.RETURN",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe6",
"EventName": "BACLEARS.UNCOND",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of instruction cache hits.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of instruction cache misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
"SampleAfterValue": "200003",
"UMask": "0x2"

84
tools/perf/pmu-events/arch/x86/elkhartlake/memory.json
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@ -1,441 +1,357 @@
[
{
"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000044",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000044",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3002184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000020",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000020",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184008000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184008000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x402184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PREFETCHES.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000470",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000477",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000477",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000800",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2184000800",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x102184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x202184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}

143
tools/perf/pmu-events/arch/x86/elkhartlake/other.json
View File

@ -1,674 +1,531 @@
[
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EdgeDetect": "1",
"EventCode": "0x63",
"EventName": "BUS_LOCK.ALL",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.BLOCK_CYCLES",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "BUS_LOCK.LOCK_CYCLES",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EdgeDetect": "1",
"EventCode": "0x63",
"EventName": "BUS_LOCK.SELF_LOCKS",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_DRAM_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_L2_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "C0_STALLS.LOAD_LLC_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.MASKED",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of hardware interrupts received by the processor.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xcb",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "203",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10044",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000044",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000044",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.ALL_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000044",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3000000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.COREWB_M.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8003000000000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000004",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000001",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000002",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000040",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000010",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000020",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.HWPF_L2_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000020",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L1WB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.L2WB_M.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all hardware and software prefetches that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.PREFETCHES.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10470",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10477",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000477",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x184000477",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.READS_TO_CORE.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000000000000477",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10800",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100184000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"MSRValue": "0x8000100000000000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts uncached memory writes that have any type of response.",
"Counter": "0,1,2,3",
"EventCode": "0XB7",
"EventName": "OCR.UC_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200000010000",
"Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}

213
tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
View File

@ -1,662 +1,449 @@
[
{
"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of near CALL branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf9"
},
{
"BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xbf"
},
{
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfd"
},
{
"BriefDescription": "Counts the number of near RET branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfb"
},
{
"BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x7e"
},
{
"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xeb"
},
{
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xf7"
},
{
"BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0xfe"
},
{
"BriefDescription": "Counts the total number of BTCLEARS.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xe8",
"EventName": "BTCLEAR.ANY",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
"CollectPEBSRecord": "2",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PDIR_COUNTER": "NA",
"PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of unhalted core clock cycles.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
"CollectPEBSRecord": "2",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PDIR_COUNTER": "NA",
"PEBScounters": "34",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
},
{
"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.ANY",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of cycles the integer divider is busy.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xcd",
"EventName": "CYCLES_DIV_BUSY.IDIV",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
"CollectPEBSRecord": "2",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
"PEBScounters": "32",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of instructions retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.ANY",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003"
},
{
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"SampleAfterValue": "1000003",
"UMask": "0x6"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALL",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "This event is deprecated.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ALL",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue": "1000003",
"UMask": "0x40"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.CISC",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.DECODE",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.ITLB",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
"SampleAfterValue": "1000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.OTHER",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the total number of consumed retirement slots.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "TOPDOWN_RETIRING.ALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003"
},
{
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Counts the total number of uops retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Counts the number of integer divide uops retired.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.X87",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}

117
tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json
View File

@ -1,363 +1,246 @@
[
{
"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Entry hits.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDE_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Entry misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDE_MISS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDPE_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.EPDPE_MISS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "ITLB.FILLS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.PDE_CACHE_MISS",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x80"
},
{
"BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"UMask": "0x20"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0xe"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 1G page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
},
{
"BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PDIR_COUNTER": "NA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk).",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DTLB_MISS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x13"
},
{
"BriefDescription": "Counts the number of load uops retired that miss in the second Level TLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x11"
},
{
"BriefDescription": "Counts the number of store uops retired that miss in the second level TLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"UMask": "0x12"
}

288
tools/perf/pmu-events/arch/x86/goldmont/cache.json
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6
tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles the FP divide unit is busy",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Machine clears due to FP assists",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "Floating point divide uops retired. (Precise Event Capable)",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "2",

16
tools/perf/pmu-events/arch/x86/goldmont/frontend.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "BACLEARs asserted for any branch type",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "BACLEARs asserted for conditional branch",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
@ -21,8 +17,6 @@
},
{
"BriefDescription": "BACLEARs asserted for return branch",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"PublicDescription": "Counts BACLEARS on return instructions.",
@ -31,8 +25,6 @@
},
{
"BriefDescription": "Decode restrictions due to predicting wrong instruction length",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
@ -41,8 +33,6 @@
},
{
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
@ -51,8 +41,6 @@
},
{
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
@ -61,8 +49,6 @@
},
{
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
@ -71,8 +57,6 @@
},
{
"BriefDescription": "MS decode starts",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",

6
tools/perf/pmu-events/arch/x86/goldmont/memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Machine clears due to memory ordering issue",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Load uops that split a page (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "2",
@ -22,8 +18,6 @@
},
{
"BriefDescription": "Store uops that split a page (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "2",

10
tools/perf/pmu-events/arch/x86/goldmont/other.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles code-fetch stalled due to any reason.",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ALL",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
@ -10,8 +8,6 @@
},
{
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
@ -20,8 +16,6 @@
},
{
"BriefDescription": "Cycles hardware interrupts are masked",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.MASKED",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles pending interrupts are masked",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
"PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
@ -40,8 +32,6 @@
},
{
"BriefDescription": "Hardware interrupts received",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts hardware interrupts received by the processor.",

77
tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
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@ -1,8 +1,6 @@
[
{
"BriefDescription": "Retired branch instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "2",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Retired taken branch instructions (Precise event capable)",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"PEBS": "2",
@ -22,8 +18,6 @@
},
{
"BriefDescription": "Retired near call instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CALL",
"PEBS": "2",
@ -33,8 +27,6 @@
},
{
"BriefDescription": "Retired far branch instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "2",
@ -44,8 +36,6 @@
},
{
"BriefDescription": "Retired near indirect call instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.IND_CALL",
"PEBS": "2",
@ -55,8 +45,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.JCC",
"PEBS": "2",
@ -66,8 +54,6 @@
},
{
"BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"PEBS": "2",
@ -77,8 +63,6 @@
},
{
"BriefDescription": "Retired near relative call instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.REL_CALL",
"PEBS": "2",
@ -88,8 +72,6 @@
},
{
"BriefDescription": "Retired near return instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.RETURN",
"PEBS": "2",
@ -99,8 +81,6 @@
},
{
"BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"PEBS": "2",
@ -110,8 +90,6 @@
},
{
"BriefDescription": "Retired mispredicted branch instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "2",
@ -120,8 +98,6 @@
},
{
"BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"PEBS": "2",
@ -131,8 +107,6 @@
},
{
"BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.JCC",
"PEBS": "2",
@ -142,8 +116,6 @@
},
{
"BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS": "2",
@ -153,8 +125,6 @@
},
{
"BriefDescription": "Retired mispredicted near return instructions (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RETURN",
"PEBS": "2",
@ -164,8 +134,6 @@
},
{
"BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"PEBS": "2",
@ -175,7 +143,6 @@
},
{
"BriefDescription": "Core cycles when core is not halted (Fixed event)",
"Counter": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.CORE",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
@ -183,8 +150,6 @@
},
{
"BriefDescription": "Core cycles when core is not halted",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
@ -192,8 +157,6 @@
},
{
"BriefDescription": "Reference cycles when core is not halted",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF",
"PublicDescription": "Reference cycles when core is not halted. This event uses a programmable general purpose performance counter.",
@ -202,7 +165,6 @@
},
{
"BriefDescription": "Reference cycles when core is not halted (Fixed event)",
"Counter": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
@ -210,8 +172,6 @@
},
{
"BriefDescription": "Cycles a divider is busy",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.ALL",
"PublicDescription": "Counts core cycles if either divide unit is busy.",
@ -219,8 +179,6 @@
},
{
"BriefDescription": "Cycles the integer divide unit is busy",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.IDIV",
"PublicDescription": "Counts core cycles the integer divide unit is busy.",
@ -229,7 +187,6 @@
},
{
"BriefDescription": "Instructions retired (Fixed event)",
"Counter": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"SampleAfterValue": "2000003",
@ -237,8 +194,6 @@
},
{
"BriefDescription": "Instructions retired (Precise event capable)",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "2",
@ -247,8 +202,6 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).",
@ -256,8 +209,6 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle to recover",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
@ -266,8 +217,6 @@
},
{
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCA",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
@ -276,8 +225,6 @@
},
{
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.4K_ALIAS",
"PEBS": "2",
@ -287,8 +234,6 @@
},
{
"BriefDescription": "Loads blocked (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"PEBS": "2",
@ -298,8 +243,6 @@
},
{
"BriefDescription": "Loads blocked due to store data not ready (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"PEBS": "2",
@ -309,8 +252,6 @@
},
{
"BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBS": "2",
@ -320,8 +261,6 @@
},
{
"BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.UTLB_MISS",
"PEBS": "2",
@ -331,8 +270,6 @@
},
{
"BriefDescription": "All machine clears",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.ALL",
"PublicDescription": "Counts machine clears for any reason.",
@ -340,8 +277,6 @@
},
{
"BriefDescription": "Machine clears due to memory disambiguation",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
"PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.",
@ -350,8 +285,6 @@
},
{
"BriefDescription": "Self-Modifying Code detected",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",
@ -360,8 +293,6 @@
},
{
"BriefDescription": "Uops issued to the back end per cycle",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
@ -369,8 +300,6 @@
},
{
"BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "UOPS_NOT_DELIVERED.ANY",
"PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
@ -378,8 +307,6 @@
},
{
"BriefDescription": "Uops retired (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ANY",
"PEBS": "2",
@ -388,8 +315,6 @@
},
{
"BriefDescription": "Integer divide uops retired. (Precise Event Capable)",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.IDIV",
"PEBS": "2",
@ -399,8 +324,6 @@
},
{
"BriefDescription": "MS uops retired (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.MS",
"PEBS": "2",

14
tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
View File

@ -1,8 +1,6 @@
[
{
"BriefDescription": "ITLB misses",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x81",
"EventName": "ITLB.MISS",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
@ -11,8 +9,6 @@
},
{
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
@ -23,8 +19,6 @@
},
{
"BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
@ -35,8 +29,6 @@
},
{
"BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
@ -47,8 +39,6 @@
},
{
"BriefDescription": "Duration of page-walks in cycles",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.CYCLES",
"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
@ -57,8 +47,6 @@
},
{
"BriefDescription": "Duration of D-side page-walks in cycles",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
@ -67,8 +55,6 @@
},
{
"BriefDescription": "Duration of I-side pagewalks in cycles",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x05",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",

470
tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
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File diff suppressed because it is too large Load Diff

11
tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json
View File

@ -1,36 +1,25 @@
[
{
"BriefDescription": "Cycles the FP divide unit is busy",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xCD",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Machine clears due to FP assists",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.",
"SampleAfterValue": "20003",
"UMask": "0x4"
},
{
"BriefDescription": "Floating point divide uops retired (Precise Event Capable)",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.FPDIV",
"PEBS": "2",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of floating point divide uops retired.",
"SampleAfterValue": "2000003",
"UMask": "0x8"

32
tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
View File

@ -1,96 +1,64 @@
[
{
"BriefDescription": "BACLEARs asserted for any branch type",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.ALL",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "BACLEARs asserted for conditional branch",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.COND",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
"SampleAfterValue": "200003",
"UMask": "0x10"
},
{
"BriefDescription": "BACLEARs asserted for return branch",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE6",
"EventName": "BACLEARS.RETURN",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts BACLEARS on return instructions.",
"SampleAfterValue": "200003",
"UMask": "0x8"
},
{
"BriefDescription": "Decode restrictions due to predicting wrong instruction length",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE9",
"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.ACCESSES",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.",
"SampleAfterValue": "200003",
"UMask": "0x3"
},
{
"BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "MS decode starts",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xE7",
"EventName": "MS_DECODED.MS_ENTRY",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.",
"SampleAfterValue": "200003",
"UMask": "0x1"

10
tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
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@ -1,36 +1,26 @@
[
{
"BriefDescription": "Machine clears due to memory ordering issue",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.",
"SampleAfterValue": "20003",
"UMask": "0x2"
},
{
"BriefDescription": "Load uops that split a page (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
"PEBS": "2",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Store uops that split a page (Precise event capable)",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"PEBS": "2",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.",
"SampleAfterValue": "200003",
"UMask": "0x4"

20
tools/perf/pmu-events/arch/x86/goldmontplus/other.json
View File

@ -1,59 +1,39 @@
[
{
"BriefDescription": "Cycles code-fetch stalled due to any reason.",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ALL",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
"SampleAfterValue": "200003"
},
{
"BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.",
"CollectPEBSRecord": "1",
"Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles hardware interrupts are masked",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.MASKED",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
"SampleAfterValue": "200003",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles pending interrupts are masked",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
"SampleAfterValue": "200003",
"UMask": "0x4"
},
{
"BriefDescription": "Hardware interrupts received",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PDIR_COUNTER": "na",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts hardware interrupts received by the processor.",
"SampleAfterValue": "203",
"UMask": "0x1"

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