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clk: rockchip: add missing rk3288 npll rate table 

The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Heiko Stübner 2014-09-24 23:41:54 +02:00 committed by Mike Turquette
parent f9c0d14062
commit d1a559a1cb
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3288.c
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@ -143,7 +143,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
RK3288_MODE_CON, 14, 9, NULL),
RK3288_MODE_CON, 14, 9, rk3288_pll_rates),
};
static struct clk_div_table div_hclk_cpu_t[] = {