ARM: at91/dt: split sam9x5 peripheral definitions
This patch splits the sam9x5 peripheral definitions into: - a common base for all sam9x5 SoCs (at91sam9x5.dtsi) - several optional peripheral definitions which will be included by specific sam9x5 SoCs (at91sam9x5_'periph name'.dtsi) This provides a better representation of the real hardware (drop unneeded dt nodes) and avoids future peripheral id conflict (lcdc and isi both use peripheral id 25). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Boris BREZILLON
Nicolas Ferre
parent
d54322d8f6
commit
d195608acc
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@ -7,6 +7,8 @@
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*/
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*/
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5_usart3.dtsi"
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#include "at91sam9x5_macb0.dtsi"
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/ {
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/ {
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model = "Atmel AT91SAM9G25 SoC";
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model = "Atmel AT91SAM9G25 SoC";
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@ -7,6 +7,7 @@
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*/
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*/
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5_macb0.dtsi"
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/ {
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/ {
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model = "Atmel AT91SAM9G35 SoC";
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model = "Atmel AT91SAM9G35 SoC";
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@ -7,6 +7,9 @@
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*/
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*/
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5_usart3.dtsi"
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#include "at91sam9x5_macb0.dtsi"
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#include "at91sam9x5_macb1.dtsi"
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/ {
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/ {
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model = "Atmel AT91SAM9X25 SoC";
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model = "Atmel AT91SAM9X25 SoC";
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@ -22,27 +25,6 @@
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0x80000000 0xfffd0000 0xb83fffff /* pioC */
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0x80000000 0xfffd0000 0xb83fffff /* pioC */
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0x003fffff 0x003f8000 0x00000000 /* pioD */
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0x003fffff 0x003f8000 0x00000000 /* pioD */
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>;
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>;
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macb1 {
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pinctrl_macb1_rmii: macb1_rmii-0 {
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atmel,pins =
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<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
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AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
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AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
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AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
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AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
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AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
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AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
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AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
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AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
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AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
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};
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};
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};
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macb1: ethernet@f8030000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb1_rmii>;
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};
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};
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};
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};
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};
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};
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@ -7,6 +7,7 @@
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*/
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*/
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5.dtsi"
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#include "at91sam9x5_macb0.dtsi"
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/ {
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/ {
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model = "Atmel AT91SAM9X35 SoC";
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model = "Atmel AT91SAM9X35 SoC";
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@ -206,29 +206,6 @@
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};
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};
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};
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};
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usart3 {
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pinctrl_usart3: usart3-0 {
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atmel,pins =
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<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
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AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
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};
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
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};
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pinctrl_usart3_sck: usart3_sck-0 {
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atmel,pins =
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<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
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};
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};
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uart0 {
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uart0 {
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pinctrl_uart0: uart0-0 {
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pinctrl_uart0: uart0-0 {
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atmel,pins =
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atmel,pins =
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@ -277,34 +254,6 @@
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};
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};
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};
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};
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macb0 {
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pinctrl_macb0_rmii: macb0_rmii-0 {
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atmel,pins =
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<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
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AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
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AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
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AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
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AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
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AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
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AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
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AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
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AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
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AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
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};
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pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
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atmel,pins =
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<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
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AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
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AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
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AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
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AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
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AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
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AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
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AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
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};
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};
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mmc0 {
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mmc0 {
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pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
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pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
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atmel,pins =
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atmel,pins =
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@ -608,22 +557,6 @@
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status = "disabled";
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status = "disabled";
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};
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};
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macb0: ethernet@f802c000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xf802c000 0x100>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii>;
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status = "disabled";
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};
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macb1: ethernet@f8030000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xf8030000 0x100>;
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interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
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status = "disabled";
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};
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i2c0: i2c@f8010000 {
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i2c0: i2c@f8010000 {
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compatible = "atmel,at91sam9x5-i2c";
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compatible = "atmel,at91sam9x5-i2c";
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reg = <0xf8010000 0x100>;
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reg = <0xf8010000 0x100>;
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@ -0,0 +1,56 @@
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/*
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* at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
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* Ethernet interface.
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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ahb {
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apb {
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pinctrl@fffff400 {
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macb0 {
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pinctrl_macb0_rmii: macb0_rmii-0 {
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atmel,pins =
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<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
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AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
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AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
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AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
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AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
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AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
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AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
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AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
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AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
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AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
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};
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pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
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atmel,pins =
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<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
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AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
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AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
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AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
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AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
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AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
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AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
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AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
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};
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};
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};
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macb0: ethernet@f802c000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xf802c000 0x100>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_rmii>;
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status = "disabled";
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};
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};
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};
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};
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@ -0,0 +1,44 @@
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/*
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* at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
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* Ethernet interfaces.
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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ahb {
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apb {
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pinctrl@fffff400 {
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macb1 {
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pinctrl_macb1_rmii: macb1_rmii-0 {
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atmel,pins =
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<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
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AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
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AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
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AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
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AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
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AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
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AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
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AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
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AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
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AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
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};
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};
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};
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macb1: ethernet@f8030000 {
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compatible = "cdns,at32ap7000-macb", "cdns,macb";
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reg = <0xf8030000 0x100>;
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interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb1_rmii>;
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status = "disabled";
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};
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};
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};
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};
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@ -0,0 +1,51 @@
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/*
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* at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
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* 4 USART.
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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ahb {
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apb {
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pinctrl@fffff400 {
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usart3 {
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pinctrl_usart3: usart3-0 {
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atmel,pins =
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<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
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AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
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};
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pinctrl_usart3_rts: usart3_rts-0 {
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atmel,pins =
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<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
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};
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pinctrl_usart3_cts: usart3_cts-0 {
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atmel,pins =
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<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
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};
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pinctrl_usart3_sck: usart3_sck-0 {
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atmel,pins =
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<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
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};
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};
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};
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usart3: serial@f8028000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8028000 0x200>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usart3>;
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status = "disabled";
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};
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|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
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Reference in New Issue