[media] s5p-tv: remove obsolete driver
The s5p-tv driver has been replaced by the exynos drm driver for quite a long time now. Remove this driver to avoid having duplicate drivers, of which this one is considered dead code by Samsung. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
This commit is contained in:
Hans Verkuil
Mauro Carvalho Chehab
parent
f304562ed3
commit
d0d44516f8
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@ -1666,14 +1666,6 @@ S: Maintained
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F: arch/arm/plat-samsung/s5p-dev-mfc.c
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F: drivers/media/platform/s5p-mfc/
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ARM/SAMSUNG S5P SERIES TV SUBSYSTEM SUPPORT
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M: Kyungmin Park <kyungmin.park@samsung.com>
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M: Tomasz Stanislawski <t.stanislaws@samsung.com>
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L: linux-arm-kernel@lists.infradead.org
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L: linux-media@vger.kernel.org
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S: Maintained
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F: drivers/media/platform/s5p-tv/
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ARM/SAMSUNG S5P SERIES HDMI CEC SUBSYSTEM SUPPORT
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M: Kyungmin Park <kyungmin.park@samsung.com>
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L: linux-arm-kernel@lists.infradead.org
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@ -38,7 +38,6 @@ config DRM_EXYNOS7_DECON
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config DRM_EXYNOS_MIXER
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bool "Mixer"
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depends on !VIDEO_SAMSUNG_S5P_TV
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help
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Choose this option if you want to use Exynos Mixer for DRM.
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@ -77,7 +76,7 @@ config DRM_EXYNOS_DP
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config DRM_EXYNOS_HDMI
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bool "HDMI"
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depends on !VIDEO_SAMSUNG_S5P_TV && (DRM_EXYNOS_MIXER || DRM_EXYNOS5433_DECON)
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depends on DRM_EXYNOS_MIXER || DRM_EXYNOS5433_DECON
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help
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Choose this option if you want to use Exynos HDMI for DRM.
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@ -107,7 +107,6 @@ config VIDEO_S3C_CAMIF
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source "drivers/media/platform/soc_camera/Kconfig"
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source "drivers/media/platform/exynos4-is/Kconfig"
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source "drivers/media/platform/s5p-tv/Kconfig"
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source "drivers/media/platform/am437x/Kconfig"
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source "drivers/media/platform/xilinx/Kconfig"
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source "drivers/media/platform/rcar-vin/Kconfig"
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@ -30,7 +30,6 @@ obj-$(CONFIG_VIDEO_S3C_CAMIF) += s3c-camif/
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obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS) += exynos4-is/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) += s5p-mfc/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV) += s5p-tv/
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_G2D) += s5p-g2d/
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obj-$(CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC) += exynos-gsc/
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@ -1,88 +0,0 @@
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# drivers/media/platform/s5p-tv/Kconfig
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#
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# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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# Tomasz Stanislawski <t.stanislaws@samsung.com>
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#
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# Licensed under GPL
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config VIDEO_SAMSUNG_S5P_TV
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bool "Samsung TV driver for S5P platform"
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depends on PM
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depends on ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST
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default n
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---help---
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Say Y here to enable selecting the TV output devices for
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Samsung S5P platform.
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if VIDEO_SAMSUNG_S5P_TV
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config VIDEO_SAMSUNG_S5P_HDMI
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tristate "Samsung HDMI Driver"
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depends on VIDEO_V4L2
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depends on I2C
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depends on VIDEO_SAMSUNG_S5P_TV
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select VIDEO_SAMSUNG_S5P_HDMIPHY
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help
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Say Y here if you want support for the HDMI output
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interface in S5P Samsung SoC. The driver can be compiled
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as module. It is an auxiliary driver, that exposes a V4L2
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subdev for use by other drivers. This driver requires
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hdmiphy driver to work correctly.
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config VIDEO_SAMSUNG_S5P_HDMI_DEBUG
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bool "Enable debug for HDMI Driver"
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depends on VIDEO_SAMSUNG_S5P_HDMI
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default n
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help
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Enables debugging for HDMI driver.
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config VIDEO_SAMSUNG_S5P_HDMIPHY
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tristate "Samsung HDMIPHY Driver"
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depends on VIDEO_DEV && VIDEO_V4L2 && I2C
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depends on VIDEO_SAMSUNG_S5P_TV
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help
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Say Y here if you want support for the physical HDMI
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interface in S5P Samsung SoC. The driver can be compiled
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as module. It is an I2C driver, that exposes a V4L2
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subdev for use by other drivers.
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config VIDEO_SAMSUNG_S5P_SII9234
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tristate "Samsung SII9234 Driver"
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depends on VIDEO_DEV && VIDEO_V4L2 && I2C
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depends on VIDEO_SAMSUNG_S5P_TV
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help
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Say Y here if you want support for the MHL interface
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in S5P Samsung SoC. The driver can be compiled
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as module. It is an I2C driver, that exposes a V4L2
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subdev for use by other drivers.
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config VIDEO_SAMSUNG_S5P_SDO
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tristate "Samsung Analog TV Driver"
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depends on VIDEO_DEV && VIDEO_V4L2
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depends on VIDEO_SAMSUNG_S5P_TV
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help
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Say Y here if you want support for the analog TV output
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interface in S5P Samsung SoC. The driver can be compiled
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as module. It is an auxiliary driver, that exposes a V4L2
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subdev for use by other drivers. This driver requires
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hdmiphy driver to work correctly.
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config VIDEO_SAMSUNG_S5P_MIXER
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tristate "Samsung Mixer and Video Processor Driver"
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depends on VIDEO_DEV && VIDEO_V4L2
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depends on VIDEO_SAMSUNG_S5P_TV
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depends on HAS_DMA
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select VIDEOBUF2_DMA_CONTIG
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help
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Say Y here if you want support for the Mixer in Samsung S5P SoCs.
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This device produce image data to one of output interfaces.
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config VIDEO_SAMSUNG_S5P_MIXER_DEBUG
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bool "Enable debug for Mixer Driver"
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depends on VIDEO_SAMSUNG_S5P_MIXER
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default n
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help
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Enables debugging for Mixer driver.
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endif # VIDEO_SAMSUNG_S5P_TV
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@ -1,19 +0,0 @@
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# drivers/media/platform/samsung/tvout/Makefile
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#
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# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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# http://www.samsung.com/
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# Tomasz Stanislawski <t.stanislaws@samsung.com>
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#
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# Licensed under GPL
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMIPHY) += s5p-hdmiphy.o
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s5p-hdmiphy-y += hdmiphy_drv.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_SII9234) += s5p-sii9234.o
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s5p-sii9234-y += sii9234_drv.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMI) += s5p-hdmi.o
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s5p-hdmi-y += hdmi_drv.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_SDO) += s5p-sdo.o
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s5p-sdo-y += sdo_drv.o
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obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MIXER) += s5p-mixer.o
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s5p-mixer-y += mixer_drv.o mixer_video.o mixer_reg.o mixer_grp_layer.o mixer_vp_layer.o
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File diff suppressed because it is too large
Load Diff
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@ -1,324 +0,0 @@
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/*
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* Samsung HDMI Physical interface driver
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*
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* Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
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* Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <media/v4l2-subdev.h>
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MODULE_AUTHOR("Tomasz Stanislawski <t.stanislaws@samsung.com>");
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MODULE_DESCRIPTION("Samsung HDMI Physical interface driver");
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MODULE_LICENSE("GPL");
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struct hdmiphy_conf {
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unsigned long pixclk;
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const u8 *data;
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};
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struct hdmiphy_ctx {
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struct v4l2_subdev sd;
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const struct hdmiphy_conf *conf_tab;
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};
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static const struct hdmiphy_conf hdmiphy_conf_s5pv210[] = {
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{ .pixclk = 27000000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
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0x6B, 0x10, 0x02, 0x52, 0xDF, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 27027000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
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0x6B, 0x10, 0x02, 0x52, 0xDF, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xE2, 0x26, 0x00, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 74176000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B,
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0x6D, 0x10, 0x01, 0x52, 0xEF, 0xF3, 0x54, 0xB9,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xA5, 0x26, 0x01, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 74250000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40,
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0x6A, 0x10, 0x01, 0x52, 0xFF, 0xF1, 0x54, 0xBA,
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0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xA4, 0x26, 0x01, 0x00, 0x00, 0x00, }
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},
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{ /* end marker */ }
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};
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static const struct hdmiphy_conf hdmiphy_conf_exynos4210[] = {
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{ .pixclk = 27000000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
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0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 27027000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
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0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xE2, 0x26, 0x00, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 74176000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B,
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0x6D, 0x10, 0x01, 0x51, 0xEF, 0xF3, 0x54, 0xB9,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xA5, 0x26, 0x01, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 74250000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40,
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0x6A, 0x10, 0x01, 0x51, 0xFF, 0xF1, 0x54, 0xBA,
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0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xA4, 0x26, 0x01, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 148352000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xEF, 0x5B,
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0x6D, 0x18, 0x00, 0x51, 0xEF, 0xF3, 0x54, 0xB9,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x11, 0x40, 0xA5, 0x26, 0x02, 0x00, 0x00, 0x00, }
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},
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{ .pixclk = 148500000, .data = (u8 [32]) {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xF8, 0x40,
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0x6A, 0x18, 0x00, 0x51, 0xFF, 0xF1, 0x54, 0xBA,
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0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x11, 0x40, 0xA4, 0x26, 0x02, 0x00, 0x00, 0x00, }
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},
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{ /* end marker */ }
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};
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static const struct hdmiphy_conf hdmiphy_conf_exynos4212[] = {
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{ .pixclk = 27000000, .data = (u8 [32]) {
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0x01, 0x11, 0x2D, 0x75, 0x00, 0x01, 0x00, 0x08,
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0x82, 0x00, 0x0E, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
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0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x71,
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0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
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},
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{ .pixclk = 27027000, .data = (u8 [32]) {
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0x01, 0x91, 0x2D, 0x72, 0x00, 0x64, 0x12, 0x08,
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0x43, 0x20, 0x0E, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
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0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x71,
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0x54, 0xE2, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
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},
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{ .pixclk = 74176000, .data = (u8 [32]) {
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0x01, 0x91, 0x3E, 0x35, 0x00, 0x5B, 0xDE, 0x08,
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0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
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0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x52,
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0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
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},
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{ .pixclk = 74250000, .data = (u8 [32]) {
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0x01, 0x91, 0x3E, 0x35, 0x00, 0x40, 0xF0, 0x08,
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0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
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0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0x52,
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0x54, 0xA4, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
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},
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{ .pixclk = 148500000, .data = (u8 [32]) {
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0x01, 0x91, 0x3E, 0x15, 0x00, 0x40, 0xF0, 0x08,
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0x82, 0x20, 0x73, 0xD9, 0x45, 0xA0, 0x34, 0xC0,
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0x0B, 0x80, 0x12, 0x87, 0x08, 0x24, 0x24, 0xA4,
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0x54, 0x4A, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, }
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},
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{ /* end marker */ }
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};
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static const struct hdmiphy_conf hdmiphy_conf_exynos4412[] = {
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{ .pixclk = 27000000, .data = (u8 [32]) {
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0x01, 0x11, 0x2D, 0x75, 0x40, 0x01, 0x00, 0x08,
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0x82, 0x00, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
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0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
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0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
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},
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{ .pixclk = 27027000, .data = (u8 [32]) {
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0x01, 0x91, 0x2D, 0x72, 0x40, 0x64, 0x12, 0x08,
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0x43, 0x20, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
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0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
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0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, }
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},
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{ .pixclk = 74176000, .data = (u8 [32]) {
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0x01, 0x91, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0x08,
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0x81, 0x20, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
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0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
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0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
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||||
},
|
||||
{ .pixclk = 74250000, .data = (u8 [32]) {
|
||||
0x01, 0x91, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
|
||||
0x81, 0x20, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
|
||||
0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
|
||||
0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, }
|
||||
},
|
||||
{ .pixclk = 148500000, .data = (u8 [32]) {
|
||||
0x01, 0x91, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
|
||||
0x81, 0x20, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
|
||||
0x08, 0x80, 0x11, 0x84, 0x02, 0x22, 0x44, 0x86,
|
||||
0x54, 0x4B, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, }
|
||||
},
|
||||
{ /* end marker */ }
|
||||
};
|
||||
|
||||
static inline struct hdmiphy_ctx *sd_to_ctx(struct v4l2_subdev *sd)
|
||||
{
|
||||
return container_of(sd, struct hdmiphy_ctx, sd);
|
||||
}
|
||||
|
||||
static const u8 *hdmiphy_find_conf(unsigned long pixclk,
|
||||
const struct hdmiphy_conf *conf)
|
||||
{
|
||||
for (; conf->pixclk; ++conf)
|
||||
if (conf->pixclk == pixclk)
|
||||
return conf->data;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int hdmiphy_s_power(struct v4l2_subdev *sd, int on)
|
||||
{
|
||||
/* to be implemented */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmiphy_s_dv_timings(struct v4l2_subdev *sd,
|
||||
struct v4l2_dv_timings *timings)
|
||||
{
|
||||
const u8 *data;
|
||||
u8 buffer[32];
|
||||
int ret;
|
||||
struct hdmiphy_ctx *ctx = sd_to_ctx(sd);
|
||||
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
||||
struct device *dev = &client->dev;
|
||||
unsigned long pixclk = timings->bt.pixelclock;
|
||||
|
||||
dev_info(dev, "s_dv_timings\n");
|
||||
if ((timings->bt.flags & V4L2_DV_FL_REDUCED_FPS) && pixclk == 74250000)
|
||||
pixclk = 74176000;
|
||||
data = hdmiphy_find_conf(pixclk, ctx->conf_tab);
|
||||
if (!data) {
|
||||
dev_err(dev, "format not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* storing configuration to the device */
|
||||
memcpy(buffer, data, 32);
|
||||
ret = i2c_master_send(client, buffer, 32);
|
||||
if (ret != 32) {
|
||||
dev_err(dev, "failed to configure HDMIPHY via I2C\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmiphy_dv_timings_cap(struct v4l2_subdev *sd,
|
||||
struct v4l2_dv_timings_cap *cap)
|
||||
{
|
||||
if (cap->pad != 0)
|
||||
return -EINVAL;
|
||||
|
||||
cap->type = V4L2_DV_BT_656_1120;
|
||||
/* The phy only determines the pixelclock, leave the other values
|
||||
* at 0 to signify that we have no information for them. */
|
||||
cap->bt.min_pixelclock = 27000000;
|
||||
cap->bt.max_pixelclock = 148500000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmiphy_s_stream(struct v4l2_subdev *sd, int enable)
|
||||
{
|
||||
struct i2c_client *client = v4l2_get_subdevdata(sd);
|
||||
struct device *dev = &client->dev;
|
||||
u8 buffer[2];
|
||||
int ret;
|
||||
|
||||
dev_info(dev, "s_stream(%d)\n", enable);
|
||||
/* going to/from configuration from/to operation mode */
|
||||
buffer[0] = 0x1f;
|
||||
buffer[1] = enable ? 0x80 : 0x00;
|
||||
|
||||
ret = i2c_master_send(client, buffer, 2);
|
||||
if (ret != 2) {
|
||||
dev_err(dev, "stream (%d) failed\n", enable);
|
||||
return -EIO;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct v4l2_subdev_core_ops hdmiphy_core_ops = {
|
||||
.s_power = hdmiphy_s_power,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_video_ops hdmiphy_video_ops = {
|
||||
.s_dv_timings = hdmiphy_s_dv_timings,
|
||||
.s_stream = hdmiphy_s_stream,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_pad_ops hdmiphy_pad_ops = {
|
||||
.dv_timings_cap = hdmiphy_dv_timings_cap,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_ops hdmiphy_ops = {
|
||||
.core = &hdmiphy_core_ops,
|
||||
.video = &hdmiphy_video_ops,
|
||||
.pad = &hdmiphy_pad_ops,
|
||||
};
|
||||
|
||||
static int hdmiphy_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct hdmiphy_ctx *ctx;
|
||||
|
||||
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx)
|
||||
return -ENOMEM;
|
||||
|
||||
ctx->conf_tab = (struct hdmiphy_conf *)id->driver_data;
|
||||
v4l2_i2c_subdev_init(&ctx->sd, client, &hdmiphy_ops);
|
||||
|
||||
dev_info(&client->dev, "probe successful\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmiphy_remove(struct i2c_client *client)
|
||||
{
|
||||
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
||||
struct hdmiphy_ctx *ctx = sd_to_ctx(sd);
|
||||
|
||||
kfree(ctx);
|
||||
dev_info(&client->dev, "remove successful\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id hdmiphy_id[] = {
|
||||
{ "hdmiphy", (unsigned long)hdmiphy_conf_exynos4210 },
|
||||
{ "hdmiphy-s5pv210", (unsigned long)hdmiphy_conf_s5pv210 },
|
||||
{ "hdmiphy-exynos4210", (unsigned long)hdmiphy_conf_exynos4210 },
|
||||
{ "hdmiphy-exynos4212", (unsigned long)hdmiphy_conf_exynos4212 },
|
||||
{ "hdmiphy-exynos4412", (unsigned long)hdmiphy_conf_exynos4412 },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, hdmiphy_id);
|
||||
|
||||
static struct i2c_driver hdmiphy_driver = {
|
||||
.driver = {
|
||||
.name = "s5p-hdmiphy",
|
||||
},
|
||||
.probe = hdmiphy_probe,
|
||||
.remove = hdmiphy_remove,
|
||||
.id_table = hdmiphy_id,
|
||||
};
|
||||
|
||||
module_i2c_driver(hdmiphy_driver);
|
||||
|
|
@ -1,364 +0,0 @@
|
|||
/*
|
||||
* Samsung TV Mixer driver
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Tomasz Stanislawski, <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundiation. either version 2 of the License,
|
||||
* or (at your option) any later version
|
||||
*/
|
||||
|
||||
#ifndef SAMSUNG_MIXER_H
|
||||
#define SAMSUNG_MIXER_H
|
||||
|
||||
#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MIXER_DEBUG
|
||||
#define DEBUG
|
||||
#endif
|
||||
|
||||
#include <linux/fb.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/wait.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/videobuf2-v4l2.h>
|
||||
|
||||
#include "regs-mixer.h"
|
||||
|
||||
/** maximum number of output interfaces */
|
||||
#define MXR_MAX_OUTPUTS 2
|
||||
/** maximum number of input interfaces (layers) */
|
||||
#define MXR_MAX_LAYERS 3
|
||||
#define MXR_DRIVER_NAME "s5p-mixer"
|
||||
/** maximal number of planes for every layer */
|
||||
#define MXR_MAX_PLANES 2
|
||||
|
||||
#define MXR_ENABLE 1
|
||||
#define MXR_DISABLE 0
|
||||
|
||||
/** description of a macroblock for packed formats */
|
||||
struct mxr_block {
|
||||
/** vertical number of pixels in macroblock */
|
||||
unsigned int width;
|
||||
/** horizontal number of pixels in macroblock */
|
||||
unsigned int height;
|
||||
/** size of block in bytes */
|
||||
unsigned int size;
|
||||
};
|
||||
|
||||
/** description of supported format */
|
||||
struct mxr_format {
|
||||
/** format name/mnemonic */
|
||||
const char *name;
|
||||
/** fourcc identifier */
|
||||
u32 fourcc;
|
||||
/** colorspace identifier */
|
||||
enum v4l2_colorspace colorspace;
|
||||
/** number of planes in image data */
|
||||
int num_planes;
|
||||
/** description of block for each plane */
|
||||
struct mxr_block plane[MXR_MAX_PLANES];
|
||||
/** number of subframes in image data */
|
||||
int num_subframes;
|
||||
/** specifies to which subframe belong given plane */
|
||||
int plane2subframe[MXR_MAX_PLANES];
|
||||
/** internal code, driver dependent */
|
||||
unsigned long cookie;
|
||||
};
|
||||
|
||||
/** description of crop configuration for image */
|
||||
struct mxr_crop {
|
||||
/** width of layer in pixels */
|
||||
unsigned int full_width;
|
||||
/** height of layer in pixels */
|
||||
unsigned int full_height;
|
||||
/** horizontal offset of first pixel to be displayed */
|
||||
unsigned int x_offset;
|
||||
/** vertical offset of first pixel to be displayed */
|
||||
unsigned int y_offset;
|
||||
/** width of displayed data in pixels */
|
||||
unsigned int width;
|
||||
/** height of displayed data in pixels */
|
||||
unsigned int height;
|
||||
/** indicate which fields are present in buffer */
|
||||
unsigned int field;
|
||||
};
|
||||
|
||||
/** stages of geometry operations */
|
||||
enum mxr_geometry_stage {
|
||||
MXR_GEOMETRY_SINK,
|
||||
MXR_GEOMETRY_COMPOSE,
|
||||
MXR_GEOMETRY_CROP,
|
||||
MXR_GEOMETRY_SOURCE,
|
||||
};
|
||||
|
||||
/* flag indicating that offset should be 0 */
|
||||
#define MXR_NO_OFFSET 0x80000000
|
||||
|
||||
/** description of transformation from source to destination image */
|
||||
struct mxr_geometry {
|
||||
/** cropping for source image */
|
||||
struct mxr_crop src;
|
||||
/** cropping for destination image */
|
||||
struct mxr_crop dst;
|
||||
/** layer-dependant description of horizontal scaling */
|
||||
unsigned int x_ratio;
|
||||
/** layer-dependant description of vertical scaling */
|
||||
unsigned int y_ratio;
|
||||
};
|
||||
|
||||
/** instance of a buffer */
|
||||
struct mxr_buffer {
|
||||
/** common v4l buffer stuff -- must be first */
|
||||
struct vb2_v4l2_buffer vb;
|
||||
/** node for layer's lists */
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
|
||||
/** internal states of layer */
|
||||
enum mxr_layer_state {
|
||||
/** layers is not shown */
|
||||
MXR_LAYER_IDLE = 0,
|
||||
/** layer is shown */
|
||||
MXR_LAYER_STREAMING,
|
||||
/** state before STREAMOFF is finished */
|
||||
MXR_LAYER_STREAMING_FINISH,
|
||||
};
|
||||
|
||||
/** forward declarations */
|
||||
struct mxr_device;
|
||||
struct mxr_layer;
|
||||
|
||||
/** callback for layers operation */
|
||||
struct mxr_layer_ops {
|
||||
/* TODO: try to port it to subdev API */
|
||||
/** handler for resource release function */
|
||||
void (*release)(struct mxr_layer *);
|
||||
/** setting buffer to HW */
|
||||
void (*buffer_set)(struct mxr_layer *, struct mxr_buffer *);
|
||||
/** setting format and geometry in HW */
|
||||
void (*format_set)(struct mxr_layer *);
|
||||
/** streaming stop/start */
|
||||
void (*stream_set)(struct mxr_layer *, int);
|
||||
/** adjusting geometry */
|
||||
void (*fix_geometry)(struct mxr_layer *,
|
||||
enum mxr_geometry_stage, unsigned long);
|
||||
};
|
||||
|
||||
/** layer instance, a single window and content displayed on output */
|
||||
struct mxr_layer {
|
||||
/** parent mixer device */
|
||||
struct mxr_device *mdev;
|
||||
/** layer index (unique identifier) */
|
||||
int idx;
|
||||
/** callbacks for layer methods */
|
||||
struct mxr_layer_ops ops;
|
||||
/** format array */
|
||||
const struct mxr_format **fmt_array;
|
||||
/** size of format array */
|
||||
unsigned long fmt_array_size;
|
||||
|
||||
/** lock for protection of list and state fields */
|
||||
spinlock_t enq_slock;
|
||||
/** list for enqueued buffers */
|
||||
struct list_head enq_list;
|
||||
/** buffer currently owned by hardware in temporary registers */
|
||||
struct mxr_buffer *update_buf;
|
||||
/** buffer currently owned by hardware in shadow registers */
|
||||
struct mxr_buffer *shadow_buf;
|
||||
/** state of layer IDLE/STREAMING */
|
||||
enum mxr_layer_state state;
|
||||
|
||||
/** mutex for protection of fields below */
|
||||
struct mutex mutex;
|
||||
/** handler for video node */
|
||||
struct video_device vfd;
|
||||
/** queue for output buffers */
|
||||
struct vb2_queue vb_queue;
|
||||
/** current image format */
|
||||
const struct mxr_format *fmt;
|
||||
/** current geometry of image */
|
||||
struct mxr_geometry geo;
|
||||
};
|
||||
|
||||
/** description of mixers output interface */
|
||||
struct mxr_output {
|
||||
/** name of output */
|
||||
char name[32];
|
||||
/** output subdev */
|
||||
struct v4l2_subdev *sd;
|
||||
/** cookie used for configuration of registers */
|
||||
int cookie;
|
||||
};
|
||||
|
||||
/** specify source of output subdevs */
|
||||
struct mxr_output_conf {
|
||||
/** name of output (connector) */
|
||||
char *output_name;
|
||||
/** name of module that generates output subdev */
|
||||
char *module_name;
|
||||
/** cookie need for mixer HW */
|
||||
int cookie;
|
||||
};
|
||||
|
||||
struct clk;
|
||||
struct regulator;
|
||||
|
||||
/** auxiliary resources used my mixer */
|
||||
struct mxr_resources {
|
||||
/** interrupt index */
|
||||
int irq;
|
||||
/** pointer to Mixer registers */
|
||||
void __iomem *mxr_regs;
|
||||
/** pointer to Video Processor registers */
|
||||
void __iomem *vp_regs;
|
||||
/** other resources, should used under mxr_device.mutex */
|
||||
struct clk *mixer;
|
||||
struct clk *vp;
|
||||
struct clk *sclk_mixer;
|
||||
struct clk *sclk_hdmi;
|
||||
struct clk *sclk_dac;
|
||||
};
|
||||
|
||||
/* event flags used */
|
||||
enum mxr_devide_flags {
|
||||
MXR_EVENT_VSYNC = 0,
|
||||
MXR_EVENT_TOP = 1,
|
||||
};
|
||||
|
||||
/** drivers instance */
|
||||
struct mxr_device {
|
||||
/** master device */
|
||||
struct device *dev;
|
||||
/** state of each layer */
|
||||
struct mxr_layer *layer[MXR_MAX_LAYERS];
|
||||
/** state of each output */
|
||||
struct mxr_output *output[MXR_MAX_OUTPUTS];
|
||||
/** number of registered outputs */
|
||||
int output_cnt;
|
||||
|
||||
/* video resources */
|
||||
|
||||
/** V4L2 device */
|
||||
struct v4l2_device v4l2_dev;
|
||||
/** event wait queue */
|
||||
wait_queue_head_t event_queue;
|
||||
/** state flags */
|
||||
unsigned long event_flags;
|
||||
|
||||
/** spinlock for protection of registers */
|
||||
spinlock_t reg_slock;
|
||||
|
||||
/** mutex for protection of fields below */
|
||||
struct mutex mutex;
|
||||
/** number of entities depndant on output configuration */
|
||||
int n_output;
|
||||
/** number of users that do streaming */
|
||||
int n_streamer;
|
||||
/** index of current output */
|
||||
int current_output;
|
||||
/** auxiliary resources used my mixer */
|
||||
struct mxr_resources res;
|
||||
};
|
||||
|
||||
/** transform device structure into mixer device */
|
||||
static inline struct mxr_device *to_mdev(struct device *dev)
|
||||
{
|
||||
struct v4l2_device *vdev = dev_get_drvdata(dev);
|
||||
return container_of(vdev, struct mxr_device, v4l2_dev);
|
||||
}
|
||||
|
||||
/** get current output data, should be called under mdev's mutex */
|
||||
static inline struct mxr_output *to_output(struct mxr_device *mdev)
|
||||
{
|
||||
return mdev->output[mdev->current_output];
|
||||
}
|
||||
|
||||
/** get current output subdev, should be called under mdev's mutex */
|
||||
static inline struct v4l2_subdev *to_outsd(struct mxr_device *mdev)
|
||||
{
|
||||
struct mxr_output *out = to_output(mdev);
|
||||
return out ? out->sd : NULL;
|
||||
}
|
||||
|
||||
/** forward declaration for mixer platform data */
|
||||
struct mxr_platform_data;
|
||||
|
||||
/** acquiring common video resources */
|
||||
int mxr_acquire_video(struct mxr_device *mdev,
|
||||
struct mxr_output_conf *output_cont, int output_count);
|
||||
|
||||
/** releasing common video resources */
|
||||
void mxr_release_video(struct mxr_device *mdev);
|
||||
|
||||
struct mxr_layer *mxr_graph_layer_create(struct mxr_device *mdev, int idx);
|
||||
struct mxr_layer *mxr_vp_layer_create(struct mxr_device *mdev, int idx);
|
||||
struct mxr_layer *mxr_base_layer_create(struct mxr_device *mdev,
|
||||
int idx, char *name, const struct mxr_layer_ops *ops);
|
||||
|
||||
void mxr_base_layer_release(struct mxr_layer *layer);
|
||||
void mxr_layer_release(struct mxr_layer *layer);
|
||||
|
||||
int mxr_base_layer_register(struct mxr_layer *layer);
|
||||
void mxr_base_layer_unregister(struct mxr_layer *layer);
|
||||
|
||||
unsigned long mxr_get_plane_size(const struct mxr_block *blk,
|
||||
unsigned int width, unsigned int height);
|
||||
|
||||
/** adds new consumer for mixer's power */
|
||||
int __must_check mxr_power_get(struct mxr_device *mdev);
|
||||
/** removes consumer for mixer's power */
|
||||
void mxr_power_put(struct mxr_device *mdev);
|
||||
/** add new client for output configuration */
|
||||
void mxr_output_get(struct mxr_device *mdev);
|
||||
/** removes new client for output configuration */
|
||||
void mxr_output_put(struct mxr_device *mdev);
|
||||
/** add new client for streaming */
|
||||
void mxr_streamer_get(struct mxr_device *mdev);
|
||||
/** removes new client for streaming */
|
||||
void mxr_streamer_put(struct mxr_device *mdev);
|
||||
/** returns format of data delivared to current output */
|
||||
void mxr_get_mbus_fmt(struct mxr_device *mdev,
|
||||
struct v4l2_mbus_framefmt *mbus_fmt);
|
||||
|
||||
/* Debug */
|
||||
|
||||
#define mxr_err(mdev, fmt, ...) dev_err(mdev->dev, fmt, ##__VA_ARGS__)
|
||||
#define mxr_warn(mdev, fmt, ...) dev_warn(mdev->dev, fmt, ##__VA_ARGS__)
|
||||
#define mxr_info(mdev, fmt, ...) dev_info(mdev->dev, fmt, ##__VA_ARGS__)
|
||||
|
||||
#ifdef CONFIG_VIDEO_SAMSUNG_S5P_MIXER_DEBUG
|
||||
#define mxr_dbg(mdev, fmt, ...) dev_dbg(mdev->dev, fmt, ##__VA_ARGS__)
|
||||
#else
|
||||
#define mxr_dbg(mdev, fmt, ...) do { (void) mdev; } while (0)
|
||||
#endif
|
||||
|
||||
/* accessing Mixer's and Video Processor's registers */
|
||||
|
||||
void mxr_vsync_set_update(struct mxr_device *mdev, int en);
|
||||
void mxr_reg_reset(struct mxr_device *mdev);
|
||||
irqreturn_t mxr_irq_handler(int irq, void *dev_data);
|
||||
void mxr_reg_s_output(struct mxr_device *mdev, int cookie);
|
||||
void mxr_reg_streamon(struct mxr_device *mdev);
|
||||
void mxr_reg_streamoff(struct mxr_device *mdev);
|
||||
int mxr_reg_wait4vsync(struct mxr_device *mdev);
|
||||
void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
|
||||
struct v4l2_mbus_framefmt *fmt);
|
||||
void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en);
|
||||
void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr);
|
||||
void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
|
||||
const struct mxr_format *fmt, const struct mxr_geometry *geo);
|
||||
|
||||
void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en);
|
||||
void mxr_reg_vp_buffer(struct mxr_device *mdev,
|
||||
dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2]);
|
||||
void mxr_reg_vp_format(struct mxr_device *mdev,
|
||||
const struct mxr_format *fmt, const struct mxr_geometry *geo);
|
||||
void mxr_reg_dump(struct mxr_device *mdev);
|
||||
|
||||
#endif /* SAMSUNG_MIXER_H */
|
||||
|
||||
|
|
@ -1,527 +0,0 @@
|
|||
/*
|
||||
* Samsung TV Mixer driver
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Tomasz Stanislawski, <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundiation. either version 2 of the License,
|
||||
* or (at your option) any later version
|
||||
*/
|
||||
|
||||
#include "mixer.h"
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
|
||||
MODULE_DESCRIPTION("Samsung MIXER");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
/* --------- DRIVER PARAMETERS ---------- */
|
||||
|
||||
static struct mxr_output_conf mxr_output_conf[] = {
|
||||
{
|
||||
.output_name = "S5P HDMI connector",
|
||||
.module_name = "s5p-hdmi",
|
||||
.cookie = 1,
|
||||
},
|
||||
{
|
||||
.output_name = "S5P SDO connector",
|
||||
.module_name = "s5p-sdo",
|
||||
.cookie = 0,
|
||||
},
|
||||
};
|
||||
|
||||
void mxr_get_mbus_fmt(struct mxr_device *mdev,
|
||||
struct v4l2_mbus_framefmt *mbus_fmt)
|
||||
{
|
||||
struct v4l2_subdev *sd;
|
||||
struct v4l2_subdev_format fmt = {
|
||||
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
|
||||
};
|
||||
int ret;
|
||||
|
||||
mutex_lock(&mdev->mutex);
|
||||
sd = to_outsd(mdev);
|
||||
ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
|
||||
*mbus_fmt = fmt.format;
|
||||
WARN(ret, "failed to get mbus_fmt for output %s\n", sd->name);
|
||||
mutex_unlock(&mdev->mutex);
|
||||
}
|
||||
|
||||
void mxr_streamer_get(struct mxr_device *mdev)
|
||||
{
|
||||
mutex_lock(&mdev->mutex);
|
||||
++mdev->n_streamer;
|
||||
mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_streamer);
|
||||
if (mdev->n_streamer == 1) {
|
||||
struct v4l2_subdev *sd = to_outsd(mdev);
|
||||
struct v4l2_subdev_format fmt = {
|
||||
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
|
||||
};
|
||||
struct v4l2_mbus_framefmt *mbus_fmt = &fmt.format;
|
||||
struct mxr_resources *res = &mdev->res;
|
||||
int ret;
|
||||
|
||||
if (to_output(mdev)->cookie == 0)
|
||||
clk_set_parent(res->sclk_mixer, res->sclk_dac);
|
||||
else
|
||||
clk_set_parent(res->sclk_mixer, res->sclk_hdmi);
|
||||
mxr_reg_s_output(mdev, to_output(mdev)->cookie);
|
||||
|
||||
ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
|
||||
WARN(ret, "failed to get mbus_fmt for output %s\n", sd->name);
|
||||
ret = v4l2_subdev_call(sd, video, s_stream, 1);
|
||||
WARN(ret, "starting stream failed for output %s\n", sd->name);
|
||||
|
||||
mxr_reg_set_mbus_fmt(mdev, mbus_fmt);
|
||||
mxr_reg_streamon(mdev);
|
||||
ret = mxr_reg_wait4vsync(mdev);
|
||||
WARN(ret, "failed to get vsync (%d) from output\n", ret);
|
||||
}
|
||||
mutex_unlock(&mdev->mutex);
|
||||
mxr_reg_dump(mdev);
|
||||
/* FIXME: what to do when streaming fails? */
|
||||
}
|
||||
|
||||
void mxr_streamer_put(struct mxr_device *mdev)
|
||||
{
|
||||
mutex_lock(&mdev->mutex);
|
||||
--mdev->n_streamer;
|
||||
mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_streamer);
|
||||
if (mdev->n_streamer == 0) {
|
||||
int ret;
|
||||
struct v4l2_subdev *sd = to_outsd(mdev);
|
||||
|
||||
mxr_reg_streamoff(mdev);
|
||||
/* vsync applies Mixer setup */
|
||||
ret = mxr_reg_wait4vsync(mdev);
|
||||
WARN(ret, "failed to get vsync (%d) from output\n", ret);
|
||||
ret = v4l2_subdev_call(sd, video, s_stream, 0);
|
||||
WARN(ret, "stopping stream failed for output %s\n", sd->name);
|
||||
}
|
||||
WARN(mdev->n_streamer < 0, "negative number of streamers (%d)\n",
|
||||
mdev->n_streamer);
|
||||
mutex_unlock(&mdev->mutex);
|
||||
mxr_reg_dump(mdev);
|
||||
}
|
||||
|
||||
void mxr_output_get(struct mxr_device *mdev)
|
||||
{
|
||||
mutex_lock(&mdev->mutex);
|
||||
++mdev->n_output;
|
||||
mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_output);
|
||||
/* turn on auxiliary driver */
|
||||
if (mdev->n_output == 1)
|
||||
v4l2_subdev_call(to_outsd(mdev), core, s_power, 1);
|
||||
mutex_unlock(&mdev->mutex);
|
||||
}
|
||||
|
||||
void mxr_output_put(struct mxr_device *mdev)
|
||||
{
|
||||
mutex_lock(&mdev->mutex);
|
||||
--mdev->n_output;
|
||||
mxr_dbg(mdev, "%s(%d)\n", __func__, mdev->n_output);
|
||||
/* turn on auxiliary driver */
|
||||
if (mdev->n_output == 0)
|
||||
v4l2_subdev_call(to_outsd(mdev), core, s_power, 0);
|
||||
WARN(mdev->n_output < 0, "negative number of output users (%d)\n",
|
||||
mdev->n_output);
|
||||
mutex_unlock(&mdev->mutex);
|
||||
}
|
||||
|
||||
int mxr_power_get(struct mxr_device *mdev)
|
||||
{
|
||||
int ret = pm_runtime_get_sync(mdev->dev);
|
||||
|
||||
/* returning 1 means that power is already enabled,
|
||||
* so zero success be returned */
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mxr_power_put(struct mxr_device *mdev)
|
||||
{
|
||||
pm_runtime_put_sync(mdev->dev);
|
||||
}
|
||||
|
||||
/* --------- RESOURCE MANAGEMENT -------------*/
|
||||
|
||||
static int mxr_acquire_plat_resources(struct mxr_device *mdev,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mxr");
|
||||
if (res == NULL) {
|
||||
mxr_err(mdev, "get memory resource failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
mdev->res.mxr_regs = ioremap(res->start, resource_size(res));
|
||||
if (mdev->res.mxr_regs == NULL) {
|
||||
mxr_err(mdev, "register mapping failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vp");
|
||||
if (res == NULL) {
|
||||
mxr_err(mdev, "get memory resource failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail_mxr_regs;
|
||||
}
|
||||
|
||||
mdev->res.vp_regs = ioremap(res->start, resource_size(res));
|
||||
if (mdev->res.vp_regs == NULL) {
|
||||
mxr_err(mdev, "register mapping failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail_mxr_regs;
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq");
|
||||
if (res == NULL) {
|
||||
mxr_err(mdev, "get interrupt resource failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail_vp_regs;
|
||||
}
|
||||
|
||||
ret = request_irq(res->start, mxr_irq_handler, 0, "s5p-mixer", mdev);
|
||||
if (ret) {
|
||||
mxr_err(mdev, "request interrupt failed.\n");
|
||||
goto fail_vp_regs;
|
||||
}
|
||||
mdev->res.irq = res->start;
|
||||
|
||||
return 0;
|
||||
|
||||
fail_vp_regs:
|
||||
iounmap(mdev->res.vp_regs);
|
||||
|
||||
fail_mxr_regs:
|
||||
iounmap(mdev->res.mxr_regs);
|
||||
|
||||
fail:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mxr_resource_clear_clocks(struct mxr_resources *res)
|
||||
{
|
||||
res->mixer = ERR_PTR(-EINVAL);
|
||||
res->vp = ERR_PTR(-EINVAL);
|
||||
res->sclk_mixer = ERR_PTR(-EINVAL);
|
||||
res->sclk_hdmi = ERR_PTR(-EINVAL);
|
||||
res->sclk_dac = ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static void mxr_release_plat_resources(struct mxr_device *mdev)
|
||||
{
|
||||
free_irq(mdev->res.irq, mdev);
|
||||
iounmap(mdev->res.vp_regs);
|
||||
iounmap(mdev->res.mxr_regs);
|
||||
}
|
||||
|
||||
static void mxr_release_clocks(struct mxr_device *mdev)
|
||||
{
|
||||
struct mxr_resources *res = &mdev->res;
|
||||
|
||||
if (!IS_ERR(res->sclk_dac))
|
||||
clk_put(res->sclk_dac);
|
||||
if (!IS_ERR(res->sclk_hdmi))
|
||||
clk_put(res->sclk_hdmi);
|
||||
if (!IS_ERR(res->sclk_mixer))
|
||||
clk_put(res->sclk_mixer);
|
||||
if (!IS_ERR(res->vp))
|
||||
clk_put(res->vp);
|
||||
if (!IS_ERR(res->mixer))
|
||||
clk_put(res->mixer);
|
||||
}
|
||||
|
||||
static int mxr_acquire_clocks(struct mxr_device *mdev)
|
||||
{
|
||||
struct mxr_resources *res = &mdev->res;
|
||||
struct device *dev = mdev->dev;
|
||||
|
||||
mxr_resource_clear_clocks(res);
|
||||
|
||||
res->mixer = clk_get(dev, "mixer");
|
||||
if (IS_ERR(res->mixer)) {
|
||||
mxr_err(mdev, "failed to get clock 'mixer'\n");
|
||||
goto fail;
|
||||
}
|
||||
res->vp = clk_get(dev, "vp");
|
||||
if (IS_ERR(res->vp)) {
|
||||
mxr_err(mdev, "failed to get clock 'vp'\n");
|
||||
goto fail;
|
||||
}
|
||||
res->sclk_mixer = clk_get(dev, "sclk_mixer");
|
||||
if (IS_ERR(res->sclk_mixer)) {
|
||||
mxr_err(mdev, "failed to get clock 'sclk_mixer'\n");
|
||||
goto fail;
|
||||
}
|
||||
res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
|
||||
if (IS_ERR(res->sclk_hdmi)) {
|
||||
mxr_err(mdev, "failed to get clock 'sclk_hdmi'\n");
|
||||
goto fail;
|
||||
}
|
||||
res->sclk_dac = clk_get(dev, "sclk_dac");
|
||||
if (IS_ERR(res->sclk_dac)) {
|
||||
mxr_err(mdev, "failed to get clock 'sclk_dac'\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
mxr_release_clocks(mdev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int mxr_acquire_resources(struct mxr_device *mdev,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
ret = mxr_acquire_plat_resources(mdev, pdev);
|
||||
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = mxr_acquire_clocks(mdev);
|
||||
if (ret)
|
||||
goto fail_plat;
|
||||
|
||||
mxr_info(mdev, "resources acquired\n");
|
||||
return 0;
|
||||
|
||||
fail_plat:
|
||||
mxr_release_plat_resources(mdev);
|
||||
fail:
|
||||
mxr_err(mdev, "resources acquire failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mxr_release_resources(struct mxr_device *mdev)
|
||||
{
|
||||
mxr_release_clocks(mdev);
|
||||
mxr_release_plat_resources(mdev);
|
||||
memset(&mdev->res, 0, sizeof(mdev->res));
|
||||
mxr_resource_clear_clocks(&mdev->res);
|
||||
}
|
||||
|
||||
static void mxr_release_layers(struct mxr_device *mdev)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mdev->layer); ++i)
|
||||
if (mdev->layer[i])
|
||||
mxr_layer_release(mdev->layer[i]);
|
||||
}
|
||||
|
||||
static int mxr_acquire_layers(struct mxr_device *mdev,
|
||||
struct mxr_platform_data *pdata)
|
||||
{
|
||||
mdev->layer[0] = mxr_graph_layer_create(mdev, 0);
|
||||
mdev->layer[1] = mxr_graph_layer_create(mdev, 1);
|
||||
mdev->layer[2] = mxr_vp_layer_create(mdev, 0);
|
||||
|
||||
if (!mdev->layer[0] || !mdev->layer[1] || !mdev->layer[2]) {
|
||||
mxr_err(mdev, "failed to acquire layers\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
mxr_release_layers(mdev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* ---------- POWER MANAGEMENT ----------- */
|
||||
|
||||
static int mxr_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct mxr_device *mdev = to_mdev(dev);
|
||||
struct mxr_resources *res = &mdev->res;
|
||||
int ret;
|
||||
|
||||
mxr_dbg(mdev, "resume - start\n");
|
||||
mutex_lock(&mdev->mutex);
|
||||
/* turn clocks on */
|
||||
ret = clk_prepare_enable(res->mixer);
|
||||
if (ret < 0) {
|
||||
dev_err(mdev->dev, "clk_prepare_enable(mixer) failed\n");
|
||||
goto fail;
|
||||
}
|
||||
ret = clk_prepare_enable(res->vp);
|
||||
if (ret < 0) {
|
||||
dev_err(mdev->dev, "clk_prepare_enable(vp) failed\n");
|
||||
goto fail_mixer;
|
||||
}
|
||||
ret = clk_prepare_enable(res->sclk_mixer);
|
||||
if (ret < 0) {
|
||||
dev_err(mdev->dev, "clk_prepare_enable(sclk_mixer) failed\n");
|
||||
goto fail_vp;
|
||||
}
|
||||
/* apply default configuration */
|
||||
mxr_reg_reset(mdev);
|
||||
mxr_dbg(mdev, "resume - finished\n");
|
||||
|
||||
mutex_unlock(&mdev->mutex);
|
||||
return 0;
|
||||
|
||||
fail_vp:
|
||||
clk_disable_unprepare(res->vp);
|
||||
fail_mixer:
|
||||
clk_disable_unprepare(res->mixer);
|
||||
fail:
|
||||
mutex_unlock(&mdev->mutex);
|
||||
dev_err(mdev->dev, "resume failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxr_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct mxr_device *mdev = to_mdev(dev);
|
||||
struct mxr_resources *res = &mdev->res;
|
||||
mxr_dbg(mdev, "suspend - start\n");
|
||||
mutex_lock(&mdev->mutex);
|
||||
/* turn clocks off */
|
||||
clk_disable_unprepare(res->sclk_mixer);
|
||||
clk_disable_unprepare(res->vp);
|
||||
clk_disable_unprepare(res->mixer);
|
||||
mutex_unlock(&mdev->mutex);
|
||||
mxr_dbg(mdev, "suspend - finished\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops mxr_pm_ops = {
|
||||
.runtime_suspend = mxr_runtime_suspend,
|
||||
.runtime_resume = mxr_runtime_resume,
|
||||
};
|
||||
|
||||
/* --------- DRIVER INITIALIZATION ---------- */
|
||||
|
||||
static int mxr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mxr_platform_data *pdata = dev->platform_data;
|
||||
struct mxr_device *mdev;
|
||||
int ret;
|
||||
|
||||
/* mdev does not exist yet so no mxr_dbg is used */
|
||||
dev_info(dev, "probe start\n");
|
||||
|
||||
mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
|
||||
if (!mdev) {
|
||||
dev_err(dev, "not enough memory.\n");
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* setup pointer to master device */
|
||||
mdev->dev = dev;
|
||||
|
||||
mutex_init(&mdev->mutex);
|
||||
spin_lock_init(&mdev->reg_slock);
|
||||
init_waitqueue_head(&mdev->event_queue);
|
||||
|
||||
/* acquire resources: regs, irqs, clocks, regulators */
|
||||
ret = mxr_acquire_resources(mdev, pdev);
|
||||
if (ret)
|
||||
goto fail_mem;
|
||||
|
||||
/* configure resources for video output */
|
||||
ret = mxr_acquire_video(mdev, mxr_output_conf,
|
||||
ARRAY_SIZE(mxr_output_conf));
|
||||
if (ret)
|
||||
goto fail_resources;
|
||||
|
||||
/* configure layers */
|
||||
ret = mxr_acquire_layers(mdev, pdata);
|
||||
if (ret)
|
||||
goto fail_video;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
mxr_info(mdev, "probe successful\n");
|
||||
return 0;
|
||||
|
||||
fail_video:
|
||||
mxr_release_video(mdev);
|
||||
|
||||
fail_resources:
|
||||
mxr_release_resources(mdev);
|
||||
|
||||
fail_mem:
|
||||
kfree(mdev);
|
||||
|
||||
fail:
|
||||
dev_info(dev, "probe failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxr_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mxr_device *mdev = to_mdev(dev);
|
||||
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
mxr_release_layers(mdev);
|
||||
mxr_release_video(mdev);
|
||||
mxr_release_resources(mdev);
|
||||
|
||||
kfree(mdev);
|
||||
|
||||
dev_info(dev, "remove successful\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver mxr_driver __refdata = {
|
||||
.probe = mxr_probe,
|
||||
.remove = mxr_remove,
|
||||
.driver = {
|
||||
.name = MXR_DRIVER_NAME,
|
||||
.pm = &mxr_pm_ops,
|
||||
}
|
||||
};
|
||||
|
||||
static int __init mxr_init(void)
|
||||
{
|
||||
int i, ret;
|
||||
static const char banner[] __initconst =
|
||||
"Samsung TV Mixer driver, "
|
||||
"(c) 2010-2011 Samsung Electronics Co., Ltd.\n";
|
||||
pr_info("%s\n", banner);
|
||||
|
||||
/* Loading auxiliary modules */
|
||||
for (i = 0; i < ARRAY_SIZE(mxr_output_conf); ++i)
|
||||
request_module(mxr_output_conf[i].module_name);
|
||||
|
||||
ret = platform_driver_register(&mxr_driver);
|
||||
if (ret != 0) {
|
||||
pr_err("s5p-tv: registration of MIXER driver failed\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
module_init(mxr_init);
|
||||
|
||||
static void __exit mxr_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&mxr_driver);
|
||||
}
|
||||
module_exit(mxr_exit);
|
||||
|
|
@ -1,270 +0,0 @@
|
|||
/*
|
||||
* Samsung TV Mixer driver
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Tomasz Stanislawski, <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundiation. either version 2 of the License,
|
||||
* or (at your option) any later version
|
||||
*/
|
||||
|
||||
#include "mixer.h"
|
||||
|
||||
#include <media/videobuf2-dma-contig.h>
|
||||
|
||||
/* FORMAT DEFINITIONS */
|
||||
|
||||
static const struct mxr_format mxr_fb_fmt_rgb565 = {
|
||||
.name = "RGB565",
|
||||
.fourcc = V4L2_PIX_FMT_RGB565,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
.num_planes = 1,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 2 },
|
||||
},
|
||||
.num_subframes = 1,
|
||||
.cookie = 4,
|
||||
};
|
||||
|
||||
static const struct mxr_format mxr_fb_fmt_argb1555 = {
|
||||
.name = "ARGB1555",
|
||||
.num_planes = 1,
|
||||
.fourcc = V4L2_PIX_FMT_RGB555,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 2 },
|
||||
},
|
||||
.num_subframes = 1,
|
||||
.cookie = 5,
|
||||
};
|
||||
|
||||
static const struct mxr_format mxr_fb_fmt_argb4444 = {
|
||||
.name = "ARGB4444",
|
||||
.num_planes = 1,
|
||||
.fourcc = V4L2_PIX_FMT_RGB444,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 2 },
|
||||
},
|
||||
.num_subframes = 1,
|
||||
.cookie = 6,
|
||||
};
|
||||
|
||||
static const struct mxr_format mxr_fb_fmt_argb8888 = {
|
||||
.name = "ARGB8888",
|
||||
.fourcc = V4L2_PIX_FMT_BGR32,
|
||||
.colorspace = V4L2_COLORSPACE_SRGB,
|
||||
.num_planes = 1,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 4 },
|
||||
},
|
||||
.num_subframes = 1,
|
||||
.cookie = 7,
|
||||
};
|
||||
|
||||
static const struct mxr_format *mxr_graph_format[] = {
|
||||
&mxr_fb_fmt_rgb565,
|
||||
&mxr_fb_fmt_argb1555,
|
||||
&mxr_fb_fmt_argb4444,
|
||||
&mxr_fb_fmt_argb8888,
|
||||
};
|
||||
|
||||
/* AUXILIARY CALLBACKS */
|
||||
|
||||
static void mxr_graph_layer_release(struct mxr_layer *layer)
|
||||
{
|
||||
mxr_base_layer_unregister(layer);
|
||||
mxr_base_layer_release(layer);
|
||||
}
|
||||
|
||||
static void mxr_graph_buffer_set(struct mxr_layer *layer,
|
||||
struct mxr_buffer *buf)
|
||||
{
|
||||
dma_addr_t addr = 0;
|
||||
|
||||
if (buf)
|
||||
addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
|
||||
mxr_reg_graph_buffer(layer->mdev, layer->idx, addr);
|
||||
}
|
||||
|
||||
static void mxr_graph_stream_set(struct mxr_layer *layer, int en)
|
||||
{
|
||||
mxr_reg_graph_layer_stream(layer->mdev, layer->idx, en);
|
||||
}
|
||||
|
||||
static void mxr_graph_format_set(struct mxr_layer *layer)
|
||||
{
|
||||
mxr_reg_graph_format(layer->mdev, layer->idx,
|
||||
layer->fmt, &layer->geo);
|
||||
}
|
||||
|
||||
static inline unsigned int closest(unsigned int x, unsigned int a,
|
||||
unsigned int b, unsigned long flags)
|
||||
{
|
||||
unsigned int mid = (a + b) / 2;
|
||||
|
||||
/* choosing closest value with constraints according to table:
|
||||
* -------------+-----+-----+-----+-------+
|
||||
* flags | 0 | LE | GE | LE|GE |
|
||||
* -------------+-----+-----+-----+-------+
|
||||
* x <= a | a | a | a | a |
|
||||
* a < x <= mid | a | a | b | a |
|
||||
* mid < x < b | b | a | b | b |
|
||||
* b <= x | b | b | b | b |
|
||||
* -------------+-----+-----+-----+-------+
|
||||
*/
|
||||
|
||||
/* remove all non-constraint flags */
|
||||
flags &= V4L2_SEL_FLAG_LE | V4L2_SEL_FLAG_GE;
|
||||
|
||||
if (x <= a)
|
||||
return a;
|
||||
if (x >= b)
|
||||
return b;
|
||||
if (flags == V4L2_SEL_FLAG_LE)
|
||||
return a;
|
||||
if (flags == V4L2_SEL_FLAG_GE)
|
||||
return b;
|
||||
if (x <= mid)
|
||||
return a;
|
||||
return b;
|
||||
}
|
||||
|
||||
static inline unsigned int do_center(unsigned int center,
|
||||
unsigned int size, unsigned int upper, unsigned int flags)
|
||||
{
|
||||
unsigned int lower;
|
||||
|
||||
if (flags & MXR_NO_OFFSET)
|
||||
return 0;
|
||||
|
||||
lower = center - min(center, size / 2);
|
||||
return min(lower, upper - size);
|
||||
}
|
||||
|
||||
static void mxr_graph_fix_geometry(struct mxr_layer *layer,
|
||||
enum mxr_geometry_stage stage, unsigned long flags)
|
||||
{
|
||||
struct mxr_geometry *geo = &layer->geo;
|
||||
struct mxr_crop *src = &geo->src;
|
||||
struct mxr_crop *dst = &geo->dst;
|
||||
unsigned int x_center, y_center;
|
||||
|
||||
switch (stage) {
|
||||
|
||||
case MXR_GEOMETRY_SINK: /* nothing to be fixed here */
|
||||
flags = 0;
|
||||
/* fall through */
|
||||
|
||||
case MXR_GEOMETRY_COMPOSE:
|
||||
/* remember center of the area */
|
||||
x_center = dst->x_offset + dst->width / 2;
|
||||
y_center = dst->y_offset + dst->height / 2;
|
||||
/* round up/down to 2 multiple depending on flags */
|
||||
if (flags & V4L2_SEL_FLAG_LE) {
|
||||
dst->width = round_down(dst->width, 2);
|
||||
dst->height = round_down(dst->height, 2);
|
||||
} else {
|
||||
dst->width = round_up(dst->width, 2);
|
||||
dst->height = round_up(dst->height, 2);
|
||||
}
|
||||
/* assure that compose rect is inside display area */
|
||||
dst->width = min(dst->width, dst->full_width);
|
||||
dst->height = min(dst->height, dst->full_height);
|
||||
|
||||
/* ensure that compose is reachable using 2x scaling */
|
||||
dst->width = min(dst->width, 2 * src->full_width);
|
||||
dst->height = min(dst->height, 2 * src->full_height);
|
||||
|
||||
/* setup offsets */
|
||||
dst->x_offset = do_center(x_center, dst->width,
|
||||
dst->full_width, flags);
|
||||
dst->y_offset = do_center(y_center, dst->height,
|
||||
dst->full_height, flags);
|
||||
flags = 0;
|
||||
/* fall through */
|
||||
|
||||
case MXR_GEOMETRY_CROP:
|
||||
/* remember center of the area */
|
||||
x_center = src->x_offset + src->width / 2;
|
||||
y_center = src->y_offset + src->height / 2;
|
||||
/* ensure that cropping area lies inside the buffer */
|
||||
if (src->full_width < dst->width)
|
||||
src->width = dst->width / 2;
|
||||
else
|
||||
src->width = closest(src->width, dst->width / 2,
|
||||
dst->width, flags);
|
||||
|
||||
if (src->width == dst->width)
|
||||
geo->x_ratio = 0;
|
||||
else
|
||||
geo->x_ratio = 1;
|
||||
|
||||
if (src->full_height < dst->height)
|
||||
src->height = dst->height / 2;
|
||||
else
|
||||
src->height = closest(src->height, dst->height / 2,
|
||||
dst->height, flags);
|
||||
|
||||
if (src->height == dst->height)
|
||||
geo->y_ratio = 0;
|
||||
else
|
||||
geo->y_ratio = 1;
|
||||
|
||||
/* setup offsets */
|
||||
src->x_offset = do_center(x_center, src->width,
|
||||
src->full_width, flags);
|
||||
src->y_offset = do_center(y_center, src->height,
|
||||
src->full_height, flags);
|
||||
flags = 0;
|
||||
/* fall through */
|
||||
case MXR_GEOMETRY_SOURCE:
|
||||
src->full_width = clamp_val(src->full_width,
|
||||
src->width + src->x_offset, 32767);
|
||||
src->full_height = clamp_val(src->full_height,
|
||||
src->height + src->y_offset, 2047);
|
||||
}
|
||||
}
|
||||
|
||||
/* PUBLIC API */
|
||||
|
||||
struct mxr_layer *mxr_graph_layer_create(struct mxr_device *mdev, int idx)
|
||||
{
|
||||
struct mxr_layer *layer;
|
||||
int ret;
|
||||
const struct mxr_layer_ops ops = {
|
||||
.release = mxr_graph_layer_release,
|
||||
.buffer_set = mxr_graph_buffer_set,
|
||||
.stream_set = mxr_graph_stream_set,
|
||||
.format_set = mxr_graph_format_set,
|
||||
.fix_geometry = mxr_graph_fix_geometry,
|
||||
};
|
||||
char name[32];
|
||||
|
||||
sprintf(name, "graph%d", idx);
|
||||
|
||||
layer = mxr_base_layer_create(mdev, idx, name, &ops);
|
||||
if (layer == NULL) {
|
||||
mxr_err(mdev, "failed to initialize layer(%d) base\n", idx);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
layer->fmt_array = mxr_graph_format;
|
||||
layer->fmt_array_size = ARRAY_SIZE(mxr_graph_format);
|
||||
|
||||
ret = mxr_base_layer_register(layer);
|
||||
if (ret)
|
||||
goto fail_layer;
|
||||
|
||||
return layer;
|
||||
|
||||
fail_layer:
|
||||
mxr_base_layer_release(layer);
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -1,551 +0,0 @@
|
|||
/*
|
||||
* Samsung TV Mixer driver
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Tomasz Stanislawski, <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundiation. either version 2 of the License,
|
||||
* or (at your option) any later version
|
||||
*/
|
||||
|
||||
#include "mixer.h"
|
||||
#include "regs-mixer.h"
|
||||
#include "regs-vp.h"
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
/* Register access subroutines */
|
||||
|
||||
static inline u32 vp_read(struct mxr_device *mdev, u32 reg_id)
|
||||
{
|
||||
return readl(mdev->res.vp_regs + reg_id);
|
||||
}
|
||||
|
||||
static inline void vp_write(struct mxr_device *mdev, u32 reg_id, u32 val)
|
||||
{
|
||||
writel(val, mdev->res.vp_regs + reg_id);
|
||||
}
|
||||
|
||||
static inline void vp_write_mask(struct mxr_device *mdev, u32 reg_id,
|
||||
u32 val, u32 mask)
|
||||
{
|
||||
u32 old = vp_read(mdev, reg_id);
|
||||
|
||||
val = (val & mask) | (old & ~mask);
|
||||
writel(val, mdev->res.vp_regs + reg_id);
|
||||
}
|
||||
|
||||
static inline u32 mxr_read(struct mxr_device *mdev, u32 reg_id)
|
||||
{
|
||||
return readl(mdev->res.mxr_regs + reg_id);
|
||||
}
|
||||
|
||||
static inline void mxr_write(struct mxr_device *mdev, u32 reg_id, u32 val)
|
||||
{
|
||||
writel(val, mdev->res.mxr_regs + reg_id);
|
||||
}
|
||||
|
||||
static inline void mxr_write_mask(struct mxr_device *mdev, u32 reg_id,
|
||||
u32 val, u32 mask)
|
||||
{
|
||||
u32 old = mxr_read(mdev, reg_id);
|
||||
|
||||
val = (val & mask) | (old & ~mask);
|
||||
writel(val, mdev->res.mxr_regs + reg_id);
|
||||
}
|
||||
|
||||
void mxr_vsync_set_update(struct mxr_device *mdev, int en)
|
||||
{
|
||||
/* block update on vsync */
|
||||
mxr_write_mask(mdev, MXR_STATUS, en ? MXR_STATUS_SYNC_ENABLE : 0,
|
||||
MXR_STATUS_SYNC_ENABLE);
|
||||
vp_write(mdev, VP_SHADOW_UPDATE, en ? VP_SHADOW_UPDATE_ENABLE : 0);
|
||||
}
|
||||
|
||||
static void __mxr_reg_vp_reset(struct mxr_device *mdev)
|
||||
{
|
||||
int tries = 100;
|
||||
|
||||
vp_write(mdev, VP_SRESET, VP_SRESET_PROCESSING);
|
||||
for (tries = 100; tries; --tries) {
|
||||
/* waiting until VP_SRESET_PROCESSING is 0 */
|
||||
if (~vp_read(mdev, VP_SRESET) & VP_SRESET_PROCESSING)
|
||||
break;
|
||||
mdelay(10);
|
||||
}
|
||||
WARN(tries == 0, "failed to reset Video Processor\n");
|
||||
}
|
||||
|
||||
static void mxr_reg_vp_default_filter(struct mxr_device *mdev);
|
||||
|
||||
void mxr_reg_reset(struct mxr_device *mdev)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val; /* value stored to register */
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
mxr_vsync_set_update(mdev, MXR_DISABLE);
|
||||
|
||||
/* set output in RGB888 mode */
|
||||
mxr_write(mdev, MXR_CFG, MXR_CFG_OUT_RGB888);
|
||||
|
||||
/* 16 beat burst in DMA */
|
||||
mxr_write_mask(mdev, MXR_STATUS, MXR_STATUS_16_BURST,
|
||||
MXR_STATUS_BURST_MASK);
|
||||
|
||||
/* setting default layer priority: layer1 > video > layer0
|
||||
* because typical usage scenario would be
|
||||
* layer0 - framebuffer
|
||||
* video - video overlay
|
||||
* layer1 - OSD
|
||||
*/
|
||||
val = MXR_LAYER_CFG_GRP0_VAL(1);
|
||||
val |= MXR_LAYER_CFG_VP_VAL(2);
|
||||
val |= MXR_LAYER_CFG_GRP1_VAL(3);
|
||||
mxr_write(mdev, MXR_LAYER_CFG, val);
|
||||
|
||||
/* use dark gray background color */
|
||||
mxr_write(mdev, MXR_BG_COLOR0, 0x808080);
|
||||
mxr_write(mdev, MXR_BG_COLOR1, 0x808080);
|
||||
mxr_write(mdev, MXR_BG_COLOR2, 0x808080);
|
||||
|
||||
/* setting graphical layers */
|
||||
|
||||
val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
|
||||
val |= MXR_GRP_CFG_BLEND_PRE_MUL; /* premul mode */
|
||||
val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
|
||||
|
||||
/* the same configuration for both layers */
|
||||
mxr_write(mdev, MXR_GRAPHIC_CFG(0), val);
|
||||
mxr_write(mdev, MXR_GRAPHIC_CFG(1), val);
|
||||
|
||||
/* configuration of Video Processor Registers */
|
||||
__mxr_reg_vp_reset(mdev);
|
||||
mxr_reg_vp_default_filter(mdev);
|
||||
|
||||
/* enable all interrupts */
|
||||
mxr_write_mask(mdev, MXR_INT_EN, ~0, MXR_INT_EN_ALL);
|
||||
|
||||
mxr_vsync_set_update(mdev, MXR_ENABLE);
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
void mxr_reg_graph_format(struct mxr_device *mdev, int idx,
|
||||
const struct mxr_format *fmt, const struct mxr_geometry *geo)
|
||||
{
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
mxr_vsync_set_update(mdev, MXR_DISABLE);
|
||||
|
||||
/* setup format */
|
||||
mxr_write_mask(mdev, MXR_GRAPHIC_CFG(idx),
|
||||
MXR_GRP_CFG_FORMAT_VAL(fmt->cookie), MXR_GRP_CFG_FORMAT_MASK);
|
||||
|
||||
/* setup geometry */
|
||||
mxr_write(mdev, MXR_GRAPHIC_SPAN(idx), geo->src.full_width);
|
||||
val = MXR_GRP_WH_WIDTH(geo->src.width);
|
||||
val |= MXR_GRP_WH_HEIGHT(geo->src.height);
|
||||
val |= MXR_GRP_WH_H_SCALE(geo->x_ratio);
|
||||
val |= MXR_GRP_WH_V_SCALE(geo->y_ratio);
|
||||
mxr_write(mdev, MXR_GRAPHIC_WH(idx), val);
|
||||
|
||||
/* setup offsets in source image */
|
||||
val = MXR_GRP_SXY_SX(geo->src.x_offset);
|
||||
val |= MXR_GRP_SXY_SY(geo->src.y_offset);
|
||||
mxr_write(mdev, MXR_GRAPHIC_SXY(idx), val);
|
||||
|
||||
/* setup offsets in display image */
|
||||
val = MXR_GRP_DXY_DX(geo->dst.x_offset);
|
||||
val |= MXR_GRP_DXY_DY(geo->dst.y_offset);
|
||||
mxr_write(mdev, MXR_GRAPHIC_DXY(idx), val);
|
||||
|
||||
mxr_vsync_set_update(mdev, MXR_ENABLE);
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
void mxr_reg_vp_format(struct mxr_device *mdev,
|
||||
const struct mxr_format *fmt, const struct mxr_geometry *geo)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
mxr_vsync_set_update(mdev, MXR_DISABLE);
|
||||
|
||||
vp_write_mask(mdev, VP_MODE, fmt->cookie, VP_MODE_FMT_MASK);
|
||||
|
||||
/* setting size of input image */
|
||||
vp_write(mdev, VP_IMG_SIZE_Y, VP_IMG_HSIZE(geo->src.full_width) |
|
||||
VP_IMG_VSIZE(geo->src.full_height));
|
||||
/* chroma height has to reduced by 2 to avoid chroma distorions */
|
||||
vp_write(mdev, VP_IMG_SIZE_C, VP_IMG_HSIZE(geo->src.full_width) |
|
||||
VP_IMG_VSIZE(geo->src.full_height / 2));
|
||||
|
||||
vp_write(mdev, VP_SRC_WIDTH, geo->src.width);
|
||||
vp_write(mdev, VP_SRC_HEIGHT, geo->src.height);
|
||||
vp_write(mdev, VP_SRC_H_POSITION,
|
||||
VP_SRC_H_POSITION_VAL(geo->src.x_offset));
|
||||
vp_write(mdev, VP_SRC_V_POSITION, geo->src.y_offset);
|
||||
|
||||
vp_write(mdev, VP_DST_WIDTH, geo->dst.width);
|
||||
vp_write(mdev, VP_DST_H_POSITION, geo->dst.x_offset);
|
||||
if (geo->dst.field == V4L2_FIELD_INTERLACED) {
|
||||
vp_write(mdev, VP_DST_HEIGHT, geo->dst.height / 2);
|
||||
vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset / 2);
|
||||
} else {
|
||||
vp_write(mdev, VP_DST_HEIGHT, geo->dst.height);
|
||||
vp_write(mdev, VP_DST_V_POSITION, geo->dst.y_offset);
|
||||
}
|
||||
|
||||
vp_write(mdev, VP_H_RATIO, geo->x_ratio);
|
||||
vp_write(mdev, VP_V_RATIO, geo->y_ratio);
|
||||
|
||||
vp_write(mdev, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
|
||||
|
||||
mxr_vsync_set_update(mdev, MXR_ENABLE);
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
|
||||
}
|
||||
|
||||
void mxr_reg_graph_buffer(struct mxr_device *mdev, int idx, dma_addr_t addr)
|
||||
{
|
||||
u32 val = addr ? ~0 : 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
mxr_vsync_set_update(mdev, MXR_DISABLE);
|
||||
|
||||
if (idx == 0)
|
||||
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
|
||||
else
|
||||
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
|
||||
mxr_write(mdev, MXR_GRAPHIC_BASE(idx), addr);
|
||||
|
||||
mxr_vsync_set_update(mdev, MXR_ENABLE);
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
void mxr_reg_vp_buffer(struct mxr_device *mdev,
|
||||
dma_addr_t luma_addr[2], dma_addr_t chroma_addr[2])
|
||||
{
|
||||
u32 val = luma_addr[0] ? ~0 : 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
mxr_vsync_set_update(mdev, MXR_DISABLE);
|
||||
|
||||
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_VP_ENABLE);
|
||||
vp_write_mask(mdev, VP_ENABLE, val, VP_ENABLE_ON);
|
||||
/* TODO: fix tiled mode */
|
||||
vp_write(mdev, VP_TOP_Y_PTR, luma_addr[0]);
|
||||
vp_write(mdev, VP_TOP_C_PTR, chroma_addr[0]);
|
||||
vp_write(mdev, VP_BOT_Y_PTR, luma_addr[1]);
|
||||
vp_write(mdev, VP_BOT_C_PTR, chroma_addr[1]);
|
||||
|
||||
mxr_vsync_set_update(mdev, MXR_ENABLE);
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
static void mxr_irq_layer_handle(struct mxr_layer *layer)
|
||||
{
|
||||
struct list_head *head = &layer->enq_list;
|
||||
struct mxr_buffer *done;
|
||||
|
||||
/* skip non-existing layer */
|
||||
if (layer == NULL)
|
||||
return;
|
||||
|
||||
spin_lock(&layer->enq_slock);
|
||||
if (layer->state == MXR_LAYER_IDLE)
|
||||
goto done;
|
||||
|
||||
done = layer->shadow_buf;
|
||||
layer->shadow_buf = layer->update_buf;
|
||||
|
||||
if (list_empty(head)) {
|
||||
if (layer->state != MXR_LAYER_STREAMING)
|
||||
layer->update_buf = NULL;
|
||||
} else {
|
||||
struct mxr_buffer *next;
|
||||
next = list_first_entry(head, struct mxr_buffer, list);
|
||||
list_del(&next->list);
|
||||
layer->update_buf = next;
|
||||
}
|
||||
|
||||
layer->ops.buffer_set(layer, layer->update_buf);
|
||||
|
||||
if (done && done != layer->shadow_buf)
|
||||
vb2_buffer_done(&done->vb.vb2_buf, VB2_BUF_STATE_DONE);
|
||||
|
||||
done:
|
||||
spin_unlock(&layer->enq_slock);
|
||||
}
|
||||
|
||||
irqreturn_t mxr_irq_handler(int irq, void *dev_data)
|
||||
{
|
||||
struct mxr_device *mdev = dev_data;
|
||||
u32 i, val;
|
||||
|
||||
spin_lock(&mdev->reg_slock);
|
||||
val = mxr_read(mdev, MXR_INT_STATUS);
|
||||
|
||||
/* wake up process waiting for VSYNC */
|
||||
if (val & MXR_INT_STATUS_VSYNC) {
|
||||
set_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
|
||||
/* toggle TOP field event if working in interlaced mode */
|
||||
if (~mxr_read(mdev, MXR_CFG) & MXR_CFG_SCAN_PROGRASSIVE)
|
||||
change_bit(MXR_EVENT_TOP, &mdev->event_flags);
|
||||
wake_up(&mdev->event_queue);
|
||||
/* vsync interrupt use different bit for read and clear */
|
||||
val &= ~MXR_INT_STATUS_VSYNC;
|
||||
val |= MXR_INT_CLEAR_VSYNC;
|
||||
}
|
||||
|
||||
/* clear interrupts */
|
||||
mxr_write(mdev, MXR_INT_STATUS, val);
|
||||
|
||||
spin_unlock(&mdev->reg_slock);
|
||||
/* leave on non-vsync event */
|
||||
if (~val & MXR_INT_CLEAR_VSYNC)
|
||||
return IRQ_HANDLED;
|
||||
/* skip layer update on bottom field */
|
||||
if (!test_bit(MXR_EVENT_TOP, &mdev->event_flags))
|
||||
return IRQ_HANDLED;
|
||||
for (i = 0; i < MXR_MAX_LAYERS; ++i)
|
||||
mxr_irq_layer_handle(mdev->layer[i]);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
void mxr_reg_s_output(struct mxr_device *mdev, int cookie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = cookie == 0 ? MXR_CFG_DST_SDO : MXR_CFG_DST_HDMI;
|
||||
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_DST_MASK);
|
||||
}
|
||||
|
||||
void mxr_reg_streamon(struct mxr_device *mdev)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
/* single write -> no need to block vsync update */
|
||||
|
||||
/* start MIXER */
|
||||
mxr_write_mask(mdev, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
|
||||
set_bit(MXR_EVENT_TOP, &mdev->event_flags);
|
||||
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
void mxr_reg_streamoff(struct mxr_device *mdev)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
/* single write -> no need to block vsync update */
|
||||
|
||||
/* stop MIXER */
|
||||
mxr_write_mask(mdev, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
|
||||
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
int mxr_reg_wait4vsync(struct mxr_device *mdev)
|
||||
{
|
||||
long time_left;
|
||||
|
||||
clear_bit(MXR_EVENT_VSYNC, &mdev->event_flags);
|
||||
/* TODO: consider adding interruptible */
|
||||
time_left = wait_event_timeout(mdev->event_queue,
|
||||
test_bit(MXR_EVENT_VSYNC, &mdev->event_flags),
|
||||
msecs_to_jiffies(1000));
|
||||
if (time_left > 0)
|
||||
return 0;
|
||||
mxr_warn(mdev, "no vsync detected - timeout\n");
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
void mxr_reg_set_mbus_fmt(struct mxr_device *mdev,
|
||||
struct v4l2_mbus_framefmt *fmt)
|
||||
{
|
||||
u32 val = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mdev->reg_slock, flags);
|
||||
mxr_vsync_set_update(mdev, MXR_DISABLE);
|
||||
|
||||
/* selecting colorspace accepted by output */
|
||||
if (fmt->colorspace == V4L2_COLORSPACE_JPEG)
|
||||
val |= MXR_CFG_OUT_YUV444;
|
||||
else
|
||||
val |= MXR_CFG_OUT_RGB888;
|
||||
|
||||
/* choosing between interlace and progressive mode */
|
||||
if (fmt->field == V4L2_FIELD_INTERLACED)
|
||||
val |= MXR_CFG_SCAN_INTERLACE;
|
||||
else
|
||||
val |= MXR_CFG_SCAN_PROGRASSIVE;
|
||||
|
||||
/* choosing between porper HD and SD mode */
|
||||
if (fmt->height == 480)
|
||||
val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
|
||||
else if (fmt->height == 576)
|
||||
val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
|
||||
else if (fmt->height == 720)
|
||||
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
|
||||
else if (fmt->height == 1080)
|
||||
val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
|
||||
else
|
||||
WARN(1, "unrecognized mbus height %u!\n", fmt->height);
|
||||
|
||||
mxr_write_mask(mdev, MXR_CFG, val, MXR_CFG_SCAN_MASK |
|
||||
MXR_CFG_OUT_MASK);
|
||||
|
||||
val = (fmt->field == V4L2_FIELD_INTERLACED) ? ~0 : 0;
|
||||
vp_write_mask(mdev, VP_MODE, val,
|
||||
VP_MODE_LINE_SKIP | VP_MODE_FIELD_ID_AUTO_TOGGLING);
|
||||
|
||||
mxr_vsync_set_update(mdev, MXR_ENABLE);
|
||||
spin_unlock_irqrestore(&mdev->reg_slock, flags);
|
||||
}
|
||||
|
||||
void mxr_reg_graph_layer_stream(struct mxr_device *mdev, int idx, int en)
|
||||
{
|
||||
/* no extra actions need to be done */
|
||||
}
|
||||
|
||||
void mxr_reg_vp_layer_stream(struct mxr_device *mdev, int en)
|
||||
{
|
||||
/* no extra actions need to be done */
|
||||
}
|
||||
|
||||
static const u8 filter_y_horiz_tap8[] = {
|
||||
0, -1, -1, -1, -1, -1, -1, -1,
|
||||
-1, -1, -1, -1, -1, 0, 0, 0,
|
||||
0, 2, 4, 5, 6, 6, 6, 6,
|
||||
6, 5, 5, 4, 3, 2, 1, 1,
|
||||
0, -6, -12, -16, -18, -20, -21, -20,
|
||||
-20, -18, -16, -13, -10, -8, -5, -2,
|
||||
127, 126, 125, 121, 114, 107, 99, 89,
|
||||
79, 68, 57, 46, 35, 25, 16, 8,
|
||||
};
|
||||
|
||||
static const u8 filter_y_vert_tap4[] = {
|
||||
0, -3, -6, -8, -8, -8, -8, -7,
|
||||
-6, -5, -4, -3, -2, -1, -1, 0,
|
||||
127, 126, 124, 118, 111, 102, 92, 81,
|
||||
70, 59, 48, 37, 27, 19, 11, 5,
|
||||
0, 5, 11, 19, 27, 37, 48, 59,
|
||||
70, 81, 92, 102, 111, 118, 124, 126,
|
||||
0, 0, -1, -1, -2, -3, -4, -5,
|
||||
-6, -7, -8, -8, -8, -8, -6, -3,
|
||||
};
|
||||
|
||||
static const u8 filter_cr_horiz_tap4[] = {
|
||||
0, -3, -6, -8, -8, -8, -8, -7,
|
||||
-6, -5, -4, -3, -2, -1, -1, 0,
|
||||
127, 126, 124, 118, 111, 102, 92, 81,
|
||||
70, 59, 48, 37, 27, 19, 11, 5,
|
||||
};
|
||||
|
||||
static inline void mxr_reg_vp_filter_set(struct mxr_device *mdev,
|
||||
int reg_id, const u8 *data, unsigned int size)
|
||||
{
|
||||
/* assure 4-byte align */
|
||||
BUG_ON(size & 3);
|
||||
for (; size; size -= 4, reg_id += 4, data += 4) {
|
||||
u32 val = (data[0] << 24) | (data[1] << 16) |
|
||||
(data[2] << 8) | data[3];
|
||||
vp_write(mdev, reg_id, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void mxr_reg_vp_default_filter(struct mxr_device *mdev)
|
||||
{
|
||||
mxr_reg_vp_filter_set(mdev, VP_POLY8_Y0_LL,
|
||||
filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
|
||||
mxr_reg_vp_filter_set(mdev, VP_POLY4_Y0_LL,
|
||||
filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
|
||||
mxr_reg_vp_filter_set(mdev, VP_POLY4_C0_LL,
|
||||
filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
|
||||
}
|
||||
|
||||
static void mxr_reg_mxr_dump(struct mxr_device *mdev)
|
||||
{
|
||||
#define DUMPREG(reg_id) \
|
||||
do { \
|
||||
mxr_dbg(mdev, #reg_id " = %08x\n", \
|
||||
(u32)readl(mdev->res.mxr_regs + reg_id)); \
|
||||
} while (0)
|
||||
|
||||
DUMPREG(MXR_STATUS);
|
||||
DUMPREG(MXR_CFG);
|
||||
DUMPREG(MXR_INT_EN);
|
||||
DUMPREG(MXR_INT_STATUS);
|
||||
|
||||
DUMPREG(MXR_LAYER_CFG);
|
||||
DUMPREG(MXR_VIDEO_CFG);
|
||||
|
||||
DUMPREG(MXR_GRAPHIC0_CFG);
|
||||
DUMPREG(MXR_GRAPHIC0_BASE);
|
||||
DUMPREG(MXR_GRAPHIC0_SPAN);
|
||||
DUMPREG(MXR_GRAPHIC0_WH);
|
||||
DUMPREG(MXR_GRAPHIC0_SXY);
|
||||
DUMPREG(MXR_GRAPHIC0_DXY);
|
||||
|
||||
DUMPREG(MXR_GRAPHIC1_CFG);
|
||||
DUMPREG(MXR_GRAPHIC1_BASE);
|
||||
DUMPREG(MXR_GRAPHIC1_SPAN);
|
||||
DUMPREG(MXR_GRAPHIC1_WH);
|
||||
DUMPREG(MXR_GRAPHIC1_SXY);
|
||||
DUMPREG(MXR_GRAPHIC1_DXY);
|
||||
#undef DUMPREG
|
||||
}
|
||||
|
||||
static void mxr_reg_vp_dump(struct mxr_device *mdev)
|
||||
{
|
||||
#define DUMPREG(reg_id) \
|
||||
do { \
|
||||
mxr_dbg(mdev, #reg_id " = %08x\n", \
|
||||
(u32) readl(mdev->res.vp_regs + reg_id)); \
|
||||
} while (0)
|
||||
|
||||
|
||||
DUMPREG(VP_ENABLE);
|
||||
DUMPREG(VP_SRESET);
|
||||
DUMPREG(VP_SHADOW_UPDATE);
|
||||
DUMPREG(VP_FIELD_ID);
|
||||
DUMPREG(VP_MODE);
|
||||
DUMPREG(VP_IMG_SIZE_Y);
|
||||
DUMPREG(VP_IMG_SIZE_C);
|
||||
DUMPREG(VP_PER_RATE_CTRL);
|
||||
DUMPREG(VP_TOP_Y_PTR);
|
||||
DUMPREG(VP_BOT_Y_PTR);
|
||||
DUMPREG(VP_TOP_C_PTR);
|
||||
DUMPREG(VP_BOT_C_PTR);
|
||||
DUMPREG(VP_ENDIAN_MODE);
|
||||
DUMPREG(VP_SRC_H_POSITION);
|
||||
DUMPREG(VP_SRC_V_POSITION);
|
||||
DUMPREG(VP_SRC_WIDTH);
|
||||
DUMPREG(VP_SRC_HEIGHT);
|
||||
DUMPREG(VP_DST_H_POSITION);
|
||||
DUMPREG(VP_DST_V_POSITION);
|
||||
DUMPREG(VP_DST_WIDTH);
|
||||
DUMPREG(VP_DST_HEIGHT);
|
||||
DUMPREG(VP_H_RATIO);
|
||||
DUMPREG(VP_V_RATIO);
|
||||
|
||||
#undef DUMPREG
|
||||
}
|
||||
|
||||
void mxr_reg_dump(struct mxr_device *mdev)
|
||||
{
|
||||
mxr_reg_mxr_dump(mdev);
|
||||
mxr_reg_vp_dump(mdev);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,242 +0,0 @@
|
|||
/*
|
||||
* Samsung TV Mixer driver
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Tomasz Stanislawski, <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundiation. either version 2 of the License,
|
||||
* or (at your option) any later version
|
||||
*/
|
||||
|
||||
#include "mixer.h"
|
||||
|
||||
#include "regs-vp.h"
|
||||
|
||||
#include <media/videobuf2-dma-contig.h>
|
||||
|
||||
/* FORMAT DEFINITIONS */
|
||||
static const struct mxr_format mxr_fmt_nv12 = {
|
||||
.name = "NV12",
|
||||
.fourcc = V4L2_PIX_FMT_NV12,
|
||||
.colorspace = V4L2_COLORSPACE_JPEG,
|
||||
.num_planes = 2,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 1 },
|
||||
{ .width = 2, .height = 2, .size = 2 },
|
||||
},
|
||||
.num_subframes = 1,
|
||||
.cookie = VP_MODE_NV12 | VP_MODE_MEM_LINEAR,
|
||||
};
|
||||
|
||||
static const struct mxr_format mxr_fmt_nv21 = {
|
||||
.name = "NV21",
|
||||
.fourcc = V4L2_PIX_FMT_NV21,
|
||||
.colorspace = V4L2_COLORSPACE_JPEG,
|
||||
.num_planes = 2,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 1 },
|
||||
{ .width = 2, .height = 2, .size = 2 },
|
||||
},
|
||||
.num_subframes = 1,
|
||||
.cookie = VP_MODE_NV21 | VP_MODE_MEM_LINEAR,
|
||||
};
|
||||
|
||||
static const struct mxr_format mxr_fmt_nv12m = {
|
||||
.name = "NV12 (mplane)",
|
||||
.fourcc = V4L2_PIX_FMT_NV12M,
|
||||
.colorspace = V4L2_COLORSPACE_JPEG,
|
||||
.num_planes = 2,
|
||||
.plane = {
|
||||
{ .width = 1, .height = 1, .size = 1 },
|
||||
{ .width = 2, .height = 2, .size = 2 },
|
||||
},
|
||||
.num_subframes = 2,
|
||||
.plane2subframe = {0, 1},
|
||||
.cookie = VP_MODE_NV12 | VP_MODE_MEM_LINEAR,
|
||||
};
|
||||
|
||||
static const struct mxr_format mxr_fmt_nv12mt = {
|
||||
.name = "NV12 tiled (mplane)",
|
||||
.fourcc = V4L2_PIX_FMT_NV12MT,
|
||||
.colorspace = V4L2_COLORSPACE_JPEG,
|
||||
.num_planes = 2,
|
||||
.plane = {
|
||||
{ .width = 128, .height = 32, .size = 4096 },
|
||||
{ .width = 128, .height = 32, .size = 2048 },
|
||||
},
|
||||
.num_subframes = 2,
|
||||
.plane2subframe = {0, 1},
|
||||
.cookie = VP_MODE_NV12 | VP_MODE_MEM_TILED,
|
||||
};
|
||||
|
||||
static const struct mxr_format *mxr_video_format[] = {
|
||||
&mxr_fmt_nv12,
|
||||
&mxr_fmt_nv21,
|
||||
&mxr_fmt_nv12m,
|
||||
&mxr_fmt_nv12mt,
|
||||
};
|
||||
|
||||
/* AUXILIARY CALLBACKS */
|
||||
|
||||
static void mxr_vp_layer_release(struct mxr_layer *layer)
|
||||
{
|
||||
mxr_base_layer_unregister(layer);
|
||||
mxr_base_layer_release(layer);
|
||||
}
|
||||
|
||||
static void mxr_vp_buffer_set(struct mxr_layer *layer,
|
||||
struct mxr_buffer *buf)
|
||||
{
|
||||
dma_addr_t luma_addr[2] = {0, 0};
|
||||
dma_addr_t chroma_addr[2] = {0, 0};
|
||||
|
||||
if (buf == NULL) {
|
||||
mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);
|
||||
return;
|
||||
}
|
||||
luma_addr[0] = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
|
||||
if (layer->fmt->num_subframes == 2) {
|
||||
chroma_addr[0] =
|
||||
vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 1);
|
||||
} else {
|
||||
/* FIXME: mxr_get_plane_size compute integer division,
|
||||
* which is slow and should not be performed in interrupt */
|
||||
chroma_addr[0] = luma_addr[0] + mxr_get_plane_size(
|
||||
&layer->fmt->plane[0], layer->geo.src.full_width,
|
||||
layer->geo.src.full_height);
|
||||
}
|
||||
if (layer->fmt->cookie & VP_MODE_MEM_TILED) {
|
||||
luma_addr[1] = luma_addr[0] + 0x40;
|
||||
chroma_addr[1] = chroma_addr[0] + 0x40;
|
||||
} else {
|
||||
luma_addr[1] = luma_addr[0] + layer->geo.src.full_width;
|
||||
chroma_addr[1] = chroma_addr[0];
|
||||
}
|
||||
mxr_reg_vp_buffer(layer->mdev, luma_addr, chroma_addr);
|
||||
}
|
||||
|
||||
static void mxr_vp_stream_set(struct mxr_layer *layer, int en)
|
||||
{
|
||||
mxr_reg_vp_layer_stream(layer->mdev, en);
|
||||
}
|
||||
|
||||
static void mxr_vp_format_set(struct mxr_layer *layer)
|
||||
{
|
||||
mxr_reg_vp_format(layer->mdev, layer->fmt, &layer->geo);
|
||||
}
|
||||
|
||||
static inline unsigned int do_center(unsigned int center,
|
||||
unsigned int size, unsigned int upper, unsigned int flags)
|
||||
{
|
||||
unsigned int lower;
|
||||
|
||||
if (flags & MXR_NO_OFFSET)
|
||||
return 0;
|
||||
|
||||
lower = center - min(center, size / 2);
|
||||
return min(lower, upper - size);
|
||||
}
|
||||
|
||||
static void mxr_vp_fix_geometry(struct mxr_layer *layer,
|
||||
enum mxr_geometry_stage stage, unsigned long flags)
|
||||
{
|
||||
struct mxr_geometry *geo = &layer->geo;
|
||||
struct mxr_crop *src = &geo->src;
|
||||
struct mxr_crop *dst = &geo->dst;
|
||||
unsigned long x_center, y_center;
|
||||
|
||||
switch (stage) {
|
||||
|
||||
case MXR_GEOMETRY_SINK: /* nothing to be fixed here */
|
||||
case MXR_GEOMETRY_COMPOSE:
|
||||
/* remember center of the area */
|
||||
x_center = dst->x_offset + dst->width / 2;
|
||||
y_center = dst->y_offset + dst->height / 2;
|
||||
|
||||
/* ensure that compose is reachable using 16x scaling */
|
||||
dst->width = clamp(dst->width, 8U, 16 * src->full_width);
|
||||
dst->height = clamp(dst->height, 1U, 16 * src->full_height);
|
||||
|
||||
/* setup offsets */
|
||||
dst->x_offset = do_center(x_center, dst->width,
|
||||
dst->full_width, flags);
|
||||
dst->y_offset = do_center(y_center, dst->height,
|
||||
dst->full_height, flags);
|
||||
flags = 0; /* remove possible MXR_NO_OFFSET flag */
|
||||
/* fall through */
|
||||
case MXR_GEOMETRY_CROP:
|
||||
/* remember center of the area */
|
||||
x_center = src->x_offset + src->width / 2;
|
||||
y_center = src->y_offset + src->height / 2;
|
||||
|
||||
/* ensure scaling is between 0.25x .. 16x */
|
||||
src->width = clamp(src->width, round_up(dst->width / 16, 4),
|
||||
dst->width * 4);
|
||||
src->height = clamp(src->height, round_up(dst->height / 16, 4),
|
||||
dst->height * 4);
|
||||
|
||||
/* hardware limits */
|
||||
src->width = clamp(src->width, 32U, 2047U);
|
||||
src->height = clamp(src->height, 4U, 2047U);
|
||||
|
||||
/* setup offsets */
|
||||
src->x_offset = do_center(x_center, src->width,
|
||||
src->full_width, flags);
|
||||
src->y_offset = do_center(y_center, src->height,
|
||||
src->full_height, flags);
|
||||
|
||||
/* setting scaling ratio */
|
||||
geo->x_ratio = (src->width << 16) / dst->width;
|
||||
geo->y_ratio = (src->height << 16) / dst->height;
|
||||
/* fall through */
|
||||
|
||||
case MXR_GEOMETRY_SOURCE:
|
||||
src->full_width = clamp(src->full_width,
|
||||
ALIGN(src->width + src->x_offset, 8), 8192U);
|
||||
src->full_height = clamp(src->full_height,
|
||||
src->height + src->y_offset, 8192U);
|
||||
}
|
||||
}
|
||||
|
||||
/* PUBLIC API */
|
||||
|
||||
struct mxr_layer *mxr_vp_layer_create(struct mxr_device *mdev, int idx)
|
||||
{
|
||||
struct mxr_layer *layer;
|
||||
int ret;
|
||||
const struct mxr_layer_ops ops = {
|
||||
.release = mxr_vp_layer_release,
|
||||
.buffer_set = mxr_vp_buffer_set,
|
||||
.stream_set = mxr_vp_stream_set,
|
||||
.format_set = mxr_vp_format_set,
|
||||
.fix_geometry = mxr_vp_fix_geometry,
|
||||
};
|
||||
char name[32];
|
||||
|
||||
sprintf(name, "video%d", idx);
|
||||
|
||||
layer = mxr_base_layer_create(mdev, idx, name, &ops);
|
||||
if (layer == NULL) {
|
||||
mxr_err(mdev, "failed to initialize layer(%d) base\n", idx);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
layer->fmt_array = mxr_video_format;
|
||||
layer->fmt_array_size = ARRAY_SIZE(mxr_video_format);
|
||||
|
||||
ret = mxr_base_layer_register(layer);
|
||||
if (ret)
|
||||
goto fail_layer;
|
||||
|
||||
return layer;
|
||||
|
||||
fail_layer:
|
||||
mxr_base_layer_release(layer);
|
||||
|
||||
fail:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -1,146 +0,0 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* HDMI register header file for Samsung TVOUT driver
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef SAMSUNG_REGS_HDMI_H
|
||||
#define SAMSUNG_REGS_HDMI_H
|
||||
|
||||
/*
|
||||
* Register part
|
||||
*/
|
||||
|
||||
#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
|
||||
#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
|
||||
#define HDMI_TG_BASE(x) ((x) + 0x00050000)
|
||||
|
||||
/* Control registers */
|
||||
#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
|
||||
#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
|
||||
#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
|
||||
#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
|
||||
#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018)
|
||||
#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C)
|
||||
#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
|
||||
|
||||
/* Core registers */
|
||||
#define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
|
||||
#define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
|
||||
#define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
|
||||
#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
|
||||
#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014)
|
||||
#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
|
||||
#define HDMI_HPD HDMI_CORE_BASE(0x0030)
|
||||
#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
|
||||
#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
|
||||
#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
|
||||
#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
|
||||
#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
|
||||
#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
|
||||
#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
|
||||
#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
|
||||
#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
|
||||
#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
|
||||
#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
|
||||
#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
|
||||
#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
|
||||
#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
|
||||
#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
|
||||
#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
|
||||
#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
|
||||
#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
|
||||
#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
|
||||
#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
|
||||
#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
|
||||
#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
|
||||
#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
|
||||
#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
|
||||
#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
|
||||
#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
|
||||
#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
|
||||
#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
|
||||
#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
|
||||
#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300)
|
||||
#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
|
||||
#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0)
|
||||
#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
|
||||
#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)
|
||||
|
||||
/* Timing generator registers */
|
||||
#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
|
||||
#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
|
||||
#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)
|
||||
#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)
|
||||
#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)
|
||||
#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)
|
||||
#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)
|
||||
#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)
|
||||
#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)
|
||||
#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)
|
||||
#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)
|
||||
#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)
|
||||
#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)
|
||||
#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)
|
||||
#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)
|
||||
#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)
|
||||
#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)
|
||||
#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)
|
||||
#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)
|
||||
#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)
|
||||
#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)
|
||||
#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)
|
||||
#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)
|
||||
#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)
|
||||
#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)
|
||||
#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)
|
||||
#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)
|
||||
#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)
|
||||
#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)
|
||||
|
||||
/*
|
||||
* Bit definition part
|
||||
*/
|
||||
|
||||
/* HDMI_INTC_CON */
|
||||
#define HDMI_INTC_EN_GLOBAL (1 << 6)
|
||||
#define HDMI_INTC_EN_HPD_PLUG (1 << 3)
|
||||
#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)
|
||||
|
||||
/* HDMI_INTC_FLAG */
|
||||
#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)
|
||||
#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)
|
||||
|
||||
/* HDMI_PHY_RSTOUT */
|
||||
#define HDMI_PHY_SW_RSTOUT (1 << 0)
|
||||
|
||||
/* HDMI_CORE_RSTOUT */
|
||||
#define HDMI_CORE_SW_RSTOUT (1 << 0)
|
||||
|
||||
/* HDMI_CON_0 */
|
||||
#define HDMI_BLUE_SCR_EN (1 << 5)
|
||||
#define HDMI_EN (1 << 0)
|
||||
|
||||
/* HDMI_CON_2 */
|
||||
#define HDMI_DVI_PERAMBLE_EN (1 << 5)
|
||||
#define HDMI_DVI_BAND_EN (1 << 1)
|
||||
|
||||
/* HDMI_PHY_STATUS */
|
||||
#define HDMI_PHY_STATUS_READY (1 << 0)
|
||||
|
||||
/* HDMI_MODE_SEL */
|
||||
#define HDMI_MODE_HDMI_EN (1 << 1)
|
||||
#define HDMI_MODE_DVI_EN (1 << 0)
|
||||
#define HDMI_MODE_MASK (3 << 0)
|
||||
|
||||
/* HDMI_TG_CMD */
|
||||
#define HDMI_TG_FIELD_EN (1 << 1)
|
||||
#define HDMI_TG_EN (1 << 0)
|
||||
|
||||
#endif /* SAMSUNG_REGS_HDMI_H */
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Mixer register header file for Samsung Mixer driver
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef SAMSUNG_REGS_MIXER_H
|
||||
#define SAMSUNG_REGS_MIXER_H
|
||||
|
||||
/*
|
||||
* Register part
|
||||
*/
|
||||
#define MXR_STATUS 0x0000
|
||||
#define MXR_CFG 0x0004
|
||||
#define MXR_INT_EN 0x0008
|
||||
#define MXR_INT_STATUS 0x000C
|
||||
#define MXR_LAYER_CFG 0x0010
|
||||
#define MXR_VIDEO_CFG 0x0014
|
||||
#define MXR_GRAPHIC0_CFG 0x0020
|
||||
#define MXR_GRAPHIC0_BASE 0x0024
|
||||
#define MXR_GRAPHIC0_SPAN 0x0028
|
||||
#define MXR_GRAPHIC0_SXY 0x002C
|
||||
#define MXR_GRAPHIC0_WH 0x0030
|
||||
#define MXR_GRAPHIC0_DXY 0x0034
|
||||
#define MXR_GRAPHIC0_BLANK 0x0038
|
||||
#define MXR_GRAPHIC1_CFG 0x0040
|
||||
#define MXR_GRAPHIC1_BASE 0x0044
|
||||
#define MXR_GRAPHIC1_SPAN 0x0048
|
||||
#define MXR_GRAPHIC1_SXY 0x004C
|
||||
#define MXR_GRAPHIC1_WH 0x0050
|
||||
#define MXR_GRAPHIC1_DXY 0x0054
|
||||
#define MXR_GRAPHIC1_BLANK 0x0058
|
||||
#define MXR_BG_CFG 0x0060
|
||||
#define MXR_BG_COLOR0 0x0064
|
||||
#define MXR_BG_COLOR1 0x0068
|
||||
#define MXR_BG_COLOR2 0x006C
|
||||
|
||||
/* for parametrized access to layer registers */
|
||||
#define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20)
|
||||
#define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20)
|
||||
#define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20)
|
||||
#define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20)
|
||||
#define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20)
|
||||
#define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20)
|
||||
|
||||
/*
|
||||
* Bit definition part
|
||||
*/
|
||||
|
||||
/* generates mask for range of bits */
|
||||
#define MXR_MASK(high_bit, low_bit) \
|
||||
(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
|
||||
|
||||
#define MXR_MASK_VAL(val, high_bit, low_bit) \
|
||||
(((val) << (low_bit)) & MXR_MASK(high_bit, low_bit))
|
||||
|
||||
/* bits for MXR_STATUS */
|
||||
#define MXR_STATUS_16_BURST (1 << 7)
|
||||
#define MXR_STATUS_BURST_MASK (1 << 7)
|
||||
#define MXR_STATUS_SYNC_ENABLE (1 << 2)
|
||||
#define MXR_STATUS_REG_RUN (1 << 0)
|
||||
|
||||
/* bits for MXR_CFG */
|
||||
#define MXR_CFG_OUT_YUV444 (0 << 8)
|
||||
#define MXR_CFG_OUT_RGB888 (1 << 8)
|
||||
#define MXR_CFG_OUT_MASK (1 << 8)
|
||||
#define MXR_CFG_DST_SDO (0 << 7)
|
||||
#define MXR_CFG_DST_HDMI (1 << 7)
|
||||
#define MXR_CFG_DST_MASK (1 << 7)
|
||||
#define MXR_CFG_SCAN_HD_720 (0 << 6)
|
||||
#define MXR_CFG_SCAN_HD_1080 (1 << 6)
|
||||
#define MXR_CFG_GRP1_ENABLE (1 << 5)
|
||||
#define MXR_CFG_GRP0_ENABLE (1 << 4)
|
||||
#define MXR_CFG_VP_ENABLE (1 << 3)
|
||||
#define MXR_CFG_SCAN_INTERLACE (0 << 2)
|
||||
#define MXR_CFG_SCAN_PROGRASSIVE (1 << 2)
|
||||
#define MXR_CFG_SCAN_NTSC (0 << 1)
|
||||
#define MXR_CFG_SCAN_PAL (1 << 1)
|
||||
#define MXR_CFG_SCAN_SD (0 << 0)
|
||||
#define MXR_CFG_SCAN_HD (1 << 0)
|
||||
#define MXR_CFG_SCAN_MASK 0x47
|
||||
|
||||
/* bits for MXR_GRAPHICn_CFG */
|
||||
#define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21)
|
||||
#define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20)
|
||||
#define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8)
|
||||
#define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0)
|
||||
#define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)
|
||||
|
||||
/* bits for MXR_GRAPHICn_WH */
|
||||
#define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28)
|
||||
#define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12)
|
||||
#define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16)
|
||||
#define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)
|
||||
|
||||
/* bits for MXR_GRAPHICn_SXY */
|
||||
#define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16)
|
||||
#define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0)
|
||||
|
||||
/* bits for MXR_GRAPHICn_DXY */
|
||||
#define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16)
|
||||
#define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0)
|
||||
|
||||
/* bits for MXR_INT_EN */
|
||||
#define MXR_INT_EN_VSYNC (1 << 11)
|
||||
#define MXR_INT_EN_ALL (0x0f << 8)
|
||||
|
||||
/* bit for MXR_INT_STATUS */
|
||||
#define MXR_INT_CLEAR_VSYNC (1 << 11)
|
||||
#define MXR_INT_STATUS_VSYNC (1 << 0)
|
||||
|
||||
/* bit for MXR_LAYER_CFG */
|
||||
#define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8)
|
||||
#define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4)
|
||||
#define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0)
|
||||
|
||||
#endif /* SAMSUNG_REGS_MIXER_H */
|
||||
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/* drivers/media/platform/s5p-tv/regs-sdo.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* SDO register description file
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef SAMSUNG_REGS_SDO_H
|
||||
#define SAMSUNG_REGS_SDO_H
|
||||
|
||||
/*
|
||||
* Register part
|
||||
*/
|
||||
|
||||
#define SDO_CLKCON 0x0000
|
||||
#define SDO_CONFIG 0x0008
|
||||
#define SDO_VBI 0x0014
|
||||
#define SDO_DAC 0x003C
|
||||
#define SDO_CCCON 0x0180
|
||||
#define SDO_IRQ 0x0280
|
||||
#define SDO_IRQMASK 0x0284
|
||||
#define SDO_VERSION 0x03D8
|
||||
|
||||
/*
|
||||
* Bit definition part
|
||||
*/
|
||||
|
||||
/* SDO Clock Control Register (SDO_CLKCON) */
|
||||
#define SDO_TVOUT_SW_RESET (1 << 4)
|
||||
#define SDO_TVOUT_CLOCK_READY (1 << 1)
|
||||
#define SDO_TVOUT_CLOCK_ON (1 << 0)
|
||||
|
||||
/* SDO Video Standard Configuration Register (SDO_CONFIG) */
|
||||
#define SDO_PROGRESSIVE (1 << 4)
|
||||
#define SDO_NTSC_M 0
|
||||
#define SDO_PAL_M 1
|
||||
#define SDO_PAL_BGHID 2
|
||||
#define SDO_PAL_N 3
|
||||
#define SDO_PAL_NC 4
|
||||
#define SDO_NTSC_443 8
|
||||
#define SDO_PAL_60 9
|
||||
#define SDO_STANDARD_MASK 0xf
|
||||
|
||||
/* SDO VBI Configuration Register (SDO_VBI) */
|
||||
#define SDO_CVBS_WSS_INS (1 << 14)
|
||||
#define SDO_CVBS_CLOSED_CAPTION_MASK (3 << 12)
|
||||
|
||||
/* SDO DAC Configuration Register (SDO_DAC) */
|
||||
#define SDO_POWER_ON_DAC (1 << 0)
|
||||
|
||||
/* SDO Color Compensation On/Off Control (SDO_CCCON) */
|
||||
#define SDO_COMPENSATION_BHS_ADJ_OFF (1 << 4)
|
||||
#define SDO_COMPENSATION_CVBS_COMP_OFF (1 << 0)
|
||||
|
||||
/* SDO Interrupt Request Register (SDO_IRQ) */
|
||||
#define SDO_VSYNC_IRQ_PEND (1 << 0)
|
||||
|
||||
#endif /* SAMSUNG_REGS_SDO_H */
|
||||
|
|
@ -1,88 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Video processor register header file for Samsung Mixer driver
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef SAMSUNG_REGS_VP_H
|
||||
#define SAMSUNG_REGS_VP_H
|
||||
|
||||
/*
|
||||
* Register part
|
||||
*/
|
||||
|
||||
#define VP_ENABLE 0x0000
|
||||
#define VP_SRESET 0x0004
|
||||
#define VP_SHADOW_UPDATE 0x0008
|
||||
#define VP_FIELD_ID 0x000C
|
||||
#define VP_MODE 0x0010
|
||||
#define VP_IMG_SIZE_Y 0x0014
|
||||
#define VP_IMG_SIZE_C 0x0018
|
||||
#define VP_PER_RATE_CTRL 0x001C
|
||||
#define VP_TOP_Y_PTR 0x0028
|
||||
#define VP_BOT_Y_PTR 0x002C
|
||||
#define VP_TOP_C_PTR 0x0030
|
||||
#define VP_BOT_C_PTR 0x0034
|
||||
#define VP_ENDIAN_MODE 0x03CC
|
||||
#define VP_SRC_H_POSITION 0x0044
|
||||
#define VP_SRC_V_POSITION 0x0048
|
||||
#define VP_SRC_WIDTH 0x004C
|
||||
#define VP_SRC_HEIGHT 0x0050
|
||||
#define VP_DST_H_POSITION 0x0054
|
||||
#define VP_DST_V_POSITION 0x0058
|
||||
#define VP_DST_WIDTH 0x005C
|
||||
#define VP_DST_HEIGHT 0x0060
|
||||
#define VP_H_RATIO 0x0064
|
||||
#define VP_V_RATIO 0x0068
|
||||
#define VP_POLY8_Y0_LL 0x006C
|
||||
#define VP_POLY4_Y0_LL 0x00EC
|
||||
#define VP_POLY4_C0_LL 0x012C
|
||||
|
||||
/*
|
||||
* Bit definition part
|
||||
*/
|
||||
|
||||
/* generates mask for range of bits */
|
||||
|
||||
#define VP_MASK(high_bit, low_bit) \
|
||||
(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
|
||||
|
||||
#define VP_MASK_VAL(val, high_bit, low_bit) \
|
||||
(((val) << (low_bit)) & VP_MASK(high_bit, low_bit))
|
||||
|
||||
/* VP_ENABLE */
|
||||
#define VP_ENABLE_ON (1 << 0)
|
||||
|
||||
/* VP_SRESET */
|
||||
#define VP_SRESET_PROCESSING (1 << 0)
|
||||
|
||||
/* VP_SHADOW_UPDATE */
|
||||
#define VP_SHADOW_UPDATE_ENABLE (1 << 0)
|
||||
|
||||
/* VP_MODE */
|
||||
#define VP_MODE_NV12 (0 << 6)
|
||||
#define VP_MODE_NV21 (1 << 6)
|
||||
#define VP_MODE_LINE_SKIP (1 << 5)
|
||||
#define VP_MODE_MEM_LINEAR (0 << 4)
|
||||
#define VP_MODE_MEM_TILED (1 << 4)
|
||||
#define VP_MODE_FMT_MASK (5 << 4)
|
||||
#define VP_MODE_FIELD_ID_AUTO_TOGGLING (1 << 2)
|
||||
#define VP_MODE_2D_IPC (1 << 1)
|
||||
|
||||
/* VP_IMG_SIZE_Y */
|
||||
/* VP_IMG_SIZE_C */
|
||||
#define VP_IMG_HSIZE(x) VP_MASK_VAL(x, 29, 16)
|
||||
#define VP_IMG_VSIZE(x) VP_MASK_VAL(x, 13, 0)
|
||||
|
||||
/* VP_SRC_H_POSITION */
|
||||
#define VP_SRC_H_POSITION_VAL(x) VP_MASK_VAL(x, 14, 4)
|
||||
|
||||
/* VP_ENDIAN_MODE */
|
||||
#define VP_ENDIAN_MODE_LITTLE (1 << 0)
|
||||
|
||||
#endif /* SAMSUNG_REGS_VP_H */
|
||||
|
|
@ -1,497 +0,0 @@
|
|||
/*
|
||||
* Samsung Standard Definition Output (SDO) driver
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Tomasz Stanislawski, <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published
|
||||
* by the Free Software Foundiation. either version 2 of the License,
|
||||
* or (at your option) any later version
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <media/v4l2-subdev.h>
|
||||
|
||||
#include "regs-sdo.h"
|
||||
|
||||
MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
|
||||
MODULE_DESCRIPTION("Samsung Standard Definition Output (SDO)");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
#define SDO_DEFAULT_STD V4L2_STD_PAL
|
||||
|
||||
struct sdo_format {
|
||||
v4l2_std_id id;
|
||||
/* all modes are 720 pixels wide */
|
||||
unsigned int height;
|
||||
unsigned int cookie;
|
||||
};
|
||||
|
||||
struct sdo_device {
|
||||
/** pointer to device parent */
|
||||
struct device *dev;
|
||||
/** base address of SDO registers */
|
||||
void __iomem *regs;
|
||||
/** SDO interrupt */
|
||||
unsigned int irq;
|
||||
/** DAC source clock */
|
||||
struct clk *sclk_dac;
|
||||
/** DAC clock */
|
||||
struct clk *dac;
|
||||
/** DAC physical interface */
|
||||
struct clk *dacphy;
|
||||
/** clock for control of VPLL */
|
||||
struct clk *fout_vpll;
|
||||
/** vpll rate before sdo stream was on */
|
||||
unsigned long vpll_rate;
|
||||
/** regulator for SDO IP power */
|
||||
struct regulator *vdac;
|
||||
/** regulator for SDO plug detection */
|
||||
struct regulator *vdet;
|
||||
/** subdev used as device interface */
|
||||
struct v4l2_subdev sd;
|
||||
/** current format */
|
||||
const struct sdo_format *fmt;
|
||||
};
|
||||
|
||||
static inline struct sdo_device *sd_to_sdev(struct v4l2_subdev *sd)
|
||||
{
|
||||
return container_of(sd, struct sdo_device, sd);
|
||||
}
|
||||
|
||||
static inline
|
||||
void sdo_write_mask(struct sdo_device *sdev, u32 reg_id, u32 value, u32 mask)
|
||||
{
|
||||
u32 old = readl(sdev->regs + reg_id);
|
||||
value = (value & mask) | (old & ~mask);
|
||||
writel(value, sdev->regs + reg_id);
|
||||
}
|
||||
|
||||
static inline
|
||||
void sdo_write(struct sdo_device *sdev, u32 reg_id, u32 value)
|
||||
{
|
||||
writel(value, sdev->regs + reg_id);
|
||||
}
|
||||
|
||||
static inline
|
||||
u32 sdo_read(struct sdo_device *sdev, u32 reg_id)
|
||||
{
|
||||
return readl(sdev->regs + reg_id);
|
||||
}
|
||||
|
||||
static irqreturn_t sdo_irq_handler(int irq, void *dev_data)
|
||||
{
|
||||
struct sdo_device *sdev = dev_data;
|
||||
|
||||
/* clear interrupt */
|
||||
sdo_write_mask(sdev, SDO_IRQ, ~0, SDO_VSYNC_IRQ_PEND);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void sdo_reg_debug(struct sdo_device *sdev)
|
||||
{
|
||||
#define DBGREG(reg_id) \
|
||||
dev_info(sdev->dev, #reg_id " = %08x\n", \
|
||||
sdo_read(sdev, reg_id))
|
||||
|
||||
DBGREG(SDO_CLKCON);
|
||||
DBGREG(SDO_CONFIG);
|
||||
DBGREG(SDO_VBI);
|
||||
DBGREG(SDO_DAC);
|
||||
DBGREG(SDO_IRQ);
|
||||
DBGREG(SDO_IRQMASK);
|
||||
DBGREG(SDO_VERSION);
|
||||
}
|
||||
|
||||
static const struct sdo_format sdo_format[] = {
|
||||
{ V4L2_STD_PAL_N, .height = 576, .cookie = SDO_PAL_N },
|
||||
{ V4L2_STD_PAL_Nc, .height = 576, .cookie = SDO_PAL_NC },
|
||||
{ V4L2_STD_PAL_M, .height = 480, .cookie = SDO_PAL_M },
|
||||
{ V4L2_STD_PAL_60, .height = 480, .cookie = SDO_PAL_60 },
|
||||
{ V4L2_STD_NTSC_443, .height = 480, .cookie = SDO_NTSC_443 },
|
||||
{ V4L2_STD_PAL, .height = 576, .cookie = SDO_PAL_BGHID },
|
||||
{ V4L2_STD_NTSC_M, .height = 480, .cookie = SDO_NTSC_M },
|
||||
};
|
||||
|
||||
static const struct sdo_format *sdo_find_format(v4l2_std_id id)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < ARRAY_SIZE(sdo_format); ++i)
|
||||
if (sdo_format[i].id & id)
|
||||
return &sdo_format[i];
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int sdo_g_tvnorms_output(struct v4l2_subdev *sd, v4l2_std_id *std)
|
||||
{
|
||||
*std = V4L2_STD_NTSC_M | V4L2_STD_PAL_M | V4L2_STD_PAL |
|
||||
V4L2_STD_PAL_N | V4L2_STD_PAL_Nc |
|
||||
V4L2_STD_NTSC_443 | V4L2_STD_PAL_60;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdo_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
|
||||
{
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
const struct sdo_format *fmt;
|
||||
fmt = sdo_find_format(std);
|
||||
if (fmt == NULL)
|
||||
return -EINVAL;
|
||||
sdev->fmt = fmt;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdo_g_std_output(struct v4l2_subdev *sd, v4l2_std_id *std)
|
||||
{
|
||||
*std = sd_to_sdev(sd)->fmt->id;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdo_get_fmt(struct v4l2_subdev *sd,
|
||||
struct v4l2_subdev_pad_config *cfg,
|
||||
struct v4l2_subdev_format *format)
|
||||
{
|
||||
struct v4l2_mbus_framefmt *fmt = &format->format;
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
|
||||
if (!sdev->fmt)
|
||||
return -ENXIO;
|
||||
if (format->pad)
|
||||
return -EINVAL;
|
||||
/* all modes are 720 pixels wide */
|
||||
fmt->width = 720;
|
||||
fmt->height = sdev->fmt->height;
|
||||
fmt->code = MEDIA_BUS_FMT_FIXED;
|
||||
fmt->field = V4L2_FIELD_INTERLACED;
|
||||
fmt->colorspace = V4L2_COLORSPACE_JPEG;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdo_s_power(struct v4l2_subdev *sd, int on)
|
||||
{
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
struct device *dev = sdev->dev;
|
||||
int ret;
|
||||
|
||||
dev_info(dev, "sdo_s_power(%d)\n", on);
|
||||
|
||||
if (on)
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
else
|
||||
ret = pm_runtime_put_sync(dev);
|
||||
|
||||
/* only values < 0 indicate errors */
|
||||
return ret < 0 ? ret : 0;
|
||||
}
|
||||
|
||||
static int sdo_streamon(struct sdo_device *sdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* set proper clock for Timing Generator */
|
||||
sdev->vpll_rate = clk_get_rate(sdev->fout_vpll);
|
||||
ret = clk_set_rate(sdev->fout_vpll, 54000000);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "Failed to set vpll rate\n");
|
||||
return ret;
|
||||
}
|
||||
dev_info(sdev->dev, "fout_vpll.rate = %lu\n",
|
||||
clk_get_rate(sdev->fout_vpll));
|
||||
/* enable clock in SDO */
|
||||
sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_CLOCK_ON);
|
||||
ret = clk_prepare_enable(sdev->dacphy);
|
||||
if (ret < 0) {
|
||||
dev_err(sdev->dev, "clk_prepare_enable(dacphy) failed\n");
|
||||
goto fail;
|
||||
}
|
||||
/* enable DAC */
|
||||
sdo_write_mask(sdev, SDO_DAC, ~0, SDO_POWER_ON_DAC);
|
||||
sdo_reg_debug(sdev);
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
|
||||
clk_set_rate(sdev->fout_vpll, sdev->vpll_rate);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sdo_streamoff(struct sdo_device *sdev)
|
||||
{
|
||||
int tries;
|
||||
|
||||
sdo_write_mask(sdev, SDO_DAC, 0, SDO_POWER_ON_DAC);
|
||||
clk_disable_unprepare(sdev->dacphy);
|
||||
sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_CLOCK_ON);
|
||||
for (tries = 100; tries; --tries) {
|
||||
if (sdo_read(sdev, SDO_CLKCON) & SDO_TVOUT_CLOCK_READY)
|
||||
break;
|
||||
mdelay(1);
|
||||
}
|
||||
if (tries == 0)
|
||||
dev_err(sdev->dev, "failed to stop streaming\n");
|
||||
clk_set_rate(sdev->fout_vpll, sdev->vpll_rate);
|
||||
return tries ? 0 : -EIO;
|
||||
}
|
||||
|
||||
static int sdo_s_stream(struct v4l2_subdev *sd, int on)
|
||||
{
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
return on ? sdo_streamon(sdev) : sdo_streamoff(sdev);
|
||||
}
|
||||
|
||||
static const struct v4l2_subdev_core_ops sdo_sd_core_ops = {
|
||||
.s_power = sdo_s_power,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_video_ops sdo_sd_video_ops = {
|
||||
.s_std_output = sdo_s_std_output,
|
||||
.g_std_output = sdo_g_std_output,
|
||||
.g_tvnorms_output = sdo_g_tvnorms_output,
|
||||
.s_stream = sdo_s_stream,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_pad_ops sdo_sd_pad_ops = {
|
||||
.get_fmt = sdo_get_fmt,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_ops sdo_sd_ops = {
|
||||
.core = &sdo_sd_core_ops,
|
||||
.video = &sdo_sd_video_ops,
|
||||
.pad = &sdo_sd_pad_ops,
|
||||
};
|
||||
|
||||
static int sdo_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct v4l2_subdev *sd = dev_get_drvdata(dev);
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
|
||||
dev_info(dev, "suspend\n");
|
||||
regulator_disable(sdev->vdet);
|
||||
regulator_disable(sdev->vdac);
|
||||
clk_disable_unprepare(sdev->sclk_dac);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdo_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct v4l2_subdev *sd = dev_get_drvdata(dev);
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
int ret;
|
||||
|
||||
dev_info(dev, "resume\n");
|
||||
|
||||
ret = clk_prepare_enable(sdev->sclk_dac);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = regulator_enable(sdev->vdac);
|
||||
if (ret < 0)
|
||||
goto dac_clk_dis;
|
||||
|
||||
ret = regulator_enable(sdev->vdet);
|
||||
if (ret < 0)
|
||||
goto vdac_r_dis;
|
||||
|
||||
/* software reset */
|
||||
sdo_write_mask(sdev, SDO_CLKCON, ~0, SDO_TVOUT_SW_RESET);
|
||||
mdelay(10);
|
||||
sdo_write_mask(sdev, SDO_CLKCON, 0, SDO_TVOUT_SW_RESET);
|
||||
|
||||
/* setting TV mode */
|
||||
sdo_write_mask(sdev, SDO_CONFIG, sdev->fmt->cookie, SDO_STANDARD_MASK);
|
||||
/* XXX: forcing interlaced mode using undocumented bit */
|
||||
sdo_write_mask(sdev, SDO_CONFIG, 0, SDO_PROGRESSIVE);
|
||||
/* turn all VBI off */
|
||||
sdo_write_mask(sdev, SDO_VBI, 0, SDO_CVBS_WSS_INS |
|
||||
SDO_CVBS_CLOSED_CAPTION_MASK);
|
||||
/* turn all post processing off */
|
||||
sdo_write_mask(sdev, SDO_CCCON, ~0, SDO_COMPENSATION_BHS_ADJ_OFF |
|
||||
SDO_COMPENSATION_CVBS_COMP_OFF);
|
||||
sdo_reg_debug(sdev);
|
||||
return 0;
|
||||
|
||||
vdac_r_dis:
|
||||
regulator_disable(sdev->vdac);
|
||||
dac_clk_dis:
|
||||
clk_disable_unprepare(sdev->sclk_dac);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops sdo_pm_ops = {
|
||||
.runtime_suspend = sdo_runtime_suspend,
|
||||
.runtime_resume = sdo_runtime_resume,
|
||||
};
|
||||
|
||||
static int sdo_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sdo_device *sdev;
|
||||
struct resource *res;
|
||||
int ret = 0;
|
||||
struct clk *sclk_vpll;
|
||||
|
||||
dev_info(dev, "probe start\n");
|
||||
sdev = devm_kzalloc(&pdev->dev, sizeof(*sdev), GFP_KERNEL);
|
||||
if (!sdev) {
|
||||
dev_err(dev, "not enough memory.\n");
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
sdev->dev = dev;
|
||||
|
||||
/* mapping registers */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(dev, "get memory resource failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
sdev->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
|
||||
if (sdev->regs == NULL) {
|
||||
dev_err(dev, "register mapping failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* acquiring interrupt */
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (res == NULL) {
|
||||
dev_err(dev, "get interrupt resource failed.\n");
|
||||
ret = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
ret = devm_request_irq(&pdev->dev, res->start, sdo_irq_handler, 0,
|
||||
"s5p-sdo", sdev);
|
||||
if (ret) {
|
||||
dev_err(dev, "request interrupt failed.\n");
|
||||
goto fail;
|
||||
}
|
||||
sdev->irq = res->start;
|
||||
|
||||
/* acquire clocks */
|
||||
sdev->sclk_dac = clk_get(dev, "sclk_dac");
|
||||
if (IS_ERR(sdev->sclk_dac)) {
|
||||
dev_err(dev, "failed to get clock 'sclk_dac'\n");
|
||||
ret = PTR_ERR(sdev->sclk_dac);
|
||||
goto fail;
|
||||
}
|
||||
sdev->dac = clk_get(dev, "dac");
|
||||
if (IS_ERR(sdev->dac)) {
|
||||
dev_err(dev, "failed to get clock 'dac'\n");
|
||||
ret = PTR_ERR(sdev->dac);
|
||||
goto fail_sclk_dac;
|
||||
}
|
||||
sdev->dacphy = clk_get(dev, "dacphy");
|
||||
if (IS_ERR(sdev->dacphy)) {
|
||||
dev_err(dev, "failed to get clock 'dacphy'\n");
|
||||
ret = PTR_ERR(sdev->dacphy);
|
||||
goto fail_dac;
|
||||
}
|
||||
sclk_vpll = clk_get(dev, "sclk_vpll");
|
||||
if (IS_ERR(sclk_vpll)) {
|
||||
dev_err(dev, "failed to get clock 'sclk_vpll'\n");
|
||||
ret = PTR_ERR(sclk_vpll);
|
||||
goto fail_dacphy;
|
||||
}
|
||||
clk_set_parent(sdev->sclk_dac, sclk_vpll);
|
||||
clk_put(sclk_vpll);
|
||||
sdev->fout_vpll = clk_get(dev, "fout_vpll");
|
||||
if (IS_ERR(sdev->fout_vpll)) {
|
||||
dev_err(dev, "failed to get clock 'fout_vpll'\n");
|
||||
ret = PTR_ERR(sdev->fout_vpll);
|
||||
goto fail_dacphy;
|
||||
}
|
||||
dev_info(dev, "fout_vpll.rate = %lu\n", clk_get_rate(sclk_vpll));
|
||||
|
||||
/* acquire regulator */
|
||||
sdev->vdac = devm_regulator_get(dev, "vdd33a_dac");
|
||||
if (IS_ERR(sdev->vdac)) {
|
||||
dev_err(dev, "failed to get regulator 'vdac'\n");
|
||||
ret = PTR_ERR(sdev->vdac);
|
||||
goto fail_fout_vpll;
|
||||
}
|
||||
sdev->vdet = devm_regulator_get(dev, "vdet");
|
||||
if (IS_ERR(sdev->vdet)) {
|
||||
dev_err(dev, "failed to get regulator 'vdet'\n");
|
||||
ret = PTR_ERR(sdev->vdet);
|
||||
goto fail_fout_vpll;
|
||||
}
|
||||
|
||||
/* enable gate for dac clock, because mixer uses it */
|
||||
ret = clk_prepare_enable(sdev->dac);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "clk_prepare_enable(dac) failed\n");
|
||||
goto fail_fout_vpll;
|
||||
}
|
||||
|
||||
/* configure power management */
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
/* configuration of interface subdevice */
|
||||
v4l2_subdev_init(&sdev->sd, &sdo_sd_ops);
|
||||
sdev->sd.owner = THIS_MODULE;
|
||||
strlcpy(sdev->sd.name, "s5p-sdo", sizeof(sdev->sd.name));
|
||||
|
||||
/* set default format */
|
||||
sdev->fmt = sdo_find_format(SDO_DEFAULT_STD);
|
||||
BUG_ON(sdev->fmt == NULL);
|
||||
|
||||
/* keeping subdev in device's private for use by other drivers */
|
||||
dev_set_drvdata(dev, &sdev->sd);
|
||||
|
||||
dev_info(dev, "probe succeeded\n");
|
||||
return 0;
|
||||
|
||||
fail_fout_vpll:
|
||||
clk_put(sdev->fout_vpll);
|
||||
fail_dacphy:
|
||||
clk_put(sdev->dacphy);
|
||||
fail_dac:
|
||||
clk_put(sdev->dac);
|
||||
fail_sclk_dac:
|
||||
clk_put(sdev->sclk_dac);
|
||||
fail:
|
||||
dev_info(dev, "probe failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sdo_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct v4l2_subdev *sd = dev_get_drvdata(&pdev->dev);
|
||||
struct sdo_device *sdev = sd_to_sdev(sd);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_disable_unprepare(sdev->dac);
|
||||
clk_put(sdev->fout_vpll);
|
||||
clk_put(sdev->dacphy);
|
||||
clk_put(sdev->dac);
|
||||
clk_put(sdev->sclk_dac);
|
||||
|
||||
dev_info(&pdev->dev, "remove successful\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver sdo_driver __refdata = {
|
||||
.probe = sdo_probe,
|
||||
.remove = sdo_remove,
|
||||
.driver = {
|
||||
.name = "s5p-sdo",
|
||||
.pm = &sdo_pm_ops,
|
||||
}
|
||||
};
|
||||
|
||||
module_platform_driver(sdo_driver);
|
||||
|
|
@ -1,407 +0,0 @@
|
|||
/*
|
||||
* Samsung MHL interface driver
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics Co.Ltd
|
||||
* Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/freezer.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/platform_data/media/sii9234.h>
|
||||
#include <media/v4l2-subdev.h>
|
||||
|
||||
MODULE_AUTHOR("Tomasz Stanislawski <t.stanislaws@samsung.com>");
|
||||
MODULE_DESCRIPTION("Samsung MHL interface driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
struct sii9234_context {
|
||||
struct i2c_client *client;
|
||||
struct regulator *power;
|
||||
int gpio_n_reset;
|
||||
struct v4l2_subdev sd;
|
||||
};
|
||||
|
||||
static inline struct sii9234_context *sd_to_context(struct v4l2_subdev *sd)
|
||||
{
|
||||
return container_of(sd, struct sii9234_context, sd);
|
||||
}
|
||||
|
||||
static inline int sii9234_readb(struct i2c_client *client, int addr)
|
||||
{
|
||||
return i2c_smbus_read_byte_data(client, addr);
|
||||
}
|
||||
|
||||
static inline int sii9234_writeb(struct i2c_client *client, int addr, int value)
|
||||
{
|
||||
return i2c_smbus_write_byte_data(client, addr, value);
|
||||
}
|
||||
|
||||
static inline int sii9234_writeb_mask(struct i2c_client *client, int addr,
|
||||
int value, int mask)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = i2c_smbus_read_byte_data(client, addr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = (ret & ~mask) | (value & mask);
|
||||
return i2c_smbus_write_byte_data(client, addr, ret);
|
||||
}
|
||||
|
||||
static inline int sii9234_readb_idx(struct i2c_client *client, int addr)
|
||||
{
|
||||
int ret;
|
||||
ret = i2c_smbus_write_byte_data(client, 0xbc, addr >> 8);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = i2c_smbus_write_byte_data(client, 0xbd, addr & 0xff);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return i2c_smbus_read_byte_data(client, 0xbe);
|
||||
}
|
||||
|
||||
static inline int sii9234_writeb_idx(struct i2c_client *client, int addr,
|
||||
int value)
|
||||
{
|
||||
int ret;
|
||||
ret = i2c_smbus_write_byte_data(client, 0xbc, addr >> 8);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = i2c_smbus_write_byte_data(client, 0xbd, addr & 0xff);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = i2c_smbus_write_byte_data(client, 0xbe, value);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int sii9234_writeb_idx_mask(struct i2c_client *client, int addr,
|
||||
int value, int mask)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = sii9234_readb_idx(client, addr);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
ret = (ret & ~mask) | (value & mask);
|
||||
return sii9234_writeb_idx(client, addr, ret);
|
||||
}
|
||||
|
||||
static int sii9234_reset(struct sii9234_context *ctx)
|
||||
{
|
||||
struct i2c_client *client = ctx->client;
|
||||
struct device *dev = &client->dev;
|
||||
int ret, tries;
|
||||
|
||||
gpio_direction_output(ctx->gpio_n_reset, 1);
|
||||
mdelay(1);
|
||||
gpio_direction_output(ctx->gpio_n_reset, 0);
|
||||
mdelay(1);
|
||||
gpio_direction_output(ctx->gpio_n_reset, 1);
|
||||
mdelay(1);
|
||||
|
||||
/* going to TTPI mode */
|
||||
ret = sii9234_writeb(client, 0xc7, 0);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to set TTPI mode\n");
|
||||
return ret;
|
||||
}
|
||||
for (tries = 0; tries < 100 ; ++tries) {
|
||||
ret = sii9234_readb(client, 0x1b);
|
||||
if (ret > 0)
|
||||
break;
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to reset device\n");
|
||||
return -EIO;
|
||||
}
|
||||
mdelay(1);
|
||||
}
|
||||
if (tries == 100) {
|
||||
dev_err(dev, "maximal number of tries reached\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sii9234_verify_version(struct i2c_client *client)
|
||||
{
|
||||
struct device *dev = &client->dev;
|
||||
int family, rev, tpi_rev, dev_id, sub_id, hdcp, id;
|
||||
|
||||
family = sii9234_readb(client, 0x1b);
|
||||
rev = sii9234_readb(client, 0x1c) & 0x0f;
|
||||
tpi_rev = sii9234_readb(client, 0x1d) & 0x7f;
|
||||
dev_id = sii9234_readb_idx(client, 0x0103);
|
||||
sub_id = sii9234_readb_idx(client, 0x0102);
|
||||
hdcp = sii9234_readb(client, 0x30);
|
||||
|
||||
if (family < 0 || rev < 0 || tpi_rev < 0 || dev_id < 0 ||
|
||||
sub_id < 0 || hdcp < 0) {
|
||||
dev_err(dev, "failed to read chip's version\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
id = (dev_id << 8) | sub_id;
|
||||
|
||||
dev_info(dev, "chip: SiL%02x family: %02x, rev: %02x\n",
|
||||
id, family, rev);
|
||||
dev_info(dev, "tpi_rev:%02x, hdcp: %02x\n", tpi_rev, hdcp);
|
||||
if (id != 0x9234) {
|
||||
dev_err(dev, "not supported chip\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u8 data[][3] = {
|
||||
/* setup from driver created by doonsoo45.kim */
|
||||
{ 0x01, 0x05, 0x04 }, /* Enable Auto soft reset on SCDT = 0 */
|
||||
{ 0x01, 0x08, 0x35 }, /* Power Up TMDS Tx Core */
|
||||
{ 0x01, 0x0d, 0x1c }, /* HDMI Transcode mode enable */
|
||||
{ 0x01, 0x2b, 0x01 }, /* Enable HDCP Compliance workaround */
|
||||
{ 0x01, 0x79, 0x40 }, /* daniel test...MHL_INT */
|
||||
{ 0x01, 0x80, 0x34 }, /* Enable Rx PLL Clock Value */
|
||||
{ 0x01, 0x90, 0x27 }, /* Enable CBUS discovery */
|
||||
{ 0x01, 0x91, 0xe5 }, /* Skip RGND detection */
|
||||
{ 0x01, 0x92, 0x46 }, /* Force MHD mode */
|
||||
{ 0x01, 0x93, 0xdc }, /* Disable CBUS pull-up during RGND measurement */
|
||||
{ 0x01, 0x94, 0x66 }, /* 1.8V CBUS VTH & GND threshold */
|
||||
{ 0x01, 0x95, 0x31 }, /* RGND block & single discovery attempt */
|
||||
{ 0x01, 0x96, 0x22 }, /* use 1K and 2K setting */
|
||||
{ 0x01, 0xa0, 0x10 }, /* SIMG: Term mode */
|
||||
{ 0x01, 0xa1, 0xfc }, /* Disable internal Mobile HD driver */
|
||||
{ 0x01, 0xa3, 0xfa }, /* SIMG: Output Swing default EB, 3x Clk Mult */
|
||||
{ 0x01, 0xa5, 0x80 }, /* SIMG: RGND Hysterisis, 3x mode for Beast */
|
||||
{ 0x01, 0xa6, 0x0c }, /* SIMG: Swing Offset */
|
||||
{ 0x02, 0x3d, 0x3f }, /* Power up CVCC 1.2V core */
|
||||
{ 0x03, 0x00, 0x00 }, /* SIMG: correcting HW default */
|
||||
{ 0x03, 0x11, 0x01 }, /* Enable TxPLL Clock */
|
||||
{ 0x03, 0x12, 0x15 }, /* Enable Tx Clock Path & Equalizer */
|
||||
{ 0x03, 0x13, 0x60 }, /* SIMG: Set termination value */
|
||||
{ 0x03, 0x14, 0xf0 }, /* SIMG: Change CKDT level */
|
||||
{ 0x03, 0x17, 0x07 }, /* SIMG: PLL Calrefsel */
|
||||
{ 0x03, 0x1a, 0x20 }, /* VCO Cal */
|
||||
{ 0x03, 0x22, 0xe0 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x23, 0xc0 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x24, 0xa0 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x25, 0x80 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x26, 0x60 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x27, 0x40 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x28, 0x20 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x29, 0x00 }, /* SIMG: Auto EQ */
|
||||
{ 0x03, 0x31, 0x0b }, /* SIMG: Rx PLL BW value from I2C BW ~ 4MHz */
|
||||
{ 0x03, 0x45, 0x06 }, /* SIMG: DPLL Mode */
|
||||
{ 0x03, 0x4b, 0x06 }, /* SIMG: Correcting HW default */
|
||||
{ 0x03, 0x4c, 0xa0 }, /* Manual zone control */
|
||||
{ 0x03, 0x4d, 0x02 }, /* SIMG: PLL Mode Value (order is important) */
|
||||
};
|
||||
|
||||
static int sii9234_set_internal(struct sii9234_context *ctx)
|
||||
{
|
||||
struct i2c_client *client = ctx->client;
|
||||
int i, ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(data); ++i) {
|
||||
int addr = (data[i][0] << 8) | data[i][1];
|
||||
ret = sii9234_writeb_idx(client, addr, data[i][2]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sii9234_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct v4l2_subdev *sd = dev_get_drvdata(dev);
|
||||
struct sii9234_context *ctx = sd_to_context(sd);
|
||||
struct i2c_client *client = ctx->client;
|
||||
|
||||
dev_info(dev, "suspend start\n");
|
||||
|
||||
sii9234_writeb_mask(client, 0x1e, 3, 3);
|
||||
regulator_disable(ctx->power);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sii9234_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct v4l2_subdev *sd = dev_get_drvdata(dev);
|
||||
struct sii9234_context *ctx = sd_to_context(sd);
|
||||
struct i2c_client *client = ctx->client;
|
||||
int ret;
|
||||
|
||||
dev_info(dev, "resume start\n");
|
||||
ret = regulator_enable(ctx->power);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = sii9234_reset(ctx);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
/* enable tpi */
|
||||
ret = sii9234_writeb_mask(client, 0x1e, 1, 0);
|
||||
if (ret < 0)
|
||||
goto fail;
|
||||
ret = sii9234_set_internal(ctx);
|
||||
if (ret < 0)
|
||||
goto fail;
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
dev_err(dev, "failed to resume\n");
|
||||
regulator_disable(ctx->power);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops sii9234_pm_ops = {
|
||||
.runtime_suspend = sii9234_runtime_suspend,
|
||||
.runtime_resume = sii9234_runtime_resume,
|
||||
};
|
||||
|
||||
static int sii9234_s_power(struct v4l2_subdev *sd, int on)
|
||||
{
|
||||
struct sii9234_context *ctx = sd_to_context(sd);
|
||||
int ret;
|
||||
|
||||
if (on)
|
||||
ret = pm_runtime_get_sync(&ctx->client->dev);
|
||||
else
|
||||
ret = pm_runtime_put(&ctx->client->dev);
|
||||
/* only values < 0 indicate errors */
|
||||
return ret < 0 ? ret : 0;
|
||||
}
|
||||
|
||||
static int sii9234_s_stream(struct v4l2_subdev *sd, int enable)
|
||||
{
|
||||
struct sii9234_context *ctx = sd_to_context(sd);
|
||||
|
||||
/* (dis/en)able TDMS output */
|
||||
sii9234_writeb_mask(ctx->client, 0x1a, enable ? 0 : ~0 , 1 << 4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct v4l2_subdev_core_ops sii9234_core_ops = {
|
||||
.s_power = sii9234_s_power,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_video_ops sii9234_video_ops = {
|
||||
.s_stream = sii9234_s_stream,
|
||||
};
|
||||
|
||||
static const struct v4l2_subdev_ops sii9234_ops = {
|
||||
.core = &sii9234_core_ops,
|
||||
.video = &sii9234_video_ops,
|
||||
};
|
||||
|
||||
static int sii9234_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct device *dev = &client->dev;
|
||||
struct sii9234_platform_data *pdata = dev->platform_data;
|
||||
struct sii9234_context *ctx;
|
||||
int ret;
|
||||
|
||||
ctx = devm_kzalloc(&client->dev, sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx) {
|
||||
dev_err(dev, "out of memory\n");
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
ctx->client = client;
|
||||
|
||||
ctx->power = devm_regulator_get(dev, "hdmi-en");
|
||||
if (IS_ERR(ctx->power)) {
|
||||
dev_err(dev, "failed to acquire regulator hdmi-en\n");
|
||||
return PTR_ERR(ctx->power);
|
||||
}
|
||||
|
||||
ctx->gpio_n_reset = pdata->gpio_n_reset;
|
||||
ret = devm_gpio_request(dev, ctx->gpio_n_reset, "MHL_RST");
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to acquire MHL_RST gpio\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
v4l2_i2c_subdev_init(&ctx->sd, client, &sii9234_ops);
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
/* enable device */
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
if (ret)
|
||||
goto fail_pm;
|
||||
|
||||
/* verify chip version */
|
||||
ret = sii9234_verify_version(client);
|
||||
if (ret)
|
||||
goto fail_pm_get;
|
||||
|
||||
/* stop processing */
|
||||
pm_runtime_put(dev);
|
||||
|
||||
dev_info(dev, "probe successful\n");
|
||||
|
||||
return 0;
|
||||
|
||||
fail_pm_get:
|
||||
pm_runtime_put_sync(dev);
|
||||
|
||||
fail_pm:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
fail:
|
||||
dev_err(dev, "probe failed\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sii9234_remove(struct i2c_client *client)
|
||||
{
|
||||
struct device *dev = &client->dev;
|
||||
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
dev_info(dev, "remove successful\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct i2c_device_id sii9234_id[] = {
|
||||
{ "SII9234", 0 },
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(i2c, sii9234_id);
|
||||
static struct i2c_driver sii9234_driver = {
|
||||
.driver = {
|
||||
.name = "sii9234",
|
||||
.pm = &sii9234_pm_ops,
|
||||
},
|
||||
.probe = sii9234_probe,
|
||||
.remove = sii9234_remove,
|
||||
.id_table = sii9234_id,
|
||||
};
|
||||
|
||||
module_i2c_driver(sii9234_driver);
|
||||
Loading…
Reference in New Issue