clk: uniphier: add CPU-gear change (cpufreq) support
Core support code for CPU frequency changes, which will be used by the generic cpufreq driver. The register view is different from the generic clk-mux; it has a separate status register, and an update bit to load the register setting. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -1,8 +1,11 @@
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obj-y += clk-uniphier-core.o
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obj-y += clk-uniphier-cpugear.o
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obj-y += clk-uniphier-fixed-factor.o
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obj-y += clk-uniphier-fixed-rate.o
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obj-y += clk-uniphier-gate.o
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obj-y += clk-uniphier-mux.o
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obj-y += clk-uniphier-sys.o
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obj-y += clk-uniphier-mio.o
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obj-y += clk-uniphier-peri.o
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@ -27,6 +27,9 @@ static struct clk_hw *uniphier_clk_register(struct device *dev,
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const struct uniphier_clk_data *data)
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{
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switch (data->type) {
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case UNIPHIER_CLK_TYPE_CPUGEAR:
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return uniphier_clk_register_cpugear(dev, regmap, data->name,
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&data->data.cpugear);
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case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
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return uniphier_clk_register_fixed_factor(dev, data->name,
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&data->data.factor);
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@ -0,0 +1,115 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include "clk-uniphier.h"
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#define UNIPHIER_CLK_CPUGEAR_STAT 0 /* status */
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#define UNIPHIER_CLK_CPUGEAR_SET 4 /* set */
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#define UNIPHIER_CLK_CPUGEAR_UPD 8 /* update */
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#define UNIPHIER_CLK_CPUGEAR_UPD_BIT BIT(0)
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struct uniphier_clk_cpugear {
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struct clk_hw hw;
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struct regmap *regmap;
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unsigned int regbase;
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unsigned int mask;
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};
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#define to_uniphier_clk_cpugear(_hw) \
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container_of(_hw, struct uniphier_clk_cpugear, hw)
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static int uniphier_clk_cpugear_set_parent(struct clk_hw *hw, u8 index)
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{
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struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
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int ret;
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unsigned int val;
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ret = regmap_write_bits(gear->regmap,
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gear->regbase + UNIPHIER_CLK_CPUGEAR_SET,
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gear->mask, index);
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if (ret)
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return ret;
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ret = regmap_write_bits(gear->regmap,
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gear->regbase + UNIPHIER_CLK_CPUGEAR_SET,
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UNIPHIER_CLK_CPUGEAR_UPD_BIT,
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UNIPHIER_CLK_CPUGEAR_UPD_BIT);
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if (ret)
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return ret;
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return regmap_read_poll_timeout(gear->regmap,
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gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
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val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT),
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0, 1);
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}
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static u8 uniphier_clk_cpugear_get_parent(struct clk_hw *hw)
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{
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struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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int ret;
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unsigned int val;
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ret = regmap_read(gear->regmap,
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gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val);
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if (ret)
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return ret;
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val &= gear->mask;
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return val < num_parents ? val : -EINVAL;
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}
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static const struct clk_ops uniphier_clk_cpugear_ops = {
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.determine_rate = __clk_mux_determine_rate,
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.set_parent = uniphier_clk_cpugear_set_parent,
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.get_parent = uniphier_clk_cpugear_get_parent,
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};
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struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
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struct regmap *regmap,
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const char *name,
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const struct uniphier_clk_cpugear_data *data)
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{
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struct uniphier_clk_cpugear *gear;
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struct clk_init_data init;
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int ret;
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gear = devm_kzalloc(dev, sizeof(*gear), GFP_KERNEL);
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if (!gear)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &uniphier_clk_cpugear_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = data->parent_names;
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init.num_parents = data->num_parents,
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gear->regmap = regmap;
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gear->regbase = data->regbase;
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gear->mask = data->mask;
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gear->hw.init = &init;
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ret = devm_clk_hw_register(dev, &gear->hw);
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if (ret)
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return ERR_PTR(ret);
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return &gear->hw;
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}
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@ -20,15 +20,24 @@ struct clk_hw;
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struct device;
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struct regmap;
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#define UNIPHIER_CLK_MUX_MAX_PARENTS 8
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#define UNIPHIER_CLK_CPUGEAR_MAX_PARENTS 16
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#define UNIPHIER_CLK_MUX_MAX_PARENTS 8
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enum uniphier_clk_type {
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UNIPHIER_CLK_TYPE_CPUGEAR,
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UNIPHIER_CLK_TYPE_FIXED_FACTOR,
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UNIPHIER_CLK_TYPE_FIXED_RATE,
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UNIPHIER_CLK_TYPE_GATE,
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UNIPHIER_CLK_TYPE_MUX,
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};
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struct uniphier_clk_cpugear_data {
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const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS];
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unsigned int num_parents;
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unsigned int regbase;
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unsigned int mask;
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};
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struct uniphier_clk_fixed_factor_data {
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const char *parent_name;
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unsigned int mult;
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@ -58,6 +67,7 @@ struct uniphier_clk_data {
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enum uniphier_clk_type type;
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int idx;
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union {
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struct uniphier_clk_cpugear_data cpugear;
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struct uniphier_clk_fixed_factor_data factor;
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struct uniphier_clk_fixed_rate_data rate;
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struct uniphier_clk_gate_data gate;
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}, \
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}
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struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
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struct regmap *regmap,
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const char *name,
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const struct uniphier_clk_cpugear_data *data);
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struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
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const char *name,
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const struct uniphier_clk_fixed_factor_data *data);
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