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Merge branch 'remotes/lorenzo/pci/mediatek' 

- Fix mediatek MMIO size computation to enable full size of available
    MMIO space (Honghui Zhang)

  - Fix mediatek DMA window size computation to allow endpoint DMA access
    to full DRAM address range (Honghui Zhang)

* remotes/lorenzo/pci/mediatek:
  PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
  PCI: mediatek: Fix memory mapped IO range size computation
This commit is contained in:
Bjorn Helgaas 2019-03-06 15:30:23 -06:00
parent a8e04a7a7f cbe3a7728c
commit d00aaa88c3
1 changed files with 9 additions and 4 deletions
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13
drivers/pci/controller/pcie-mediatek.c
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@ -90,6 +90,12 @@
#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
#define PCIE_AXI_WINDOW0 0x448 #define PCIE_AXI_WINDOW0 0x448
#define WIN_ENABLE BIT(7) #define WIN_ENABLE BIT(7)
/*
* Define PCIe to AHB window size as 2^33 to support max 8GB address space
* translate, support least 4GB DRAM size access from EP DMA(physical DRAM
* start from 0x40000000).
*/
#define PCIE2AHB_SIZE 0x21
/* PCIe V2 configuration transaction header */ /* PCIe V2 configuration transaction header */
#define PCIE_CFG_HEADER0 0x460 #define PCIE_CFG_HEADER0 0x460
@ -654,7 +660,6 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
struct resource *mem = &pcie->mem; struct resource *mem = &pcie->mem;
const struct mtk_pcie_soc *soc = port->pcie->soc; const struct mtk_pcie_soc *soc = port->pcie->soc;
u32 val; u32 val;
size_t size;
int err; int err;
/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
@ -706,15 +711,15 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
mtk_pcie_enable_msi(port); mtk_pcie_enable_msi(port);
/* Set AHB to PCIe translation windows */ /* Set AHB to PCIe translation windows */
size = mem->end - mem->start; val = lower_32_bits(mem->start) |
val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size)); AHB2PCIE_SIZE(fls(resource_size(mem)));
writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
val = upper_32_bits(mem->start); val = upper_32_bits(mem->start);
writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
/* Set PCIe to AXI translation memory space.*/ /* Set PCIe to AXI translation memory space.*/
val = fls(0xffffffff) | WIN_ENABLE; val = PCIE2AHB_SIZE | WIN_ENABLE;
writel(val, port->base + PCIE_AXI_WINDOW0); writel(val, port->base + PCIE_AXI_WINDOW0);
return 0; return 0;