[Blackfin] arch: hook up set_irq_wake in Blackfin's irq code
- Add support for irq_wake on system and gpio interrupts - Remove outdated kernel options - Add option to select default PM mode - Fix various places where SIC_IWRx was only handled partially Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Michael Hennerich
Bryan Wu
parent
2c4f829b0c
commit
cfefe3c683
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@ -904,29 +904,38 @@ config ARCH_SUSPEND_POSSIBLE
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depends on !SMP
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choice
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prompt "Select PM Wakeup Event Source"
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default PM_WAKEUP_GPIO_BY_SIC_IWR
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prompt "Default Power Saving Mode"
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depends on PM
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default PM_BFIN_SLEEP_DEEPER
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config PM_BFIN_SLEEP_DEEPER
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bool "Sleep Deeper"
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help
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If you have a GPIO already configured as input with the corresponding PORTx_MASK
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bit set - "Specify Wakeup Event by SIC_IWR value"
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config PM_WAKEUP_GPIO_BY_SIC_IWR
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bool "Specify Wakeup Event by SIC_IWR value"
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config PM_WAKEUP_BY_GPIO
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bool "Cause Wakeup Event by GPIO"
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config PM_WAKEUP_GPIO_API
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bool "Configure Wakeup Event by PM GPIO API"
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Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
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power dissipation by disabling the clock to the processor core (CCLK).
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Furthermore, Standby sets the internal power supply voltage (VDDINT)
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to 0.85 V to provide the greatest power savings, while preserving the
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processor state.
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The PLL and system clock (SCLK) continue to operate at a very low
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frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
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the SDRAM is put into Self Refresh Mode. Typically an external event
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such as GPIO interrupt or RTC activity wakes up the processor.
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Various Peripherals such as UART, SPORT, PPI may not function as
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normal during Sleep Deeper, due to the reduced SCLK frequency.
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When in the sleep mode, system DMA access to L1 memory is not supported.
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config PM_BFIN_SLEEP
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bool "Sleep"
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help
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Sleep Mode (High Power Savings) - The sleep mode reduces power
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dissipation by disabling the clock to the processor core (CCLK).
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The PLL and system clock (SCLK), however, continue to operate in
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this mode. Typically an external event or RTC activity will wake
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up the processor. When in the sleep mode,
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system DMA access to L1 memory is not supported.
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endchoice
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config PM_WAKEUP_SIC_IWR
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hex "Wakeup Events (SIC_IWR)"
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depends on PM_WAKEUP_GPIO_BY_SIC_IWR
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default 0x8 if (BF537 || BF536 || BF534)
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default 0x80 if (BF533 || BF532 || BF531)
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default 0x80 if (BF54x)
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default 0x80 if (BF52x)
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config PM_WAKEUP_BY_GPIO
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bool "Cause Wakeup Event by GPIO"
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config PM_WAKEUP_GPIO_NUMBER
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int "Wakeup GPIO number"
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@ -186,7 +186,7 @@ static struct str_ident {
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char name[RESOURCE_LABEL_SIZE];
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} str_ident[MAX_RESOURCES];
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#ifdef CONFIG_PM
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#if defined(CONFIG_PM) && !defined(CONFIG_BF54x)
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static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
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static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
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static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
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@ -696,9 +696,8 @@ static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
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return 0;
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}
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u32 gpio_pm_setup(void)
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u32 bfin_pm_setup(void)
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{
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u32 sic_iwr = 0;
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u16 bank, mask, i, gpio;
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for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
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@ -723,7 +722,8 @@ u32 gpio_pm_setup(void)
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gpio = i;
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while (mask) {
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if (mask & 1) {
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if ((mask & 1) && (wakeup_flags_map[gpio] !=
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PM_WAKE_IGNORE)) {
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reserved_gpio_map[gpio_bank(gpio)] |=
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gpio_bit(gpio);
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bfin_gpio_wakeup_type(gpio,
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@ -734,21 +734,17 @@ u32 gpio_pm_setup(void)
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mask >>= 1;
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}
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sic_iwr |= 1 <<
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(sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
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bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
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gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
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}
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}
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AWA_DUMMY_READ(maskb_set);
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if (sic_iwr)
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return sic_iwr;
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else
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return IWR_ENABLE_ALL;
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return 0;
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}
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void gpio_pm_restore(void)
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void bfin_pm_restore(void)
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{
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u16 bank, mask, i;
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@ -768,7 +764,7 @@ void gpio_pm_restore(void)
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reserved_gpio_map[bank] =
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gpio_bank_saved[bank].reserved;
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bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
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}
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gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
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@ -191,6 +191,9 @@ ENTRY(_sleep_mode)
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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@ -237,6 +240,10 @@ ENTRY(_deep_sleep)
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CLI R4;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs;
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@ -261,6 +268,9 @@ ENTRY(_deep_sleep)
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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@ -286,7 +296,13 @@ ENTRY(_sleep_deeper)
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CLI R4;
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P3 = R0;
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P4 = R1;
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P5 = R2;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs; /* Set SDRAM Self Refresh */
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@ -327,6 +343,8 @@ ENTRY(_sleep_deeper)
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call _test_pll_locked;
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R0 = P3;
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R1 = P4;
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R3 = P5;
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call _set_sic_iwr; /* Set Awake from IDLE */
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P0.H = hi(PLL_CTL);
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@ -340,6 +358,9 @@ ENTRY(_sleep_deeper)
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr; /* Set Awake from IDLE PLL */
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P0.H = hi(VR_CTL);
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@ -417,14 +438,23 @@ ENTRY(_unset_dram_srfs)
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RTS;
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ENTRY(_set_sic_iwr)
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
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P0.H = hi(SIC_IWR0);
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P0.L = lo(SIC_IWR0);
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P1.H = hi(SIC_IWR1);
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P1.L = lo(SIC_IWR1);
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[P1] = R1;
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#if defined(CONFIG_BF54x)
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P1.H = hi(SIC_IWR2);
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P1.L = lo(SIC_IWR2);
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[P1] = R2;
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#endif
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#else
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P0.H = hi(SIC_IWR);
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P0.L = lo(SIC_IWR);
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#endif
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[P0] = R0;
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SSYNC;
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RTS;
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@ -1,5 +1,5 @@
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/*
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* File: arch/blackfin/mach-common/ints-priority-sc.c
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* File: arch/blackfin/mach-common/ints-priority.c
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* Based on:
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* Author:
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*
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@ -13,7 +13,7 @@
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* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
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* 2003 Metrowerks/Motorola
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* 2003 Bas Vermeulen <bas@buyways.nl>
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* Copyright 2004-2007 Analog Devices Inc.
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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@ -69,6 +69,10 @@ unsigned long irq_flags = 0x1f;
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/* The number of spurious interrupts */
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atomic_t num_spurious;
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#ifdef CONFIG_PM
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unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
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#endif
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struct ivgx {
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/* irq number for request_irq, available in mach-bf533/irq.h */
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unsigned int irqno;
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@ -178,6 +182,27 @@ static void bfin_internal_unmask_irq(unsigned int irq)
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SSYNC();
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}
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#ifdef CONFIG_PM
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int bfin_internal_set_wake(unsigned int irq, unsigned int state)
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{
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unsigned bank, bit;
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unsigned long flags;
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bank = (irq - (IRQ_CORETMR + 1)) / 32;
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bit = (irq - (IRQ_CORETMR + 1)) % 32;
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local_irq_save(flags);
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if (state)
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bfin_sic_iwr[bank] |= (1 << bit);
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else
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bfin_sic_iwr[bank] &= ~(1 << bit);
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local_irq_restore(flags);
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return 0;
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}
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#endif
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static struct irq_chip bfin_core_irqchip = {
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.ack = ack_noop,
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.mask = bfin_core_mask_irq,
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@ -188,6 +213,9 @@ static struct irq_chip bfin_internal_irqchip = {
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.ack = ack_noop,
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.mask = bfin_internal_mask_irq,
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.unmask = bfin_internal_unmask_irq,
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#ifdef CONFIG_PM
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.set_wake = bfin_internal_set_wake,
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#endif
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};
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#ifdef BF537_GENERIC_ERROR_INT_DEMUX
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@ -434,6 +462,20 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
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return 0;
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}
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#ifdef CONFIG_PM
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int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
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{
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unsigned gpio = irq_to_gpio(irq);
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if (state)
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gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
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else
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gpio_pm_wakeup_free(gpio);
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return 0;
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}
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#endif
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static struct irq_chip bfin_gpio_irqchip = {
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.ack = bfin_gpio_ack_irq,
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.mask = bfin_gpio_mask_irq,
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@ -441,7 +483,10 @@ static struct irq_chip bfin_gpio_irqchip = {
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.unmask = bfin_gpio_unmask_irq,
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.set_type = bfin_gpio_irq_type,
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.startup = bfin_gpio_irq_startup,
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.shutdown = bfin_gpio_irq_shutdown
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.shutdown = bfin_gpio_irq_shutdown,
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#ifdef CONFIG_PM
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.set_wake = bfin_gpio_set_wake,
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#endif
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};
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static void bfin_demux_gpio_irq(unsigned int inta_irq,
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@ -487,7 +532,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
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}
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if (search) {
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for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
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for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
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irq += i;
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mask = get_gpiop_data(i) &
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@ -763,6 +808,74 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
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return 0;
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}
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#ifdef CONFIG_PM
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u32 pint_saved_masks[NR_PINT_SYS_IRQS];
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u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
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int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
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{
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u32 pint_irq;
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u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
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u32 bank = PINT_2_BANK(pint_val);
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u32 pintbit = PINT_BIT(pint_val);
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switch (bank) {
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case 0:
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pint_irq = IRQ_PINT0;
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break;
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case 2:
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pint_irq = IRQ_PINT2;
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break;
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case 3:
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pint_irq = IRQ_PINT3;
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break;
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case 1:
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pint_irq = IRQ_PINT1;
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break;
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default:
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return -EINVAL;
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}
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bfin_internal_set_wake(pint_irq, state);
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if (state)
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pint_wakeup_masks[bank] |= pintbit;
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else
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pint_wakeup_masks[bank] &= ~pintbit;
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return 0;
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}
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u32 bfin_pm_setup(void)
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{
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u32 val, i;
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for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
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val = pint[i]->mask_clear;
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pint_saved_masks[i] = val;
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if (val ^ pint_wakeup_masks[i]) {
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pint[i]->mask_clear = val;
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pint[i]->mask_set = pint_wakeup_masks[i];
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}
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}
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return 0;
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}
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void bfin_pm_restore(void)
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{
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u32 i, val;
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for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
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val = pint_saved_masks[i];
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if (val ^ pint_wakeup_masks[i]) {
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pint[i]->mask_clear = pint[i]->mask_clear;
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pint[i]->mask_set = val;
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}
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}
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}
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#endif
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static struct irq_chip bfin_gpio_irqchip = {
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.ack = bfin_gpio_ack_irq,
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.mask = bfin_gpio_mask_irq,
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@ -770,7 +883,10 @@ static struct irq_chip bfin_gpio_irqchip = {
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.unmask = bfin_gpio_unmask_irq,
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.set_type = bfin_gpio_irq_type,
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.startup = bfin_gpio_irq_startup,
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.shutdown = bfin_gpio_irq_shutdown
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.shutdown = bfin_gpio_irq_shutdown,
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#ifdef CONFIG_PM
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.set_wake = bfin_gpio_set_wake,
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#endif
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};
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static void bfin_demux_gpio_irq(unsigned int inta_irq,
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@ -4,7 +4,7 @@
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* Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
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*
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* Created: 2001
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* Description: Power management for the bfin
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* Description: Blackfin power management
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*
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* Modified: Nicolas Pitre - PXA250 support
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* Copyright (c) 2002 Monta Vista Software, Inc.
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@ -12,7 +12,7 @@
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* Copyright (c) 2002 Monta Vista Software, Inc.
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* Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
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* Copyright 2004
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* Copyright 2004-2006 Analog Devices Inc.
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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@ -67,17 +67,20 @@ void bfin_pm_suspend_standby_enter(void)
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gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
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#endif
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#if defined(CONFIG_PM_WAKEUP_BY_GPIO) || defined(CONFIG_PM_WAKEUP_GPIO_API)
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{
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u32 flags;
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local_irq_save(flags);
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bfin_pm_setup();
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sleep_deeper(gpio_pm_setup()); /*Goto Sleep*/
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#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
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sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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#else
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sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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#endif
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gpio_pm_restore();
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bfin_pm_restore();
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
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#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
|
||||
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
|
||||
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
|
||||
# ifdef CONFIG_BF54x
|
||||
|
|
@ -88,21 +91,6 @@ void bfin_pm_suspend_standby_enter(void)
|
|||
#endif
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)
|
||||
sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
|
||||
# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
|
||||
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
|
||||
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
|
||||
# ifdef CONFIG_BF54x
|
||||
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
|
||||
# endif
|
||||
# else
|
||||
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
|
||||
# endif
|
||||
#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@ extern void program_IAR(void);
|
|||
extern void evt14_softirq(void);
|
||||
extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
|
||||
extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
|
||||
extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
|
||||
|
||||
extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
|
||||
extern char fixed_code_start;
|
||||
|
|
@ -121,6 +122,7 @@ extern unsigned long dpdt_swapcount_table[];
|
|||
|
||||
extern unsigned long table_start, table_end;
|
||||
|
||||
extern unsigned long bfin_sic_iwr[];
|
||||
extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
|
||||
extern struct file_operations dpmc_fops;
|
||||
extern char _start;
|
||||
|
|
|
|||
|
|
@ -53,10 +53,10 @@ unsigned long get_pll_status(void);
|
|||
void change_baud(int baud);
|
||||
void fullon_mode(void);
|
||||
void active_mode(void);
|
||||
void sleep_mode(u32 sic_iwr);
|
||||
void deep_sleep(u32 sic_iwr);
|
||||
void hibernate_mode(u32 sic_iwr);
|
||||
void sleep_deeper(u32 sic_iwr);
|
||||
void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
|
||||
void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
|
||||
void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
|
||||
void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
|
||||
void program_wdog_timer(unsigned long);
|
||||
void unmask_wdog_wakeup_evt(void);
|
||||
void clear_wdog_wakeup_evt(void);
|
||||
|
|
|
|||
|
|
@ -376,16 +376,19 @@ struct gpio_port_t {
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
unsigned int bfin_pm_setup(void);
|
||||
void bfin_pm_restore(void);
|
||||
|
||||
#ifndef CONFIG_BF54x
|
||||
#define PM_WAKE_RISING 0x1
|
||||
#define PM_WAKE_FALLING 0x2
|
||||
#define PM_WAKE_HIGH 0x4
|
||||
#define PM_WAKE_LOW 0x8
|
||||
#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
|
||||
#define PM_WAKE_IGNORE 0xF0
|
||||
|
||||
int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
|
||||
void gpio_pm_wakeup_free(unsigned gpio);
|
||||
unsigned int gpio_pm_setup(void);
|
||||
void gpio_pm_restore(void);
|
||||
|
||||
struct gpio_port_s {
|
||||
unsigned short data;
|
||||
|
|
@ -409,6 +412,7 @@ struct gpio_port_s {
|
|||
unsigned short fer;
|
||||
unsigned short reserved;
|
||||
};
|
||||
#endif /*CONFIG_BF54x*/
|
||||
#endif /*CONFIG_PM*/
|
||||
|
||||
/***********************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue