ARM: S5PV310: Add Timer support
This patch adds timer support for S5PV310. Until now, all S5P SoCs use CONFIG_ARCH_USES_GETTIMEOFFSET macro as a default configuration. Instead,S5PV310 implements clocksource and clock_event_device to support the high resolution timer and tickless system. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Changhwan Youn
Kukjin Kim
parent
84bbc16c1f
commit
cfca3a619b
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@ -0,0 +1,70 @@
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/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
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*
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* S5PV310 - pwm clock and timer support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_PWMCLK_H
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#define __ASM_ARCH_PWMCLK_H __FILE__
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/**
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* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
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* @tcfg: The timer TCFG1 register bits shifted down to 0.
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*
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* Return true if the given configuration from TCFG1 is a TCLK instead
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* any of the TDIV clocks.
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*/
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static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
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{
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return tcfg == S3C64XX_TCFG1_MUX_TCLK;
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}
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/**
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* tcfg_to_divisor() - convert tcfg1 setting to a divisor
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* @tcfg1: The tcfg1 setting, shifted down.
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*
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* Get the divisor value for the given tcfg1 setting. We assume the
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* caller has already checked to see if this is not a TCLK source.
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*/
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static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
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{
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return 1 << tcfg1;
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}
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/**
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* pwm_tdiv_has_div1() - does the tdiv setting have a /1
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*
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* Return true if we have a /1 in the tdiv setting.
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*/
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static inline unsigned int pwm_tdiv_has_div1(void)
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{
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return 1;
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}
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/**
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* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
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* @div: The divisor to calculate the bit information for.
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*
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* Turn a divisor into the necessary bit field for TCFG1.
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*/
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static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
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{
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return ilog2(div);
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}
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#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
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#endif /* __ASM_ARCH_PWMCLK_H */
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@ -0,0 +1,25 @@
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/* linux/arch/arm/mach-s5pv310/localtimer.c
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*
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* Cloned from linux/arch/arm/mach-realview/localtimer.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clockchips.h>
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#include <asm/irq.h>
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#include <asm/localtimer.h>
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/*
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* Setup the local clock events for a CPU.
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*/
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void __cpuinit local_timer_setup(struct clock_event_device *evt)
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{
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evt->irq = IRQ_LOCALTIMER;
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twd_timer_setup(evt);
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}
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@ -0,0 +1,287 @@
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/* linux/arch/arm/mach-s5pv310/time.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5PV310 (and compatible) HRT support
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* PWM 2/4 is used for this feature
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/platform_device.h>
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#include <asm/smp_twd.h>
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#include <mach/map.h>
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#include <plat/regs-timer.h>
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#include <asm/mach/time.h>
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static unsigned long clock_count_per_tick;
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static struct clk *tin2;
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static struct clk *tin4;
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static struct clk *tdiv2;
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static struct clk *tdiv4;
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static struct clk *timerclk;
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static void s5pv310_pwm_stop(unsigned int pwm_id)
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{
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unsigned long tcon;
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tcon = __raw_readl(S3C2410_TCON);
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switch (pwm_id) {
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case 2:
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tcon &= ~S3C2410_TCON_T2START;
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break;
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case 4:
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tcon &= ~S3C2410_TCON_T4START;
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break;
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default:
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break;
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}
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__raw_writel(tcon, S3C2410_TCON);
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}
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static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
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{
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unsigned long tcon;
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tcon = __raw_readl(S3C2410_TCON);
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/* timers reload after counting zero, so reduce the count by 1 */
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tcnt--;
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/* ensure timer is stopped... */
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switch (pwm_id) {
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case 2:
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tcon &= ~(0xf<<12);
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tcon |= S3C2410_TCON_T2MANUALUPD;
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__raw_writel(tcnt, S3C2410_TCNTB(2));
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__raw_writel(tcnt, S3C2410_TCMPB(2));
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__raw_writel(tcon, S3C2410_TCON);
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break;
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case 4:
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tcon &= ~(7<<20);
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tcon |= S3C2410_TCON_T4MANUALUPD;
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__raw_writel(tcnt, S3C2410_TCNTB(4));
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__raw_writel(tcnt, S3C2410_TCMPB(4));
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__raw_writel(tcon, S3C2410_TCON);
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break;
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default:
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break;
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}
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}
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static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
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{
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unsigned long tcon;
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tcon = __raw_readl(S3C2410_TCON);
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switch (pwm_id) {
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case 2:
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tcon |= S3C2410_TCON_T2START;
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tcon &= ~S3C2410_TCON_T2MANUALUPD;
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if (periodic)
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tcon |= S3C2410_TCON_T2RELOAD;
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else
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tcon &= ~S3C2410_TCON_T2RELOAD;
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break;
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case 4:
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tcon |= S3C2410_TCON_T4START;
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tcon &= ~S3C2410_TCON_T4MANUALUPD;
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if (periodic)
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tcon |= S3C2410_TCON_T4RELOAD;
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else
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tcon &= ~S3C2410_TCON_T4RELOAD;
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break;
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default:
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break;
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}
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__raw_writel(tcon, S3C2410_TCON);
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}
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static int s5pv310_pwm_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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s5pv310_pwm_init(2, cycles);
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s5pv310_pwm_start(2, 0);
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return 0;
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}
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static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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s5pv310_pwm_stop(2);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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s5pv310_pwm_init(2, clock_count_per_tick);
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s5pv310_pwm_start(2, 1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device pwm_event_device = {
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.name = "pwm_timer2",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.shift = 32,
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.set_next_event = s5pv310_pwm_set_next_event,
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.set_mode = s5pv310_pwm_set_mode,
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};
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irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &pwm_event_device;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction s5pv310_clock_event_irq = {
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.name = "pwm_timer2_irq",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = s5pv310_clock_event_isr,
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};
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static void __init s5pv310_clockevent_init(void)
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{
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unsigned long pclk;
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unsigned long clock_rate;
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struct clk *tscaler;
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pclk = clk_get_rate(timerclk);
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/* configure clock tick */
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tscaler = clk_get_parent(tdiv2);
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clk_set_rate(tscaler, pclk / 2);
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clk_set_rate(tdiv2, pclk / 2);
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clk_set_parent(tin2, tdiv2);
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clock_rate = clk_get_rate(tin2);
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clock_count_per_tick = clock_rate / HZ;
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pwm_event_device.mult =
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div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
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pwm_event_device.max_delta_ns =
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clockevent_delta2ns(-1, &pwm_event_device);
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pwm_event_device.min_delta_ns =
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clockevent_delta2ns(1, &pwm_event_device);
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pwm_event_device.cpumask = cpumask_of(0);
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clockevents_register_device(&pwm_event_device);
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setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq);
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}
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static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
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{
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return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
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}
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struct clocksource pwm_clocksource = {
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.name = "pwm_timer4",
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.rating = 250,
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.read = s5pv310_pwm4_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 20,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
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};
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static void __init s5pv310_clocksource_init(void)
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{
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unsigned long pclk;
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unsigned long clock_rate;
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pclk = clk_get_rate(timerclk);
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clk_set_rate(tdiv4, pclk / 2);
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clk_set_parent(tin4, tdiv4);
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clock_rate = clk_get_rate(tin4);
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s5pv310_pwm_init(4, ~0);
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s5pv310_pwm_start(4, 1);
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pwm_clocksource.mult =
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clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift);
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if (clocksource_register(&pwm_clocksource))
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panic("%s: can't register clocksource\n", pwm_clocksource.name);
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}
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static void __init s5pv310_timer_resources(void)
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{
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struct platform_device tmpdev;
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tmpdev.dev.bus = &platform_bus_type;
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timerclk = clk_get(NULL, "timers");
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if (IS_ERR(timerclk))
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panic("failed to get timers clock for system timer");
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clk_enable(timerclk);
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tmpdev.id = 2;
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tin2 = clk_get(&tmpdev.dev, "pwm-tin");
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if (IS_ERR(tin2))
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panic("failed to get pwm-tin2 clock for system timer");
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tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
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if (IS_ERR(tdiv2))
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panic("failed to get pwm-tdiv2 clock for system timer");
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clk_enable(tin2);
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tmpdev.id = 4;
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tin4 = clk_get(&tmpdev.dev, "pwm-tin");
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if (IS_ERR(tin4))
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panic("failed to get pwm-tin4 clock for system timer");
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tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
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if (IS_ERR(tdiv4))
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panic("failed to get pwm-tdiv4 clock for system timer");
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clk_enable(tin4);
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}
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static void __init s5pv310_timer_init(void)
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{
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base = S5P_VA_TWD;
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#endif
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s5pv310_timer_resources();
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s5pv310_clockevent_init();
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s5pv310_clocksource_init();
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}
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struct sys_timer s5pv310_timer = {
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.init = s5pv310_timer_init,
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};
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@ -22,6 +22,7 @@ extern int s5pv310_init(void);
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extern void s5pv310_init_irq(void);
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extern void s5pv310_map_io(void);
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extern void s5pv310_init_clocks(int xtal);
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extern struct sys_timer s5pv310_timer;
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#define s5pv310_init_uarts s5pv310_common_init_uarts
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@ -12,7 +12,7 @@ obj- :=
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# Objects we always build independent of SoC choice
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obj-y += init.o
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obj-y += time.o
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obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
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obj-y += clock.o
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obj-y += pwm-clock.o
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obj-y += gpio.o
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