dmaengine: rcar-dmac: Fix DMACHCLR handling if iommu is mapped
The commit20c169aceb
("dmaengine: rcar-dmac: clear pertinence number of channels") forgets to clear the last channel by DMACHCLR in rcar_dmac_init() (and doesn't need to clear the first channel) if iommu is mapped to the device. So, this patch fixes it by using "channels_mask" bitfield. Note that the hardware and driver don't support more than 32 bits in DMACHCLR register anyway, so this patch should reject more than 32 channels in rcar_dmac_parse_of(). Fixes:20c169aceb
("dmaengine: rcar-dmac: clear pertinence number of channels") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1567424643-26629-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -192,6 +192,7 @@ struct rcar_dmac_chan {
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* @iomem: remapped I/O memory base
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* @n_channels: number of available channels
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* @channels: array of DMAC channels
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* @channels_mask: bitfield of which DMA channels are managed by this driver
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* @modules: bitmask of client modules in use
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*/
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struct rcar_dmac {
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@ -202,6 +203,7 @@ struct rcar_dmac {
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unsigned int n_channels;
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struct rcar_dmac_chan *channels;
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unsigned int channels_mask;
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DECLARE_BITMAP(modules, 256);
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};
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@ -438,7 +440,7 @@ static int rcar_dmac_init(struct rcar_dmac *dmac)
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u16 dmaor;
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/* Clear all channels and enable the DMAC globally. */
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rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
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rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
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rcar_dmac_write(dmac, RCAR_DMAOR,
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RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
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@ -814,6 +816,9 @@ static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
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for (i = 0; i < dmac->n_channels; ++i) {
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struct rcar_dmac_chan *chan = &dmac->channels[i];
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if (!(dmac->channels_mask & BIT(i)))
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continue;
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/* Stop and reinitialize the channel. */
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spin_lock_irq(&chan->lock);
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rcar_dmac_chan_halt(chan);
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@ -1776,6 +1781,8 @@ static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
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return 0;
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}
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#define RCAR_DMAC_MAX_CHANNELS 32
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static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
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{
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struct device_node *np = dev->of_node;
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@ -1787,12 +1794,16 @@ static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
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return ret;
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}
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if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
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/* The hardware and driver don't support more than 32 bits in CHCLR */
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if (dmac->n_channels <= 0 ||
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dmac->n_channels >= RCAR_DMAC_MAX_CHANNELS) {
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dev_err(dev, "invalid number of channels %u\n",
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dmac->n_channels);
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return -EINVAL;
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}
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dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);
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return 0;
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}
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@ -1802,7 +1813,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
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DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
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DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
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DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
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unsigned int channels_offset = 0;
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struct dma_device *engine;
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struct rcar_dmac *dmac;
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struct resource *mem;
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@ -1831,10 +1841,8 @@ static int rcar_dmac_probe(struct platform_device *pdev)
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* level we can't disable it selectively, so ignore channel 0 for now if
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* the device is part of an IOMMU group.
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*/
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if (device_iommu_mapped(&pdev->dev)) {
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dmac->n_channels--;
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channels_offset = 1;
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}
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if (device_iommu_mapped(&pdev->dev))
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dmac->channels_mask &= ~BIT(0);
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dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
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sizeof(*dmac->channels), GFP_KERNEL);
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@ -1892,8 +1900,10 @@ static int rcar_dmac_probe(struct platform_device *pdev)
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INIT_LIST_HEAD(&engine->channels);
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for (i = 0; i < dmac->n_channels; ++i) {
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ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i],
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i + channels_offset);
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if (!(dmac->channels_mask & BIT(i)))
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continue;
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ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], i);
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if (ret < 0)
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goto error;
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}
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