sky2: handle advanced error recovery config issues
The PCI AER support may not work for a couple of reasons. It may not be configured into the kernel or there may be a BIOS bug that prevents MMCONFIG from working. If MMCONFIG doesn't work then the PCI registers that control AER will not be accessible via pci_read_config functions; luckly there is another window to access PCI space in the device, so use that. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -2435,13 +2435,26 @@ static void sky2_hw_intr(struct sky2_hw *hw)
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if (status & Y2_IS_PCI_EXP) {
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/* PCI-Express uncorrectable Error occurred */
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int pos = pci_find_aer_capability(hw->pdev);
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int aer = pci_find_aer_capability(hw->pdev);
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u32 err;
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pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err);
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if (aer) {
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pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS,
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&err);
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pci_cleanup_aer_uncorrect_error_status(pdev);
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} else {
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/* Either AER not configured, or not working
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* because of bad MMCONFIG, so just do recover
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* manually.
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*/
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err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
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sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
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0xfffffffful);
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}
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if (net_ratelimit())
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dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
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pci_cleanup_aer_uncorrect_error_status(pdev);
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}
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if (status & Y2_HWE_L1_MASK)
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@ -2799,9 +2812,18 @@ static void sky2_reset(struct sky2_hw *hw)
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cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (cap) {
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/* Check for advanced error reporting */
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pci_cleanup_aer_uncorrect_error_status(pdev);
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pci_cleanup_aer_correct_error_status(pdev);
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if (pci_find_aer_capability(pdev)) {
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/* Check for advanced error reporting */
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pci_cleanup_aer_uncorrect_error_status(pdev);
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pci_cleanup_aer_correct_error_status(pdev);
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} else {
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dev_warn(&pdev->dev,
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"PCI Express Advanced Error Reporting"
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" not configured or MMCONFIG problem?\n");
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sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
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0xfffffffful);
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}
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/* If error bit is stuck on ignore it */
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if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
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@ -247,7 +247,8 @@ enum csr_regs {
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B3_PA_CTRL = 0x01f0,
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B3_PA_TEST = 0x01f2,
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Y2_CFG_SPC = 0x1c00,
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Y2_CFG_SPC = 0x1c00, /* PCI config space region */
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Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */
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};
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/* B0_CTST 16 bit Control/Status register */
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