Pin control fixes for v4.12, take three:

- Make the AMD driver use a regular interrupt rather than a chained one,
   so the system does not lock up.
 
 - Fix a function call error deep inside the STM32 driver.
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Merge tag 'pinctrl-v4.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull more pin control fixes from Linus Walleij:
 "Some late arriving fixes. I should have sent earlier, just swamped
  with work as usual. Thomas patch makes AMD systems usable despite
  firmware bugs so it is fairly important.

   - Make the AMD driver use a regular interrupt rather than a chained
     one, so the system does not lock up.

   - Fix a function call error deep inside the STM32 driver"

* tag 'pinctrl-v4.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: stm32: Fix bad function call
  pinctrl/amd: Use regular interrupt instead of chained

drivers/pinctrl/pinctrl-amd.c

@@ -495,64 +495,54 @@ static struct irq_chip amd_gpio_irqchip = {
 	.flags        = IRQCHIP_SKIP_SET_WAKE,
 };
 
-static void amd_gpio_irq_handler(struct irq_desc *desc)
+#define PIN_IRQ_PENDING	(BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
+
+static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
 {
-	u32 i;
+	struct amd_gpio *gpio_dev = dev_id;
-	u32 off;
+	struct gpio_chip *gc = &gpio_dev->gc;
-	u32 reg;
+	irqreturn_t ret = IRQ_NONE;
-	u32 pin_reg;
+	unsigned int i, irqnr;
-	u64 reg64;
-	int handled = 0;
-	unsigned int irq;
 	unsigned long flags;
-	struct irq_chip *chip = irq_desc_get_chip(desc);
+	u32 *regs, regval;
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+	u64 status, mask;
-	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
 
-	chained_irq_enter(chip, desc);
+	/* Read the wake status */
-	/*enable GPIO interrupt again*/
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
+	status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
-	reg64 = reg;
+	status <<= 32;
-	reg64 = reg64 << 32;
+	status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
-
-	reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
-	reg64 |= reg;
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
-	/*
+	/* Bit 0-45 contain the relevant status bits */
-	 * first 46 bits indicates interrupt status.
+	status &= (1ULL << 46) - 1;
-	 * one bit represents four interrupt sources.
+	regs = gpio_dev->base;
-	*/
+	for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
-	for (off = 0; off < 46 ; off++) {
+		if (!(status & mask))
-		if (reg64 & BIT(off)) {
+			continue;
-			for (i = 0; i < 4; i++) {
+		status &= ~mask;
-				pin_reg = readl(gpio_dev->base +
+
-						(off * 4 + i) * 4);
+		/* Each status bit covers four pins */
-				if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
+		for (i = 0; i < 4; i++) {
-					(pin_reg & BIT(WAKE_STS_OFF))) {
+			regval = readl(regs + i);
-					irq = irq_find_mapping(gc->irqdomain,
+			if (!(regval & PIN_IRQ_PENDING))
-								off * 4 + i);
+				continue;
-					generic_handle_irq(irq);
+			irq = irq_find_mapping(gc->irqdomain, irqnr + i);
-					writel(pin_reg,
+			generic_handle_irq(irq);
-						gpio_dev->base
+			/* Clear interrupt */
-						+ (off * 4 + i) * 4);
+			writel(regval, regs + i);
-					handled++;
+			ret = IRQ_HANDLED;
-				}
-			}
 		}
 	}
 
-	if (handled == 0)
+	/* Signal EOI to the GPIO unit */
-		handle_bad_irq(desc);
-
 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
-	reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
+	regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
-	reg |= EOI_MASK;
+	regval |= EOI_MASK;
-	writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
+	writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
 
-	chained_irq_exit(chip, desc);
+	return ret;
 }
 
 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
@@ -821,10 +811,11 @@ static int amd_gpio_probe(struct platform_device *pdev)
 		goto out2;
 	}
 
-	gpiochip_set_chained_irqchip(&gpio_dev->gc,
+	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0,
-				 &amd_gpio_irqchip,
+			       KBUILD_MODNAME, gpio_dev);
-				 irq_base,
+	if (ret)
-				 amd_gpio_irq_handler);
+		goto out2;
+
 	platform_set_drvdata(pdev, gpio_dev);
 
 	dev_dbg(&pdev->dev, "amd gpio driver loaded\n");

drivers/pinctrl/stm32/pinctrl-stm32.c

@@ -798,7 +798,7 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
 		break;
 	case PIN_CONFIG_OUTPUT:
 		__stm32_gpio_set(bank, offset, arg);
-		ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+		ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
 		break;
 	default:
 		ret = -EINVAL;