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drm/i915: Gather the HDMI level shifter logic into one place 

The knowledge about the HDMI/DVI DDI translation table was scattered
around.
  - info->hdmi_level_shift was initialized with 6, the index of the 800
    mV, 0dB translation
  - A check on the VBT value was done to ensure it wasn't overflowing
    the translation table (< 0xC)
  - The actual programming was done in intel_ddi.c

As we need to change that knowledge for Broadwell, let's gather
everything into one place.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2014-08-01 11:07:54 +01:00 committed by Daniel Vetter
parent da46f936bb
commit ce4dd49e97
3 changed files with 24 additions and 9 deletions
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6
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1232,6 +1232,12 @@ enum modeset_restore {
}; };
struct ddi_vbt_port_info { struct ddi_vbt_port_info {
/*
* This is an index in the HDMI/DVI DDI buffer translation table.
* The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
* populate this field.
*/
#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
uint8_t hdmi_level_shift; uint8_t hdmi_level_shift;
uint8_t supports_dvi:1; uint8_t supports_dvi:1;

13
drivers/gpu/drm/i915/intel_bios.c
View File

@ -976,12 +976,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
if (bdb->version >= 158) { if (bdb->version >= 158) {
/* The VBT HDMI level shift values match the table we have. */ /* The VBT HDMI level shift values match the table we have. */
hdmi_level_shift = child->raw[7] & 0xF; hdmi_level_shift = child->raw[7] & 0xF;
if (hdmi_level_shift < 0xC) { DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", port_name(port),
port_name(port), hdmi_level_shift);
hdmi_level_shift); info->hdmi_level_shift = hdmi_level_shift;
info->hdmi_level_shift = hdmi_level_shift;
}
} }
} }
@ -1114,8 +1112,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
struct ddi_vbt_port_info *info = struct ddi_vbt_port_info *info =
&dev_priv->vbt.ddi_port_info[port]; &dev_priv->vbt.ddi_port_info[port];
/* Recommended BSpec default: 800mV 0dB. */ info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
info->hdmi_level_shift = 6;
info->supports_dvi = (port != PORT_A && port != PORT_E); info->supports_dvi = (port != PORT_A && port != PORT_E);
info->supports_hdmi = info->supports_dvi; info->supports_hdmi = info->supports_dvi;

14
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -145,7 +145,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 reg; u32 reg;
int i; int i, n_hdmi_entries, hdmi_800mV_0dB;
int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
const u32 *ddi_translations_fdi; const u32 *ddi_translations_fdi;
const u32 *ddi_translations_dp; const u32 *ddi_translations_dp;
@ -156,15 +156,21 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
ddi_translations_fdi = bdw_ddi_translations_fdi; ddi_translations_fdi = bdw_ddi_translations_fdi;
ddi_translations_dp = bdw_ddi_translations_dp; ddi_translations_dp = bdw_ddi_translations_dp;
ddi_translations_edp = bdw_ddi_translations_edp; ddi_translations_edp = bdw_ddi_translations_edp;
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
hdmi_800mV_0dB = 6;
} else if (IS_HASWELL(dev)) { } else if (IS_HASWELL(dev)) {
ddi_translations_fdi = hsw_ddi_translations_fdi; ddi_translations_fdi = hsw_ddi_translations_fdi;
ddi_translations_dp = hsw_ddi_translations_dp; ddi_translations_dp = hsw_ddi_translations_dp;
ddi_translations_edp = hsw_ddi_translations_dp; ddi_translations_edp = hsw_ddi_translations_dp;
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
hdmi_800mV_0dB = 6;
} else { } else {
WARN(1, "ddi translation table missing\n"); WARN(1, "ddi translation table missing\n");
ddi_translations_edp = bdw_ddi_translations_dp; ddi_translations_edp = bdw_ddi_translations_dp;
ddi_translations_fdi = bdw_ddi_translations_fdi; ddi_translations_fdi = bdw_ddi_translations_fdi;
ddi_translations_dp = bdw_ddi_translations_dp; ddi_translations_dp = bdw_ddi_translations_dp;
n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
hdmi_800mV_0dB = 6;
} }
switch (port) { switch (port) {
@ -193,6 +199,12 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
I915_WRITE(reg, ddi_translations[i]); I915_WRITE(reg, ddi_translations[i]);
reg += 4; reg += 4;
} }
/* Choose a good default if VBT is badly populated */
if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
hdmi_level >= n_hdmi_entries)
hdmi_level = hdmi_800mV_0dB;
/* Entry 9 is for HDMI: */ /* Entry 9 is for HDMI: */
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);