Merge branch 'dwmac-mediatek-add-more-support-for-RMII'
Biao Huang says:
====================
net-next: stmmac: dwmac-mediatek: add more support for RMII
changes in v2:
PATCH 1/2 net-next: stmmac: mediatek: add more support for RMII
As Andrew's comments, add the "rmii_internal" clock to the list of clocks.
PATCH 2/2 net-next: dt-binding: dwmac-mediatek: add more description for RMII
document the "rmii_internal" clock in dt-bindings
rewrite the sample dts in dt-bindings.
v1:
This series is for support RMII when MT2712 SoC provides the reference clock.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
ce2b5a3af0
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@ -14,7 +14,7 @@ Required properties:
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Should be "macirq" for the main MAC IRQ
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- clocks: Must contain a phandle for each entry in clock-names.
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- clock-names: The name of the clock listed in the clocks property. These are
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"axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC
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"axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
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- mac-address: See ethernet.txt in the same directory
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- phy-mode: See ethernet.txt in the same directory
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- mediatek,pericfg: A phandle to the syscon node that control ethernet
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@ -23,8 +23,10 @@ Required properties:
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Optional properties:
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- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
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It should be defined for RGMII/MII interface.
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It should be defined for RMII interface when the reference clock is from MT2712 SoC.
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- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
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It should be defined for RGMII/MII/RMII interface.
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It should be defined for RGMII/MII interface.
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It should be defined for RMII interface.
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Both delay properties need to be a multiple of 170 for RGMII interface,
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or will round down. Range 0~31*170.
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Both delay properties need to be a multiple of 550 for MII/RMII interface,
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@ -34,13 +36,20 @@ or will round down. Range 0~31*550.
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reference clock, which is from external PHYs, is connected to RXC pin
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on MT2712 SoC.
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Otherwise, is connected to TXC pin.
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- mediatek,rmii-clk-from-mac: boolean property, if present indicates that
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MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
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- mediatek,txc-inverse: boolean property, if present indicates that
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1. tx clock will be inversed in MII/RGMII case,
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2. tx clock inside MAC will be inversed relative to reference clock
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which is from external PHYs in RMII case, and it rarely happen.
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3. the reference clock, which outputs to TXC pin will be inversed in RMII case
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when the reference clock is from MT2712 SoC.
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- mediatek,rxc-inverse: boolean property, if present indicates that
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1. rx clock will be inversed in MII/RGMII case.
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2. reference clock will be inversed when arrived at MAC in RMII case.
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2. reference clock will be inversed when arrived at MAC in RMII case, when
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the reference clock is from external PHYs.
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3. the inside clock, which be sent to MAC, will be inversed in RMII case when
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the reference clock is from MT2712 SoC.
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- assigned-clocks: mac_main and ptp_ref clocks
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- assigned-clock-parents: parent clocks of the assigned clocks
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@ -50,29 +59,33 @@ Example:
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reg = <0 0x1101c000 0 0x1300>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "macirq";
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phy-mode ="rgmii";
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phy-mode ="rgmii-rxid";
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mac-address = [00 55 7b b5 7d f7];
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clock-names = "axi",
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"apb",
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"mac_main",
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"ptp_ref",
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"ptp_top";
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"rmii_internal";
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clocks = <&pericfg CLK_PERI_GMAC>,
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<&pericfg CLK_PERI_GMAC_PCLK>,
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<&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>;
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<&topckgen CLK_TOP_ETHER_50M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
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assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_SEL>;
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<&topckgen CLK_TOP_ETHER_50M_SEL>,
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<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
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<&topckgen CLK_TOP_APLL1_D3>;
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<&topckgen CLK_TOP_APLL1_D3>,
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<&topckgen CLK_TOP_ETHERPLL_50M>;
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power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
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mediatek,pericfg = <&pericfg>;
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mediatek,tx-delay-ps = <1530>;
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mediatek,rx-delay-ps = <1530>;
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mediatek,rmii-rxc;
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mediatek,txc-inverse;
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mediatek,rxc-inverse;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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snps,txpbl = <1>;
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snps,rxpbl = <1>;
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snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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};
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@ -55,6 +55,8 @@ struct mediatek_dwmac_plat_data {
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struct regmap *peri_regmap;
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struct device *dev;
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phy_interface_t phy_mode;
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int num_clks_to_config;
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bool rmii_clk_from_mac;
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bool rmii_rxc;
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};
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@ -73,21 +75,33 @@ struct mediatek_dwmac_variant {
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/* list of clocks required for mac */
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static const char * const mt2712_dwmac_clk_l[] = {
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"axi", "apb", "mac_main", "ptp_ref"
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"axi", "apb", "mac_main", "ptp_ref", "rmii_internal"
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};
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static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
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{
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int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
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int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
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u32 intf_val = 0;
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/* The clock labeled as "rmii_internal" in mt2712_dwmac_clk_l is needed
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* only in RMII(when MAC provides the reference clock), and useless for
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* RGMII/MII/RMII(when PHY provides the reference clock).
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* num_clks_to_config indicates the real number of clocks should be
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* configured, equals to (plat->variant->num_clks - 1) in default for all the case,
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* then +1 for rmii_clk_from_mac case.
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*/
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plat->num_clks_to_config = plat->variant->num_clks - 1;
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/* select phy interface in top control domain */
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switch (plat->phy_mode) {
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case PHY_INTERFACE_MODE_MII:
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intf_val |= PHY_INTF_MII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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intf_val |= (PHY_INTF_RMII | rmii_rxc);
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if (plat->rmii_clk_from_mac)
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plat->num_clks_to_config++;
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intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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@ -173,35 +187,50 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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break;
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case PHY_INTERFACE_MODE_RMII:
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/* the rmii reference clock is from external phy,
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* and the property "rmii_rxc" indicates which pin(TXC/RXC)
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* the reference clk is connected to. The reference clock is a
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* received signal, so rx_delay/rx_inv are used to indicate
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* the reference clock timing adjustment
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*/
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if (plat->rmii_rxc) {
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/* the rmii reference clock from outside is connected
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* to RXC pin, the reference clock will be adjusted
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* by RXC delay macro circuit.
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*/
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delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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} else {
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/* the rmii reference clock from outside is connected
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* to TXC pin, the reference clock will be adjusted
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* by TXC delay macro circuit.
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if (plat->rmii_clk_from_mac) {
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/* case 1: mac provides the rmii reference clock,
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* and the clock output to TXC pin.
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* The egress timing can be adjusted by GTXC delay macro circuit.
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* The ingress timing can be adjusted by TXC delay macro circuit.
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*/
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delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
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} else {
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/* case 2: the rmii reference clock is from external phy,
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* and the property "rmii_rxc" indicates which pin(TXC/RXC)
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* the reference clk is connected to. The reference clock is a
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* received signal, so rx_delay/rx_inv are used to indicate
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* the reference clock timing adjustment
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*/
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if (plat->rmii_rxc) {
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/* the rmii reference clock from outside is connected
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* to RXC pin, the reference clock will be adjusted
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* by RXC delay macro circuit.
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*/
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delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
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} else {
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/* the rmii reference clock from outside is connected
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* to TXC pin, the reference clock will be adjusted
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* by TXC delay macro circuit.
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*/
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delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
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delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
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}
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/* tx_inv will inverse the tx clock inside mac relateive to
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* reference clock from external phy,
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* and this bit is located in the same register with fine-tune
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*/
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if (mac_delay->tx_inv)
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fine_val = ETH_RMII_DLY_TX_INV;
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}
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/* tx_inv will inverse the tx clock inside mac relateive to
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* reference clock from external phy,
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* and this bit is located in the same register with fine-tune
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*/
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if (mac_delay->tx_inv)
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fine_val = ETH_RMII_DLY_TX_INV;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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@ -278,6 +307,7 @@ static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
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mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
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mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
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plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
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plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
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return 0;
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}
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@ -294,6 +324,8 @@ static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
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for (i = 0; i < num; i++)
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plat->clks[i].id = variant->clk_list[i];
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plat->num_clks_to_config = variant->num_clks;
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return devm_clk_bulk_get(plat->dev, num, plat->clks);
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}
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@ -321,7 +353,7 @@ static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
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return ret;
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}
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ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
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ret = clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks);
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if (ret) {
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dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
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return ret;
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@ -336,9 +368,8 @@ static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
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static void mediatek_dwmac_exit(struct platform_device *pdev, void *priv)
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{
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struct mediatek_dwmac_plat_data *plat = priv;
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const struct mediatek_dwmac_variant *variant = plat->variant;
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clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
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clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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