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Merge branch 'dwmac-mediatek-add-more-support-for-RMII' 

Biao Huang says:

====================
net-next: stmmac: dwmac-mediatek: add more support for RMII

changes in v2:
 PATCH 1/2 net-next: stmmac: mediatek: add more support for RMII
        As Andrew's comments, add the "rmii_internal" clock to the list of clocks.

 PATCH 2/2 net-next: dt-binding: dwmac-mediatek: add more description for RMII
        document the "rmii_internal" clock in dt-bindings
        rewrite the sample dts in dt-bindings.

v1:
This series is for support RMII when MT2712 SoC provides the reference clock.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-12-17 13:48:31 -08:00
parent 4e133f76c1 882007ed78
commit ce2b5a3af0
2 changed files with 83 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
Documentation/devicetree/bindings/net/mediatek-dwmac.txt
View File

@ -14,7 +14,7 @@ Required properties:
Should be "macirq" for the main MAC IRQ
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: The name of the clock listed in the clocks property. These are
"axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC
"axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
- mac-address: See ethernet.txt in the same directory
- phy-mode: See ethernet.txt in the same directory
- mediatek,pericfg: A phandle to the syscon node that control ethernet
@ -23,8 +23,10 @@ Required properties:
Optional properties:
- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
It should be defined for RGMII/MII interface.
It should be defined for RMII interface when the reference clock is from MT2712 SoC.
- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
It should be defined for RGMII/MII/RMII interface.
It should be defined for RGMII/MII interface.
It should be defined for RMII interface.
Both delay properties need to be a multiple of 170 for RGMII interface,
or will round down. Range 0~31*170.
Both delay properties need to be a multiple of 550 for MII/RMII interface,
@ -34,13 +36,20 @@ or will round down. Range 0~31*550.
reference clock, which is from external PHYs, is connected to RXC pin
on MT2712 SoC.
Otherwise, is connected to TXC pin.
- mediatek,rmii-clk-from-mac: boolean property, if present indicates that
MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
- mediatek,txc-inverse: boolean property, if present indicates that
1. tx clock will be inversed in MII/RGMII case,
2. tx clock inside MAC will be inversed relative to reference clock
which is from external PHYs in RMII case, and it rarely happen.
3. the reference clock, which outputs to TXC pin will be inversed in RMII case
when the reference clock is from MT2712 SoC.
- mediatek,rxc-inverse: boolean property, if present indicates that
1. rx clock will be inversed in MII/RGMII case.
2. reference clock will be inversed when arrived at MAC in RMII case.
2. reference clock will be inversed when arrived at MAC in RMII case, when
the reference clock is from external PHYs.
3. the inside clock, which be sent to MAC, will be inversed in RMII case when
the reference clock is from MT2712 SoC.
- assigned-clocks: mac_main and ptp_ref clocks
- assigned-clock-parents: parent clocks of the assigned clocks
@ -50,29 +59,33 @@ Example:
reg = <0 0x1101c000 0 0x1300>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "macirq";
phy-mode ="rgmii";
phy-mode ="rgmii-rxid";
mac-address = [00 55 7b b5 7d f7];
clock-names = "axi",
"apb",
"mac_main",
"ptp_ref",
"ptp_top";
"rmii_internal";
clocks = <&pericfg CLK_PERI_GMAC>,
<&pericfg CLK_PERI_GMAC_PCLK>,
<&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>;
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>;
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
<&topckgen CLK_TOP_APLL1_D3>;
<&topckgen CLK_TOP_APLL1_D3>,
<&topckgen CLK_TOP_ETHERPLL_50M>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
mediatek,pericfg = <&pericfg>;
mediatek,tx-delay-ps = <1530>;
mediatek,rx-delay-ps = <1530>;
mediatek,rmii-rxc;
mediatek,txc-inverse;
mediatek,rxc-inverse;
snps,txpbl = <32>;
snps,rxpbl = <32>;
snps,txpbl = <1>;
snps,rxpbl = <1>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
};

89
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
View File

@ -55,6 +55,8 @@ struct mediatek_dwmac_plat_data {
struct regmap *peri_regmap;
struct device *dev;
phy_interface_t phy_mode;
int num_clks_to_config;
bool rmii_clk_from_mac;
bool rmii_rxc;
};
@ -73,21 +75,33 @@ struct mediatek_dwmac_variant {
/* list of clocks required for mac */
static const char * const mt2712_dwmac_clk_l[] = {
"axi", "apb", "mac_main", "ptp_ref"
"axi", "apb", "mac_main", "ptp_ref", "rmii_internal"
};
static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
{
int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
u32 intf_val = 0;
/* The clock labeled as "rmii_internal" in mt2712_dwmac_clk_l is needed
* only in RMII(when MAC provides the reference clock), and useless for
* RGMII/MII/RMII(when PHY provides the reference clock).
* num_clks_to_config indicates the real number of clocks should be
* configured, equals to (plat->variant->num_clks - 1) in default for all the case,
* then +1 for rmii_clk_from_mac case.
*/
plat->num_clks_to_config = plat->variant->num_clks - 1;
/* select phy interface in top control domain */
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
intf_val |= PHY_INTF_MII;
break;
case PHY_INTERFACE_MODE_RMII:
intf_val |= (PHY_INTF_RMII | rmii_rxc);
if (plat->rmii_clk_from_mac)
plat->num_clks_to_config++;
intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
@ -173,35 +187,50 @@ static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
break;
case PHY_INTERFACE_MODE_RMII:
/* the rmii reference clock is from external phy,
* and the property "rmii_rxc" indicates which pin(TXC/RXC)
* the reference clk is connected to. The reference clock is a
* received signal, so rx_delay/rx_inv are used to indicate
* the reference clock timing adjustment
*/
if (plat->rmii_rxc) {
/* the rmii reference clock from outside is connected
* to RXC pin, the reference clock will be adjusted
* by RXC delay macro circuit.
*/
delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
} else {
/* the rmii reference clock from outside is connected
* to TXC pin, the reference clock will be adjusted
* by TXC delay macro circuit.
if (plat->rmii_clk_from_mac) {
/* case 1: mac provides the rmii reference clock,
* and the clock output to TXC pin.
* The egress timing can be adjusted by GTXC delay macro circuit.
* The ingress timing can be adjusted by TXC delay macro circuit.
*/
delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);
delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);
} else {
/* case 2: the rmii reference clock is from external phy,
* and the property "rmii_rxc" indicates which pin(TXC/RXC)
* the reference clk is connected to. The reference clock is a
* received signal, so rx_delay/rx_inv are used to indicate
* the reference clock timing adjustment
*/
if (plat->rmii_rxc) {
/* the rmii reference clock from outside is connected
* to RXC pin, the reference clock will be adjusted
* by RXC delay macro circuit.
*/
delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);
} else {
/* the rmii reference clock from outside is connected
* to TXC pin, the reference clock will be adjusted
* by TXC delay macro circuit.
*/
delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);
}
/* tx_inv will inverse the tx clock inside mac relateive to
* reference clock from external phy,
* and this bit is located in the same register with fine-tune
*/
if (mac_delay->tx_inv)
fine_val = ETH_RMII_DLY_TX_INV;
}
/* tx_inv will inverse the tx clock inside mac relateive to
* reference clock from external phy,
* and this bit is located in the same register with fine-tune
*/
if (mac_delay->tx_inv)
fine_val = ETH_RMII_DLY_TX_INV;
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
@ -278,6 +307,7 @@ static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
return 0;
}
@ -294,6 +324,8 @@ static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
for (i = 0; i < num; i++)
plat->clks[i].id = variant->clk_list[i];
plat->num_clks_to_config = variant->num_clks;
return devm_clk_bulk_get(plat->dev, num, plat->clks);
}
@ -321,7 +353,7 @@ static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
return ret;
}
ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
ret = clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks);
if (ret) {
dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
return ret;
@ -336,9 +368,8 @@ static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
static void mediatek_dwmac_exit(struct platform_device *pdev, void *priv)
{
struct mediatek_dwmac_plat_data *plat = priv;
const struct mediatek_dwmac_variant *variant = plat->variant;
clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);