EDAC/i10nm: Update driver to support different bus number config register offsets
The i10nm_edac driver failed to load on Ice Lake and Tremont/Jacobsville servers if their CPU stepping >= 4 and failed on Ice Lake-D servers from stepping 0. The root cause was that for Ice Lake and Tremont/Jacobsville servers with CPU stepping >=4, the offset for bus number configuration register was updated from 0xcc to 0xd0. For Ice Lake-D servers, all the steppings use the updated 0xd0 offset. Fix the issue by using the appropriate offset for bus number configuration register according to the CPU model number and stepping. Reported-by: Jerry Chen <jerry.t.chen@intel.com> Reported-and-tested-by: Jin Wen <wen.jin@intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/linux-edac/20200427084022.GC11036@zn.tnic
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@ -122,16 +122,22 @@ static int i10nm_get_all_munits(void)
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return 0;
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}
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static struct res_config i10nm_cfg = {
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static struct res_config i10nm_cfg0 = {
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.type = I10NM,
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.decs_did = 0x3452,
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.busno_cfg_offset = 0xcc,
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};
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static struct res_config i10nm_cfg1 = {
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.type = I10NM,
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.decs_did = 0x3452,
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.busno_cfg_offset = 0xd0,
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};
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static const struct x86_cpu_id i10nm_cpuids[] = {
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &i10nm_cfg),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &i10nm_cfg),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &i10nm_cfg),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &i10nm_cfg0),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &i10nm_cfg0),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &i10nm_cfg1),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
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@ -258,6 +264,10 @@ static int __init i10nm_init(void)
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cfg = (struct res_config *)id->driver_data;
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/* Newer steppings have different offset for ATOM_TREMONT_D/ICELAKE_X */
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if (boot_cpu_data.x86_stepping >= 4)
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cfg->busno_cfg_offset = 0xd0;
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rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
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if (rc)
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return rc;
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