ARM: remove u300 platform
The Ericsson U300 platform was one of two ARM929 based SoC platforms for mobile phones in ST-Ericsson after the merger of Ericsson with ST-NXP into ST-Ericsson, the other one being the ST Nomadik. The platform was not widely adopted in Linux based systems and was replaced with the far superior ST-Ericsson U8500 in 2011, but Linus Walleij kept maintaining the code for the whole time. Linus continues to use the Nomadik machine, but decided to drop u300 from the kernel as part of this year's spring cleaning. Thanks for having maintained it all these years. Cc: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/lkml/CACRpkdbJkiHR9FSfJTH_5d_qRU1__dRXHM1TL40iqNRKbGQfrQ@mail.gmail.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
edd4488aea
commit
ce1380c9f4
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@ -1,46 +0,0 @@
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ST-Ericsson U300 Device Tree Bindings
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For various board the "board" node may contain specific properties
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that pertain to this particular board, such as board-specific GPIOs
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or board power regulator supplies.
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Required root node property:
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compatible="stericsson,u300";
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Required node: syscon
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This contains the system controller.
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- compatible: must be "stericsson,u300-syscon".
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- reg: the base address and size of the system controller.
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Boards with the U300 SoC include:
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S365 "Small Board U365":
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Required node: s365
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This contains the board-specific information.
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- compatible: must be "stericsson,s365".
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- vana15-supply: the regulator supplying the 1.5V to drive the
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board.
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- syscon: a pointer to the syscon node so we can access the
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syscon registers to set the board as self-powered.
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Example:
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/ {
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model = "ST-Ericsson U300";
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compatible = "stericsson,u300";
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#address-cells = <1>;
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#size-cells = <1>;
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s365 {
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compatible = "stericsson,s365";
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vana15-supply = <&ab3100_ldo_d_reg>;
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syscon = <&syscon>;
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};
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syscon: syscon@c0011000 {
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compatible = "stericsson,u300-syscon";
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reg = <0xc0011000 0x1000>;
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};
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};
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14
MAINTAINERS
14
MAINTAINERS
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@ -2136,7 +2136,7 @@ ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
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M: Michael Petchkovsky <mkpetch@internode.on.net>
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M: Michael Petchkovsky <mkpetch@internode.on.net>
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S: Maintained
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S: Maintained
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ARM/NOMADIK/U300/Ux500 ARCHITECTURES
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ARM/NOMADIK/Ux500 ARCHITECTURES
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M: Linus Walleij <linus.walleij@linaro.org>
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M: Linus Walleij <linus.walleij@linaro.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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S: Maintained
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@ -2145,35 +2145,23 @@ F: Documentation/devicetree/bindings/arm/ste-*
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F: Documentation/devicetree/bindings/arm/ux500.yaml
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F: Documentation/devicetree/bindings/arm/ux500.yaml
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F: Documentation/devicetree/bindings/arm/ux500/
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F: Documentation/devicetree/bindings/arm/ux500/
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F: Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
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F: Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
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F: Documentation/devicetree/bindings/i2c/i2c-stu300.txt
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F: arch/arm/boot/dts/ste-*
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F: arch/arm/boot/dts/ste-*
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F: arch/arm/mach-nomadik/
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F: arch/arm/mach-nomadik/
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F: arch/arm/mach-u300/
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F: arch/arm/mach-ux500/
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F: arch/arm/mach-ux500/
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F: drivers/clk/clk-nomadik.c
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F: drivers/clk/clk-nomadik.c
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F: drivers/clk/clk-u300.c
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F: drivers/clocksource/clksrc-dbx500-prcmu.c
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F: drivers/clocksource/clksrc-dbx500-prcmu.c
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F: drivers/clocksource/timer-u300.c
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F: drivers/dma/coh901318*
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F: drivers/dma/ste_dma40*
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F: drivers/dma/ste_dma40*
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F: drivers/hwspinlock/u8500_hsem.c
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F: drivers/hwspinlock/u8500_hsem.c
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F: drivers/i2c/busses/i2c-nomadik.c
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F: drivers/i2c/busses/i2c-nomadik.c
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F: drivers/i2c/busses/i2c-stu300.c
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F: drivers/iio/adc/ab8500-gpadc.c
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F: drivers/iio/adc/ab8500-gpadc.c
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F: drivers/mfd/ab3100*
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F: drivers/mfd/ab8500*
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F: drivers/mfd/ab8500*
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F: drivers/mfd/abx500*
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F: drivers/mfd/abx500*
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F: drivers/mfd/db8500*
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F: drivers/mfd/db8500*
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F: drivers/mfd/dbx500*
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F: drivers/mfd/dbx500*
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F: drivers/pinctrl/nomadik/
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F: drivers/pinctrl/nomadik/
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F: drivers/pinctrl/pinctrl-coh901*
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F: drivers/pinctrl/pinctrl-u300.c
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F: drivers/rtc/rtc-ab3100.c
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F: drivers/rtc/rtc-ab8500.c
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F: drivers/rtc/rtc-ab8500.c
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F: drivers/rtc/rtc-coh901331.c
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F: drivers/rtc/rtc-pl031.c
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F: drivers/rtc/rtc-pl031.c
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F: drivers/soc/ux500/
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F: drivers/soc/ux500/
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F: drivers/watchdog/coh901327_wdt.c
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ARM/NUVOTON NPCM ARCHITECTURE
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ARM/NUVOTON NPCM ARCHITECTURE
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M: Avi Fishman <avifishman70@gmail.com>
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M: Avi Fishman <avifishman70@gmail.com>
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@ -704,8 +704,6 @@ source "arch/arm/mach-sunxi/Kconfig"
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source "arch/arm/mach-tegra/Kconfig"
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source "arch/arm/mach-tegra/Kconfig"
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source "arch/arm/mach-u300/Kconfig"
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source "arch/arm/mach-uniphier/Kconfig"
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source "arch/arm/mach-uniphier/Kconfig"
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source "arch/arm/mach-ux500/Kconfig"
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source "arch/arm/mach-ux500/Kconfig"
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@ -1280,14 +1280,6 @@ choice
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Say Y here if you want kernel low-level debugging support
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Say Y here if you want kernel low-level debugging support
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on Tegra based platforms.
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on Tegra based platforms.
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config DEBUG_U300_UART
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bool "Kernel low-level debugging messages via U300 UART0"
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depends on ARCH_U300
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select DEBUG_UART_PL01X
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help
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Say Y here if you want the debug print routines to direct
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their output to the uart port on U300 devices.
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config DEBUG_UX500_UART
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config DEBUG_UX500_UART
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depends on ARCH_U8500
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depends on ARCH_U8500
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bool "Use Ux500 UART for low-level debug"
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bool "Use Ux500 UART for low-level debug"
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@ -1650,7 +1642,6 @@ config DEBUG_UART_PHYS
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default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX
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default 0x808c0000 if DEBUG_EP93XX || ARCH_EP93XX
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default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
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default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
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default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
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default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
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default 0xc0013000 if DEBUG_U300_UART
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default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
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default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
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default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
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default 0xc8000003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
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default 0xd0000000 if DEBUG_SPEAR3XX
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default 0xd0000000 if DEBUG_SPEAR3XX
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@ -1804,7 +1795,6 @@ config DEBUG_UART_VIRT
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default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
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default 0xfefb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1
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default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
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default 0xfefb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2
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default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
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default 0xfefb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3
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default 0xff003000 if DEBUG_U300_UART
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default 0xffd01000 if DEBUG_HIP01_UART
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default 0xffd01000 if DEBUG_HIP01_UART
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default DEBUG_UART_PHYS if !MMU
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default DEBUG_UART_PHYS if !MMU
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depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
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depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
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machine-$(CONFIG_ARCH_STM32) += stm32
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machine-$(CONFIG_ARCH_STM32) += stm32
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machine-$(CONFIG_ARCH_SUNXI) += sunxi
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machine-$(CONFIG_ARCH_SUNXI) += sunxi
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machine-$(CONFIG_ARCH_TEGRA) += tegra
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machine-$(CONFIG_ARCH_TEGRA) += tegra
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machine-$(CONFIG_ARCH_U300) += u300
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machine-$(CONFIG_ARCH_U8500) += ux500
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machine-$(CONFIG_ARCH_U8500) += ux500
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machine-$(CONFIG_ARCH_VERSATILE) += versatile
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machine-$(CONFIG_ARCH_VERSATILE) += versatile
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machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
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machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
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@ -1255,8 +1255,6 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
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tegra124-nyan-big.dtb \
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tegra124-nyan-big.dtb \
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tegra124-nyan-blaze.dtb \
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tegra124-nyan-blaze.dtb \
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tegra124-venice2.dtb
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tegra124-venice2.dtb
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dtb-$(CONFIG_ARCH_U300) += \
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ste-u300.dtb
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dtb-$(CONFIG_ARCH_U8500) += \
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dtb-$(CONFIG_ARCH_U8500) += \
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ste-snowball.dtb \
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ste-snowball.dtb \
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ste-hrefprev60-stuib.dtb \
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ste-hrefprev60-stuib.dtb \
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@ -1,464 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree for the ST-Ericsson U300 Machine and SoC
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*/
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/dts-v1/;
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/ {
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model = "ST-Ericsson U300";
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compatible = "stericsson,u300";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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memory {
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device_type = "memory";
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reg = <0x48000000 0x03c00000>;
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};
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s365 {
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compatible = "stericsson,s365";
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vana15-supply = <&ab3100_ldo_d_reg>;
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syscon = <&syscon>;
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};
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syscon: syscon@c0011000 {
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compatible = "stericsson,u300-syscon", "syscon";
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reg = <0xc0011000 0x1000>;
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clk32: app_32_clk@32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll13: pll13@13M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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/* Slow bridge clocks under PLL13 */
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slow_clk: slow_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <0>;
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clocks = <&pll13>;
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};
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uart0_clk: uart0_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <1>;
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clocks = <&slow_clk>;
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};
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gpio_clk: gpio_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <4>;
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clocks = <&slow_clk>;
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};
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rtc_clk: rtc_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <6>;
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clocks = <&slow_clk>;
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};
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apptimer_clk: app_tmr_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <7>;
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clocks = <&slow_clk>;
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};
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acc_tmr_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <8>;
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clocks = <&slow_clk>;
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};
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pll208: pll208@208M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <208000000>;
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};
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app208: app_208_clk@208M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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cpu_clk@208M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <3>;
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clocks = <&app208>;
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};
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app104: app_104_clk@104M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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semi_clk@104M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <9>;
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clocks = <&app104>;
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};
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app52: app_52_clk@52M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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/* AHB subsystem clocks */
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ahb_clk: ahb_subsys_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <10>;
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clocks = <&app52>;
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};
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intcon_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <12>;
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clocks = <&ahb_clk>;
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};
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emif_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <5>;
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clocks = <&ahb_clk>;
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};
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dmac_clk: dmac_clk@52M {
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|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <2>; /* Rest */
|
|
||||||
clock-id = <4>;
|
|
||||||
clocks = <&app52>;
|
|
||||||
};
|
|
||||||
fsmc_clk: fsmc_clk@52M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <2>; /* Rest */
|
|
||||||
clock-id = <6>;
|
|
||||||
clocks = <&app52>;
|
|
||||||
};
|
|
||||||
xgam_clk: xgam_clk@52M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <2>; /* Rest */
|
|
||||||
clock-id = <8>;
|
|
||||||
clocks = <&app52>;
|
|
||||||
};
|
|
||||||
app26: app_26_clk@26M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "fixed-factor-clock";
|
|
||||||
clock-div = <2>;
|
|
||||||
clock-mult = <1>;
|
|
||||||
clocks = <&app52>;
|
|
||||||
};
|
|
||||||
/* Fast bridge clocks */
|
|
||||||
fast_clk: fast_clk@26M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <1>; /* Fast */
|
|
||||||
clock-id = <0>;
|
|
||||||
clocks = <&app26>;
|
|
||||||
};
|
|
||||||
i2c0_clk: i2c0_clk@26M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <1>; /* Fast */
|
|
||||||
clock-id = <1>;
|
|
||||||
clocks = <&fast_clk>;
|
|
||||||
};
|
|
||||||
i2c1_clk: i2c1_clk@26M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <1>; /* Fast */
|
|
||||||
clock-id = <2>;
|
|
||||||
clocks = <&fast_clk>;
|
|
||||||
};
|
|
||||||
mmc_pclk: mmc_p_clk@26M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <1>; /* Fast */
|
|
||||||
clock-id = <5>;
|
|
||||||
clocks = <&fast_clk>;
|
|
||||||
};
|
|
||||||
mmc_mclk: mmc_mclk {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-mclk";
|
|
||||||
clocks = <&mmc_pclk>;
|
|
||||||
};
|
|
||||||
spi_clk: spi_p_clk@26M {
|
|
||||||
#clock-cells = <0>;
|
|
||||||
compatible = "stericsson,u300-syscon-clk";
|
|
||||||
clock-type = <1>; /* Fast */
|
|
||||||
clock-id = <6>;
|
|
||||||
clocks = <&fast_clk>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
timer: timer@c0014000 {
|
|
||||||
compatible = "stericsson,u300-apptimer";
|
|
||||||
reg = <0xc0014000 0x1000>;
|
|
||||||
interrupt-parent = <&vica>;
|
|
||||||
interrupts = <24 25 26 27>;
|
|
||||||
clocks = <&apptimer_clk>;
|
|
||||||
};
|
|
||||||
|
|
||||||
gpio: gpio@c0016000 {
|
|
||||||
compatible = "stericsson,gpio-coh901";
|
|
||||||
reg = <0xc0016000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <0 1 2 18 21 22 23>;
|
|
||||||
clocks = <&gpio_clk>;
|
|
||||||
interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
|
|
||||||
"gpio4", "gpio5", "gpio6";
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <2>;
|
|
||||||
gpio-controller;
|
|
||||||
#gpio-cells = <2>;
|
|
||||||
};
|
|
||||||
|
|
||||||
pinctrl: pinctrl@c0011000 {
|
|
||||||
compatible = "stericsson,pinctrl-u300";
|
|
||||||
reg = <0xc0011000 0x1000>;
|
|
||||||
};
|
|
||||||
|
|
||||||
watchdog: watchdog@c0012000 {
|
|
||||||
compatible = "stericsson,coh901327";
|
|
||||||
reg = <0xc0012000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <3>;
|
|
||||||
clocks = <&clk32>;
|
|
||||||
};
|
|
||||||
|
|
||||||
rtc: rtc@c0017000 {
|
|
||||||
compatible = "stericsson,coh901331";
|
|
||||||
reg = <0xc0017000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <10>;
|
|
||||||
clocks = <&rtc_clk>;
|
|
||||||
};
|
|
||||||
|
|
||||||
dmac: dma-controller@c00020000 {
|
|
||||||
compatible = "stericsson,coh901318";
|
|
||||||
reg = <0xc0020000 0x1000>;
|
|
||||||
interrupt-parent = <&vica>;
|
|
||||||
interrupts = <2>;
|
|
||||||
#dma-cells = <1>;
|
|
||||||
dma-channels = <40>;
|
|
||||||
clocks = <&dmac_clk>;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* A NAND flash of 128 MiB */
|
|
||||||
fsmc: flash@40000000 {
|
|
||||||
compatible = "stericsson,fsmc-nand";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
reg = <0x9f800000 0x1000>, /* FSMC Register*/
|
|
||||||
<0x80000000 0x4000>, /* NAND Base DATA */
|
|
||||||
<0x80020000 0x4000>, /* NAND Base ADDR */
|
|
||||||
<0x80010000 0x4000>; /* NAND Base CMD */
|
|
||||||
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
|
|
||||||
nand-skip-bbtscan;
|
|
||||||
clocks = <&fsmc_clk>;
|
|
||||||
|
|
||||||
partition@0 {
|
|
||||||
label = "boot records";
|
|
||||||
reg = <0x0 0x20000>;
|
|
||||||
};
|
|
||||||
partition@20000 {
|
|
||||||
label = "free";
|
|
||||||
reg = <0x20000 0x7e0000>;
|
|
||||||
};
|
|
||||||
partition@800000 {
|
|
||||||
label = "platform";
|
|
||||||
reg = <0x800000 0xf800000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c0: i2c@c0004000 {
|
|
||||||
compatible = "st,ddci2c";
|
|
||||||
reg = <0xc0004000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <8>;
|
|
||||||
clocks = <&i2c0_clk>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
ab3100: ab3100@48 {
|
|
||||||
compatible = "stericsson,ab3100";
|
|
||||||
reg = <0x48>;
|
|
||||||
interrupt-parent = <&vica>;
|
|
||||||
interrupts = <0>; /* EXT0 IRQ */
|
|
||||||
ab3100-regulators {
|
|
||||||
compatible = "stericsson,ab3100-regulators";
|
|
||||||
ab3100_ldo_a_reg: ab3100_ldo_a {
|
|
||||||
startup-delay-us = <200>;
|
|
||||||
regulator-always-on;
|
|
||||||
regulator-boot-on;
|
|
||||||
};
|
|
||||||
ab3100_ldo_c_reg: ab3100_ldo_c {
|
|
||||||
startup-delay-us = <200>;
|
|
||||||
};
|
|
||||||
ab3100_ldo_d_reg: ab3100_ldo_d {
|
|
||||||
startup-delay-us = <200>;
|
|
||||||
};
|
|
||||||
ab3100_ldo_e_reg: ab3100_ldo_e {
|
|
||||||
regulator-min-microvolt = <1800000>;
|
|
||||||
regulator-max-microvolt = <1800000>;
|
|
||||||
startup-delay-us = <200>;
|
|
||||||
regulator-always-on;
|
|
||||||
regulator-boot-on;
|
|
||||||
};
|
|
||||||
ab3100_ldo_f_reg: ab3100_ldo_f {
|
|
||||||
regulator-min-microvolt = <2500000>;
|
|
||||||
regulator-max-microvolt = <2500000>;
|
|
||||||
startup-delay-us = <600>;
|
|
||||||
regulator-always-on;
|
|
||||||
regulator-boot-on;
|
|
||||||
};
|
|
||||||
ab3100_ldo_g_reg: ab3100_ldo_g {
|
|
||||||
regulator-min-microvolt = <1500000>;
|
|
||||||
regulator-max-microvolt = <2850000>;
|
|
||||||
startup-delay-us = <400>;
|
|
||||||
};
|
|
||||||
ab3100_ldo_h_reg: ab3100_ldo_h {
|
|
||||||
regulator-min-microvolt = <1200000>;
|
|
||||||
regulator-max-microvolt = <2750000>;
|
|
||||||
startup-delay-us = <200>;
|
|
||||||
};
|
|
||||||
ab3100_ldo_k_reg: ab3100_ldo_k {
|
|
||||||
regulator-min-microvolt = <1800000>;
|
|
||||||
regulator-max-microvolt = <2750000>;
|
|
||||||
startup-delay-us = <200>;
|
|
||||||
};
|
|
||||||
ab3100_ext_reg: ab3100_ext {
|
|
||||||
};
|
|
||||||
ab3100_buck_reg: ab3100_buck {
|
|
||||||
regulator-min-microvolt = <1200000>;
|
|
||||||
regulator-max-microvolt = <1800000>;
|
|
||||||
startup-delay-us = <1000>;
|
|
||||||
regulator-always-on;
|
|
||||||
regulator-boot-on;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
i2c1: i2c@c0005000 {
|
|
||||||
compatible = "st,ddci2c";
|
|
||||||
reg = <0xc0005000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <9>;
|
|
||||||
clocks = <&i2c1_clk>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
fwcam0: fwcam@10 {
|
|
||||||
reg = <0x10>;
|
|
||||||
};
|
|
||||||
fwcam1: fwcam@5d {
|
|
||||||
reg = <0x5d>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
||||||
amba {
|
|
||||||
compatible = "simple-bus";
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
ranges;
|
|
||||||
|
|
||||||
vica: interrupt-controller@a0001000 {
|
|
||||||
compatible = "arm,versatile-vic";
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
reg = <0xa0001000 0x20>;
|
|
||||||
};
|
|
||||||
|
|
||||||
vicb: interrupt-controller@a0002000 {
|
|
||||||
compatible = "arm,versatile-vic";
|
|
||||||
interrupt-controller;
|
|
||||||
#interrupt-cells = <1>;
|
|
||||||
reg = <0xa0002000 0x20>;
|
|
||||||
};
|
|
||||||
|
|
||||||
uart0: serial@c0013000 {
|
|
||||||
compatible = "arm,pl011", "arm,primecell";
|
|
||||||
reg = <0xc0013000 0x1000>;
|
|
||||||
interrupt-parent = <&vica>;
|
|
||||||
interrupts = <22>;
|
|
||||||
clocks = <&uart0_clk>, <&uart0_clk>;
|
|
||||||
clock-names = "apb_pclk", "uart0_clk";
|
|
||||||
dmas = <&dmac 17 &dmac 18>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
};
|
|
||||||
|
|
||||||
uart1: serial@c0007000 {
|
|
||||||
compatible = "arm,pl011", "arm,primecell";
|
|
||||||
reg = <0xc0007000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <20>;
|
|
||||||
dmas = <&dmac 38 &dmac 39>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
};
|
|
||||||
|
|
||||||
mmcsd: mmcsd@c0001000 {
|
|
||||||
compatible = "arm,pl18x", "arm,primecell";
|
|
||||||
reg = <0xc0001000 0x1000>;
|
|
||||||
interrupt-parent = <&vicb>;
|
|
||||||
interrupts = <6 7>;
|
|
||||||
clocks = <&mmc_pclk>, <&mmc_mclk>;
|
|
||||||
clock-names = "apb_pclk", "mclk";
|
|
||||||
max-frequency = <24000000>;
|
|
||||||
bus-width = <4>; // SD-card slot
|
|
||||||
cap-mmc-highspeed;
|
|
||||||
cap-sd-highspeed;
|
|
||||||
cd-gpios = <&gpio 12 0x4>;
|
|
||||||
cd-inverted;
|
|
||||||
vmmc-supply = <&ab3100_ldo_g_reg>;
|
|
||||||
dmas = <&dmac 14>;
|
|
||||||
dma-names = "rx";
|
|
||||||
};
|
|
||||||
|
|
||||||
spi: spi@c0006000 {
|
|
||||||
compatible = "arm,pl022", "arm,primecell";
|
|
||||||
reg = <0xc0006000 0x1000>;
|
|
||||||
interrupt-parent = <&vica>;
|
|
||||||
interrupts = <23>;
|
|
||||||
clocks = <&spi_clk>, <&spi_clk>;
|
|
||||||
clock-names = "SSPCLK", "apb_pclk";
|
|
||||||
dmas = <&dmac 27 &dmac 28>;
|
|
||||||
dma-names = "tx", "rx";
|
|
||||||
num-cs = <3>;
|
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <0>;
|
|
||||||
spi-dummy@1 {
|
|
||||||
compatible = "arm,pl022-dummy";
|
|
||||||
reg = <1>;
|
|
||||||
spi-max-frequency = <20000000>;
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|
@ -1,65 +0,0 @@
|
||||||
# CONFIG_LOCALVERSION_AUTO is not set
|
|
||||||
# CONFIG_SWAP is not set
|
|
||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_NO_HZ=y
|
|
||||||
CONFIG_HIGH_RES_TIMERS=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=14
|
|
||||||
CONFIG_EXPERT=y
|
|
||||||
# CONFIG_AIO is not set
|
|
||||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
|
||||||
CONFIG_MODULES=y
|
|
||||||
CONFIG_MODULE_UNLOAD=y
|
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
|
||||||
CONFIG_PARTITION_ADVANCED=y
|
|
||||||
# CONFIG_ARCH_MULTI_V7 is not set
|
|
||||||
CONFIG_ARCH_U300=y
|
|
||||||
CONFIG_MACH_U300_SPIDUMMY=y
|
|
||||||
CONFIG_PREEMPT=y
|
|
||||||
CONFIG_AEABI=y
|
|
||||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
|
||||||
CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
|
|
||||||
CONFIG_CPU_IDLE=y
|
|
||||||
# CONFIG_SUSPEND is not set
|
|
||||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_CMDLINE_PARTS=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_MTD_NAND_FSMC=y
|
|
||||||
# CONFIG_INPUT_MOUSEDEV is not set
|
|
||||||
CONFIG_INPUT_EVDEV=y
|
|
||||||
# CONFIG_KEYBOARD_ATKBD is not set
|
|
||||||
# CONFIG_INPUT_MOUSE is not set
|
|
||||||
# CONFIG_SERIO is not set
|
|
||||||
CONFIG_LEGACY_PTY_COUNT=16
|
|
||||||
CONFIG_SERIAL_AMBA_PL011=y
|
|
||||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
|
||||||
# CONFIG_HW_RANDOM is not set
|
|
||||||
CONFIG_I2C=y
|
|
||||||
# CONFIG_HWMON is not set
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_REGULATOR=y
|
|
||||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
||||||
CONFIG_FB=y
|
|
||||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
|
||||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
|
||||||
# CONFIG_USB_SUPPORT is not set
|
|
||||||
CONFIG_MMC=y
|
|
||||||
CONFIG_MMC_ARMMMCI=y
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
# CONFIG_RTC_HCTOSYS is not set
|
|
||||||
CONFIG_RTC_DRV_COH901331=y
|
|
||||||
CONFIG_DMADEVICES=y
|
|
||||||
CONFIG_COH901318=y
|
|
||||||
# CONFIG_DNOTIFY is not set
|
|
||||||
CONFIG_FUSE_FS=y
|
|
||||||
CONFIG_VFAT_FS=y
|
|
||||||
CONFIG_TMPFS=y
|
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
|
||||||
CONFIG_NLS_ISO8859_1=y
|
|
||||||
CONFIG_PRINTK_TIME=y
|
|
||||||
CONFIG_DEBUG_INFO=y
|
|
||||||
CONFIG_DEBUG_FS=y
|
|
||||||
# CONFIG_SCHED_DEBUG is not set
|
|
||||||
CONFIG_TIMER_STATS=y
|
|
||||||
# CONFIG_DEBUG_PREEMPT is not set
|
|
||||||
|
|
@ -1,32 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0
|
|
||||||
menuconfig ARCH_U300
|
|
||||||
bool "ST-Ericsson U300 Series"
|
|
||||||
depends on ARCH_MULTI_V5 && MMU
|
|
||||||
select ARM_AMBA
|
|
||||||
select ARM_VIC
|
|
||||||
select U300_TIMER
|
|
||||||
select CPU_ARM926T
|
|
||||||
select GPIOLIB
|
|
||||||
select HAVE_TCM
|
|
||||||
select PINCTRL
|
|
||||||
select PINCTRL_COH901
|
|
||||||
select PINCTRL_U300
|
|
||||||
select MFD_SYSCON
|
|
||||||
help
|
|
||||||
Support for ST-Ericsson U300 series mobile platforms.
|
|
||||||
|
|
||||||
if ARCH_U300
|
|
||||||
|
|
||||||
config MACH_U300
|
|
||||||
depends on ARCH_U300
|
|
||||||
bool "U300"
|
|
||||||
default y
|
|
||||||
|
|
||||||
config U300_DEBUG
|
|
||||||
depends on ARCH_U300
|
|
||||||
bool "Debug support for U300"
|
|
||||||
depends on PM
|
|
||||||
help
|
|
||||||
Debug support for U300 in sysfs, procfs etc.
|
|
||||||
|
|
||||||
endif
|
|
||||||
|
|
@ -1,8 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0-only
|
|
||||||
#
|
|
||||||
# Makefile for the linux kernel, U300 machine.
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y := core.o
|
|
||||||
|
|
||||||
obj-$(CONFIG_REGULATOR_AB3100) += regulator.o
|
|
||||||
|
|
@ -1,413 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0-only
|
|
||||||
/*
|
|
||||||
*
|
|
||||||
* arch/arm/mach-u300/core.c
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2012 ST-Ericsson SA
|
|
||||||
* Core platform support, IRQ handling and device definitions.
|
|
||||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
|
||||||
*/
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/pinctrl/machine.h>
|
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
|
||||||
#include <linux/platform_data/clk-u300.h>
|
|
||||||
#include <linux/irqchip.h>
|
|
||||||
#include <linux/of_address.h>
|
|
||||||
#include <linux/of_platform.h>
|
|
||||||
#include <linux/clocksource.h>
|
|
||||||
#include <linux/clk.h>
|
|
||||||
|
|
||||||
#include <asm/mach/map.h>
|
|
||||||
#include <asm/mach/arch.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These are the large blocks of memory allocated for I/O.
|
|
||||||
* the defines are used for setting up the I/O memory mapping.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* NAND Flash CS0 */
|
|
||||||
#define U300_NAND_CS0_PHYS_BASE 0x80000000
|
|
||||||
/* NFIF */
|
|
||||||
#define U300_NAND_IF_PHYS_BASE 0x9f800000
|
|
||||||
/* ALE, CLE offset for FSMC NAND */
|
|
||||||
#define PLAT_NAND_CLE (1 << 16)
|
|
||||||
#define PLAT_NAND_ALE (1 << 17)
|
|
||||||
/* AHB Peripherals */
|
|
||||||
#define U300_AHB_PER_PHYS_BASE 0xa0000000
|
|
||||||
#define U300_AHB_PER_VIRT_BASE 0xff010000
|
|
||||||
/* FAST Peripherals */
|
|
||||||
#define U300_FAST_PER_PHYS_BASE 0xc0000000
|
|
||||||
#define U300_FAST_PER_VIRT_BASE 0xff020000
|
|
||||||
/* SLOW Peripherals */
|
|
||||||
#define U300_SLOW_PER_PHYS_BASE 0xc0010000
|
|
||||||
#define U300_SLOW_PER_VIRT_BASE 0xff000000
|
|
||||||
/* Boot ROM */
|
|
||||||
#define U300_BOOTROM_PHYS_BASE 0xffff0000
|
|
||||||
#define U300_BOOTROM_VIRT_BASE 0xffff0000
|
|
||||||
/* SEMI config base */
|
|
||||||
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* AHB peripherals
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* AHB Peripherals Bridge Controller */
|
|
||||||
#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
|
|
||||||
/* Vectored Interrupt Controller 0, servicing 32 interrupts */
|
|
||||||
#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
|
|
||||||
#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
|
|
||||||
/* Vectored Interrupt Controller 1, servicing 32 interrupts */
|
|
||||||
#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
|
|
||||||
#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
|
|
||||||
/* Memory Stick Pro (MSPRO) controller */
|
|
||||||
#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
|
|
||||||
/* EMIF Configuration Area */
|
|
||||||
#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FAST peripherals
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* FAST bridge control */
|
|
||||||
#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
|
|
||||||
/* MMC/SD controller */
|
|
||||||
#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
|
|
||||||
/* PCM I2S0 controller */
|
|
||||||
#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
|
|
||||||
/* PCM I2S1 controller */
|
|
||||||
#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
|
|
||||||
/* I2C0 controller */
|
|
||||||
#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
|
|
||||||
/* I2C1 controller */
|
|
||||||
#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
|
|
||||||
/* SPI controller */
|
|
||||||
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
|
|
||||||
/* Fast UART1 on U335 only */
|
|
||||||
#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SLOW peripherals
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* SLOW bridge control */
|
|
||||||
#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
|
|
||||||
/* SYSCON */
|
|
||||||
#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
|
|
||||||
#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
|
|
||||||
/* Watchdog */
|
|
||||||
#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
|
|
||||||
/* UART0 */
|
|
||||||
#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
|
|
||||||
/* APP side special timer */
|
|
||||||
#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
|
|
||||||
#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
|
|
||||||
/* Keypad */
|
|
||||||
#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
|
|
||||||
/* GPIO */
|
|
||||||
#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
|
|
||||||
/* RTC */
|
|
||||||
#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
|
|
||||||
/* Bus tracer */
|
|
||||||
#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
|
|
||||||
/* Event handler (hardware queue) */
|
|
||||||
#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
|
|
||||||
/* Genric Timer */
|
|
||||||
#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
|
|
||||||
/* PPM */
|
|
||||||
#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* REST peripherals
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* ISP (image signal processor) */
|
|
||||||
#define U300_ISP_BASE (0xA0008000)
|
|
||||||
/* DMA Controller base */
|
|
||||||
#define U300_DMAC_BASE (0xC0020000)
|
|
||||||
/* MSL Base */
|
|
||||||
#define U300_MSL_BASE (0xc0022000)
|
|
||||||
/* APEX Base */
|
|
||||||
#define U300_APEX_BASE (0xc0030000)
|
|
||||||
/* Video Encoder Base */
|
|
||||||
#define U300_VIDEOENC_BASE (0xc0080000)
|
|
||||||
/* XGAM Base */
|
|
||||||
#define U300_XGAM_BASE (0xd0000000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SYSCON addresses applicable to the core machine.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Chip ID register 16bit (R/-) */
|
|
||||||
#define U300_SYSCON_CIDR (0x400)
|
|
||||||
/* SMCR */
|
|
||||||
#define U300_SYSCON_SMCR (0x4d0)
|
|
||||||
#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
|
|
||||||
#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
|
|
||||||
#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
|
|
||||||
#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
|
|
||||||
/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
|
|
||||||
#define U300_SYSCON_CSDR (0x4f0)
|
|
||||||
#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
|
|
||||||
/* PRINT_CONTROL Print Control 16bit (R/-) */
|
|
||||||
#define U300_SYSCON_PCR (0x4f8)
|
|
||||||
#define U300_SYSCON_PCR_SERV_IND (0x0001)
|
|
||||||
/* BOOT_CONTROL 16bit (R/-) */
|
|
||||||
#define U300_SYSCON_BCR (0x4fc)
|
|
||||||
#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
|
|
||||||
#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
|
|
||||||
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
|
|
||||||
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
|
|
||||||
|
|
||||||
static void __iomem *syscon_base;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Static I/O mappings that are needed for booting the U300 platforms. The
|
|
||||||
* only things we need are the areas where we find the timer, syscon and
|
|
||||||
* intcon, since the remaining device drivers will map their own memory
|
|
||||||
* physical to virtual as the need arise.
|
|
||||||
*/
|
|
||||||
static struct map_desc u300_io_desc[] __initdata = {
|
|
||||||
{
|
|
||||||
.virtual = U300_SLOW_PER_VIRT_BASE,
|
|
||||||
.pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
|
|
||||||
.length = SZ_64K,
|
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.virtual = U300_AHB_PER_VIRT_BASE,
|
|
||||||
.pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
|
|
||||||
.length = SZ_32K,
|
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.virtual = U300_FAST_PER_VIRT_BASE,
|
|
||||||
.pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
|
|
||||||
.length = SZ_32K,
|
|
||||||
.type = MT_DEVICE,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init u300_map_io(void)
|
|
||||||
{
|
|
||||||
iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
|
|
||||||
}
|
|
||||||
|
|
||||||
static unsigned long pin_pullup_conf[] = {
|
|
||||||
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned long pin_highz_conf[] = {
|
|
||||||
PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
|
|
||||||
};
|
|
||||||
|
|
||||||
/* Pin control settings */
|
|
||||||
static const struct pinctrl_map u300_pinmux_map[] = {
|
|
||||||
/* anonymous maps for chip power and EMIFs */
|
|
||||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
|
|
||||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
|
|
||||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
|
|
||||||
/* per-device maps for MMC/SD, SPI and UART */
|
|
||||||
PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
|
|
||||||
PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
|
|
||||||
PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
|
|
||||||
/* This pin is used for clock return rather than GPIO */
|
|
||||||
PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
|
|
||||||
pin_pullup_conf),
|
|
||||||
/* This pin is used for card detect */
|
|
||||||
PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
|
|
||||||
pin_highz_conf),
|
|
||||||
};
|
|
||||||
|
|
||||||
struct db_chip {
|
|
||||||
u16 chipid;
|
|
||||||
const char *name;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This is a list of the Digital Baseband chips used in the U300 platform.
|
|
||||||
*/
|
|
||||||
static struct db_chip db_chips[] __initdata = {
|
|
||||||
{
|
|
||||||
.chipid = 0xb800,
|
|
||||||
.name = "DB3000",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xc000,
|
|
||||||
.name = "DB3100",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xc800,
|
|
||||||
.name = "DB3150",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xd800,
|
|
||||||
.name = "DB3200",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xe000,
|
|
||||||
.name = "DB3250",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xe800,
|
|
||||||
.name = "DB3210",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xf000,
|
|
||||||
.name = "DB3350 P1x",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0xf100,
|
|
||||||
.name = "DB3350 P2x",
|
|
||||||
},
|
|
||||||
{
|
|
||||||
.chipid = 0x0000, /* List terminator */
|
|
||||||
.name = NULL,
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init u300_init_check_chip(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
u16 val;
|
|
||||||
struct db_chip *chip;
|
|
||||||
const char *chipname;
|
|
||||||
const char unknown[] = "UNKNOWN";
|
|
||||||
|
|
||||||
/* Read out and print chip ID */
|
|
||||||
val = readw(syscon_base + U300_SYSCON_CIDR);
|
|
||||||
/* This is in funky bigendian order... */
|
|
||||||
val = (val & 0xFFU) << 8 | (val >> 8);
|
|
||||||
chip = db_chips;
|
|
||||||
chipname = unknown;
|
|
||||||
|
|
||||||
for ( ; chip->chipid; chip++) {
|
|
||||||
if (chip->chipid == (val & 0xFF00U)) {
|
|
||||||
chipname = chip->name;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
|
|
||||||
"(chip ID 0x%04x)\n", chipname, val);
|
|
||||||
|
|
||||||
if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
|
|
||||||
printk(KERN_ERR "Platform configured for BS335 " \
|
|
||||||
" with DB3350 but %s detected, expect problems!",
|
|
||||||
chipname);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Forward declare this function from the watchdog */
|
|
||||||
void coh901327_watchdog_reset(void);
|
|
||||||
|
|
||||||
static void u300_restart(enum reboot_mode mode, const char *cmd)
|
|
||||||
{
|
|
||||||
switch (mode) {
|
|
||||||
case REBOOT_SOFT:
|
|
||||||
case REBOOT_HARD:
|
|
||||||
#ifdef CONFIG_COH901327_WATCHDOG
|
|
||||||
coh901327_watchdog_reset();
|
|
||||||
#endif
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
/* Do nothing */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
/* Wait for system do die/reset. */
|
|
||||||
while (1);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* These are mostly to get the right device names for the clock lookups */
|
|
||||||
static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
|
|
||||||
OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
|
|
||||||
"pinctrl-u300", NULL),
|
|
||||||
OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
|
|
||||||
"u300-gpio", NULL),
|
|
||||||
OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
|
|
||||||
"coh901327_wdog", NULL),
|
|
||||||
OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
|
|
||||||
"rtc-coh901331", NULL),
|
|
||||||
OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
|
|
||||||
"coh901318", NULL),
|
|
||||||
OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
|
|
||||||
"fsmc-nand", NULL),
|
|
||||||
OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
|
|
||||||
"uart0", NULL),
|
|
||||||
OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
|
|
||||||
"uart1", NULL),
|
|
||||||
OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
|
|
||||||
"pl022", NULL),
|
|
||||||
OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
|
|
||||||
"stu300.0", NULL),
|
|
||||||
OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
|
|
||||||
"stu300.1", NULL),
|
|
||||||
OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
|
|
||||||
"mmci", NULL),
|
|
||||||
{ /* sentinel */ },
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init u300_init_irq_dt(void)
|
|
||||||
{
|
|
||||||
struct device_node *syscon;
|
|
||||||
struct clk *clk;
|
|
||||||
|
|
||||||
syscon = of_find_node_by_path("/syscon@c0011000");
|
|
||||||
if (!syscon) {
|
|
||||||
pr_crit("could not find syscon node\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
syscon_base = of_iomap(syscon, 0);
|
|
||||||
if (!syscon_base) {
|
|
||||||
pr_crit("could not remap syscon\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
/* initialize clocking early, we want to clock the INTCON */
|
|
||||||
u300_clk_init(syscon_base);
|
|
||||||
|
|
||||||
/* Bootstrap EMIF and SEMI clocks */
|
|
||||||
clk = clk_get_sys("pl172", NULL);
|
|
||||||
BUG_ON(IS_ERR(clk));
|
|
||||||
clk_prepare_enable(clk);
|
|
||||||
clk = clk_get_sys("semi", NULL);
|
|
||||||
BUG_ON(IS_ERR(clk));
|
|
||||||
clk_prepare_enable(clk);
|
|
||||||
|
|
||||||
/* Clock the interrupt controller */
|
|
||||||
clk = clk_get_sys("intcon", NULL);
|
|
||||||
BUG_ON(IS_ERR(clk));
|
|
||||||
clk_prepare_enable(clk);
|
|
||||||
|
|
||||||
irqchip_init();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void __init u300_init_machine_dt(void)
|
|
||||||
{
|
|
||||||
u16 val;
|
|
||||||
|
|
||||||
/* Check what platform we run and print some status information */
|
|
||||||
u300_init_check_chip();
|
|
||||||
|
|
||||||
/* Initialize pinmuxing */
|
|
||||||
pinctrl_register_mappings(u300_pinmux_map,
|
|
||||||
ARRAY_SIZE(u300_pinmux_map));
|
|
||||||
|
|
||||||
of_platform_default_populate(NULL, u300_auxdata_lookup, NULL);
|
|
||||||
|
|
||||||
/* Enable SEMI self refresh */
|
|
||||||
val = readw(syscon_base + U300_SYSCON_SMCR) |
|
|
||||||
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
|
|
||||||
writew(val, syscon_base + U300_SYSCON_SMCR);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const char * u300_board_compat[] = {
|
|
||||||
"stericsson,u300",
|
|
||||||
NULL,
|
|
||||||
};
|
|
||||||
|
|
||||||
DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
|
|
||||||
.map_io = u300_map_io,
|
|
||||||
.init_irq = u300_init_irq_dt,
|
|
||||||
.init_time = timer_probe,
|
|
||||||
.init_machine = u300_init_machine_dt,
|
|
||||||
.restart = u300_restart,
|
|
||||||
.dt_compat = u300_board_compat,
|
|
||||||
MACHINE_END
|
|
||||||
|
|
@ -1,134 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0-only
|
|
||||||
/*
|
|
||||||
* arch/arm/mach-u300/regulator.c
|
|
||||||
*
|
|
||||||
* Copyright (C) 2009 ST-Ericsson AB
|
|
||||||
* Handle board-bound regulators and board power not related
|
|
||||||
* to any devices.
|
|
||||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
|
||||||
*/
|
|
||||||
#include <linux/device.h>
|
|
||||||
#include <linux/signal.h>
|
|
||||||
#include <linux/err.h>
|
|
||||||
#include <linux/of.h>
|
|
||||||
#include <linux/module.h>
|
|
||||||
#include <linux/platform_device.h>
|
|
||||||
#include <linux/regulator/machine.h>
|
|
||||||
#include <linux/regulator/consumer.h>
|
|
||||||
#include <linux/mfd/syscon.h>
|
|
||||||
#include <linux/regmap.h>
|
|
||||||
|
|
||||||
/* Power Management Control 16bit (R/W) */
|
|
||||||
#define U300_SYSCON_PMCR (0x50)
|
|
||||||
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
|
|
||||||
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Regulators that power the board and chip and which are
|
|
||||||
* not copuled to specific drivers are hogged in these
|
|
||||||
* instances.
|
|
||||||
*/
|
|
||||||
static struct regulator *main_power_15;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function is used from pm.h to shut down the system by
|
|
||||||
* resetting all regulators in turn and then disable regulator
|
|
||||||
* LDO D (main power).
|
|
||||||
*/
|
|
||||||
void u300_pm_poweroff(void)
|
|
||||||
{
|
|
||||||
sigset_t old, all;
|
|
||||||
|
|
||||||
sigfillset(&all);
|
|
||||||
if (!sigprocmask(SIG_BLOCK, &all, &old)) {
|
|
||||||
/* Disable LDO D to shut down the system */
|
|
||||||
if (main_power_15)
|
|
||||||
regulator_disable(main_power_15);
|
|
||||||
else
|
|
||||||
pr_err("regulator not available to shut down system\n");
|
|
||||||
(void) sigprocmask(SIG_SETMASK, &old, NULL);
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Hog the regulators needed to power up the board.
|
|
||||||
*/
|
|
||||||
static int __init __u300_init_boardpower(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
struct device_node *np = pdev->dev.of_node;
|
|
||||||
struct device_node *syscon_np;
|
|
||||||
struct regmap *regmap;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
pr_info("U300: setting up board power\n");
|
|
||||||
|
|
||||||
syscon_np = of_parse_phandle(np, "syscon", 0);
|
|
||||||
if (!syscon_np) {
|
|
||||||
pr_crit("U300: no syscon node\n");
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
regmap = syscon_node_to_regmap(syscon_np);
|
|
||||||
if (IS_ERR(regmap)) {
|
|
||||||
pr_crit("U300: could not locate syscon regmap\n");
|
|
||||||
return PTR_ERR(regmap);
|
|
||||||
}
|
|
||||||
|
|
||||||
main_power_15 = regulator_get(&pdev->dev, "vana15");
|
|
||||||
|
|
||||||
if (IS_ERR(main_power_15)) {
|
|
||||||
pr_err("could not get vana15");
|
|
||||||
return PTR_ERR(main_power_15);
|
|
||||||
}
|
|
||||||
err = regulator_enable(main_power_15);
|
|
||||||
if (err) {
|
|
||||||
pr_err("could not enable vana15\n");
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* On U300 a special system controller register pulls up the DC
|
|
||||||
* until the vana15 (LDO D) regulator comes up. At this point, all
|
|
||||||
* regulators are set and we do not need power control via
|
|
||||||
* DC ON anymore. This function will likely be moved whenever
|
|
||||||
* the rest of the U300 power management is implemented.
|
|
||||||
*/
|
|
||||||
pr_info("U300: disable system controller pull-up\n");
|
|
||||||
regmap_update_bits(regmap, U300_SYSCON_PMCR,
|
|
||||||
U300_SYSCON_PMCR_DCON_ENABLE, 0);
|
|
||||||
|
|
||||||
/* Register globally exported PM poweroff hook */
|
|
||||||
pm_power_off = u300_pm_poweroff;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int __init s365_board_probe(struct platform_device *pdev)
|
|
||||||
{
|
|
||||||
return __u300_init_boardpower(pdev);
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct of_device_id s365_board_match[] = {
|
|
||||||
{ .compatible = "stericsson,s365" },
|
|
||||||
{},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct platform_driver s365_board_driver = {
|
|
||||||
.driver = {
|
|
||||||
.name = "s365-board",
|
|
||||||
.of_match_table = s365_board_match,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* So at module init time we hog the regulator!
|
|
||||||
*/
|
|
||||||
static int __init u300_init_boardpower(void)
|
|
||||||
{
|
|
||||||
return platform_driver_probe(&s365_board_driver,
|
|
||||||
s365_board_probe);
|
|
||||||
}
|
|
||||||
|
|
||||||
device_initcall(u300_init_boardpower);
|
|
||||||
MODULE_LICENSE("GPL v2");
|
|
||||||
MODULE_AUTHOR("Linus Walleij");
|
|
||||||
|
|
@ -331,8 +331,7 @@ source "drivers/mtd/nand/raw/ingenic/Kconfig"
|
||||||
config MTD_NAND_FSMC
|
config MTD_NAND_FSMC
|
||||||
tristate "ST Micros FSMC NAND controller"
|
tristate "ST Micros FSMC NAND controller"
|
||||||
depends on OF && HAS_IOMEM
|
depends on OF && HAS_IOMEM
|
||||||
depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 || \
|
depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || COMPILE_TEST
|
||||||
COMPILE_TEST
|
|
||||||
help
|
help
|
||||||
Enables support for NAND Flash chips on the ST Microelectronics
|
Enables support for NAND Flash chips on the ST Microelectronics
|
||||||
Flexible Static Memory Controller (FSMC)
|
Flexible Static Memory Controller (FSMC)
|
||||||
|
|
|
||||||
|
|
@ -601,7 +601,6 @@ config SPI_PIC32_SQI
|
||||||
config SPI_PL022
|
config SPI_PL022
|
||||||
tristate "ARM AMBA PL022 SSP controller"
|
tristate "ARM AMBA PL022 SSP controller"
|
||||||
depends on ARM_AMBA
|
depends on ARM_AMBA
|
||||||
default y if MACH_U300
|
|
||||||
default y if ARCH_REALVIEW
|
default y if ARCH_REALVIEW
|
||||||
default y if INTEGRATOR_IMPD1
|
default y if INTEGRATOR_IMPD1
|
||||||
default y if ARCH_VERSATILE
|
default y if ARCH_VERSATILE
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue