powerpc/512x: mark clocks as big endian
These clocks' registers are accessed as big endian, so mark them as such. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -239,6 +239,7 @@ static inline struct clk *mpc512x_clk_divider(
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const char *name, const char *parent_name, u8 clkflags,
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u32 __iomem *reg, u8 pos, u8 len, int divflags)
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{
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divflags |= CLK_DIVIDER_BIG_ENDIAN;
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return clk_register_divider(NULL, name, parent_name, clkflags,
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reg, pos, len, divflags, &clklock);
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}
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@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable(
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{
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u8 divflags;
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divflags = 0;
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divflags = CLK_DIVIDER_BIG_ENDIAN;
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return clk_register_divider_table(NULL, name, parent_name, 0,
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reg, pos, len, divflags,
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divtab, &clklock);
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@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated(
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u32 __iomem *reg, u8 pos)
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{
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int clkflags;
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u8 gateflags;
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clkflags = CLK_SET_RATE_PARENT;
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gateflags = CLK_GATE_BIG_ENDIAN;
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return clk_register_gate(NULL, name, parent_name, clkflags,
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reg, pos, 0, &clklock);
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reg, pos, gateflags, &clklock);
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}
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static inline struct clk *mpc512x_clk_muxed(const char *name,
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@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name,
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u8 muxflags;
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clkflags = CLK_SET_RATE_PARENT;
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muxflags = 0;
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muxflags = CLK_MUX_BIG_ENDIAN;
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return clk_register_mux(NULL, name,
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parent_names, parent_count, clkflags,
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reg, pos, len, muxflags, &clklock);
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