drivers/edac: Lindent r82600
Run r82600_edac.c file through Lindent for cleanup Signed-off-by: Douglas Thompson <dougthompson@xmission.com> Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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1111660109
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cddbfcacf0
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@ -133,8 +133,8 @@ struct r82600_error_info {
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static unsigned int disable_hardware_scrub = 0;
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static unsigned int disable_hardware_scrub = 0;
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static void r82600_get_error_info (struct mem_ctl_info *mci,
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static void r82600_get_error_info(struct mem_ctl_info *mci,
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struct r82600_error_info *info)
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struct r82600_error_info *info)
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{
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{
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struct pci_dev *pdev;
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struct pci_dev *pdev;
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@ -144,18 +144,19 @@ static void r82600_get_error_info (struct mem_ctl_info *mci,
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if (info->eapr & BIT(0))
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if (info->eapr & BIT(0))
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/* Clear error to allow next error to be reported [p.62] */
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/* Clear error to allow next error to be reported [p.62] */
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pci_write_bits32(pdev, R82600_EAP,
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pci_write_bits32(pdev, R82600_EAP,
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((u32) BIT(0) & (u32) BIT(1)),
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((u32) BIT(0) & (u32) BIT(1)),
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((u32) BIT(0) & (u32) BIT(1)));
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((u32) BIT(0) & (u32) BIT(1)));
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if (info->eapr & BIT(1))
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if (info->eapr & BIT(1))
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/* Clear error to allow next error to be reported [p.62] */
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/* Clear error to allow next error to be reported [p.62] */
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pci_write_bits32(pdev, R82600_EAP,
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pci_write_bits32(pdev, R82600_EAP,
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((u32) BIT(0) & (u32) BIT(1)),
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((u32) BIT(0) & (u32) BIT(1)),
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((u32) BIT(0) & (u32) BIT(1)));
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((u32) BIT(0) & (u32) BIT(1)));
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}
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}
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static int r82600_process_error_info (struct mem_ctl_info *mci,
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static int r82600_process_error_info(struct mem_ctl_info *mci,
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struct r82600_error_info *info, int handle_errors)
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struct r82600_error_info *info,
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int handle_errors)
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{
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{
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int error_found;
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int error_found;
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u32 eapaddr, page;
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u32 eapaddr, page;
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@ -172,25 +173,23 @@ static int r82600_process_error_info (struct mem_ctl_info *mci,
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* granularity (upper 19 bits only) */
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* granularity (upper 19 bits only) */
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page = eapaddr >> PAGE_SHIFT;
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page = eapaddr >> PAGE_SHIFT;
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if (info->eapr & BIT(0)) { /* CE? */
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if (info->eapr & BIT(0)) { /* CE? */
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error_found = 1;
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error_found = 1;
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if (handle_errors)
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if (handle_errors)
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edac_mc_handle_ce(mci, page, 0, /* not avail */
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edac_mc_handle_ce(mci, page, 0, /* not avail */
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syndrome,
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syndrome, edac_mc_find_csrow_by_page(mci, page), 0, /* channel */
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edac_mc_find_csrow_by_page(mci, page),
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mci->ctl_name);
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0, /* channel */
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mci->ctl_name);
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}
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}
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if (info->eapr & BIT(1)) { /* UE? */
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if (info->eapr & BIT(1)) { /* UE? */
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error_found = 1;
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error_found = 1;
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if (handle_errors)
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if (handle_errors)
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/* 82600 doesn't give enough info */
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/* 82600 doesn't give enough info */
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edac_mc_handle_ue(mci, page, 0,
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edac_mc_handle_ue(mci, page, 0,
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edac_mc_find_csrow_by_page(mci, page),
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edac_mc_find_csrow_by_page(mci, page),
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mci->ctl_name);
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mci->ctl_name);
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}
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}
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return error_found;
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return error_found;
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@ -211,11 +210,11 @@ static inline int ecc_enabled(u8 dramcr)
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}
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}
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static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
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static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
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u8 dramcr)
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u8 dramcr)
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{
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{
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struct csrow_info *csrow;
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struct csrow_info *csrow;
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int index;
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int index;
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u8 drbar; /* SDRAM Row Boundry Address Register */
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u8 drbar; /* SDRAM Row Boundry Address Register */
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u32 row_high_limit, row_high_limit_last;
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u32 row_high_limit, row_high_limit_last;
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u32 reg_sdram, ecc_on, row_base;
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u32 reg_sdram, ecc_on, row_base;
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@ -309,12 +308,12 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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mci->edac_check = r82600_check;
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mci->edac_check = r82600_check;
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mci->ctl_page_to_phys = NULL;
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mci->ctl_page_to_phys = NULL;
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r82600_init_csrows(mci, pdev, dramcr);
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r82600_init_csrows(mci, pdev, dramcr);
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r82600_get_error_info(mci, &discard); /* clear counters */
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r82600_get_error_info(mci, &discard); /* clear counters */
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/* Here we assume that we will never see multiple instances of this
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/* Here we assume that we will never see multiple instances of this
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* type of memory controller. The ID is therefore hardcoded to 0.
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* type of memory controller. The ID is therefore hardcoded to 0.
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*/
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*/
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if (edac_mc_add_mc(mci,0)) {
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if (edac_mc_add_mc(mci, 0)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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goto fail;
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goto fail;
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}
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}
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@ -330,14 +329,14 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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debugf3("%s(): success\n", __func__);
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debugf3("%s(): success\n", __func__);
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return 0;
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return 0;
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fail:
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fail:
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edac_mc_free(mci);
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edac_mc_free(mci);
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return -ENODEV;
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return -ENODEV;
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}
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}
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/* returns count (>= 0), or negative on error */
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/* returns count (>= 0), or negative on error */
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static int __devinit r82600_init_one(struct pci_dev *pdev,
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static int __devinit r82600_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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const struct pci_device_id *ent)
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{
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{
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debugf0("%s()\n", __func__);
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debugf0("%s()\n", __func__);
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@ -359,11 +358,11 @@ static void __devexit r82600_remove_one(struct pci_dev *pdev)
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static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
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static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
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{
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{
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PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
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PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
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},
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},
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{
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{
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0,
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0,
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} /* 0 terminated list. */
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} /* 0 terminated list. */
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};
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};
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MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
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MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
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@ -390,7 +389,7 @@ module_exit(r82600_exit);
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MODULE_LICENSE("GPL");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
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MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
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"on behalf of EADS Astrium");
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"on behalf of EADS Astrium");
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MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
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MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
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module_param(disable_hardware_scrub, bool, 0644);
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module_param(disable_hardware_scrub, bool, 0644);
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