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xtensa: add missing isync to the cpu_reset TLB code 

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2019-08-12 15:01:30 -07:00
parent d45331b00d
commit cd8869f4cb
1 changed files with 1 additions and 0 deletions
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arch/xtensa/kernel/setup.c
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@ -511,6 +511,7 @@ void cpu_reset(void)
"add %2, %2, %7\n\t" "add %2, %2, %7\n\t"
"addi %0, %0, -1\n\t" "addi %0, %0, -1\n\t"
"bnez %0, 1b\n\t" "bnez %0, 1b\n\t"
"isync\n\t"
/* Jump to identity mapping */ /* Jump to identity mapping */
"jx %3\n" "jx %3\n"
"2:\n\t" "2:\n\t"