Merge branch 'remotes/lorenzo/pci/qcom'
- Add Qualcomm PCIe Endpoint controller driver and DT binding (Manivannan Sadhasivam) - Add qcom struct for device-specific details in match data (Prasad Malisetty) - Switch pcie_1_pipe_clk_src from TCXO to pipe clock after PHY init in SC7280 (Prasad Malisetty) - Add .compatible device ID for SC8180x platform (Bjorn Andersson) * remotes/lorenzo/pci/qcom: PCI: qcom: Add sc8180x compatible PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 PCI: qcom: Replace ops with struct pcie_cfg in pcie match data MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller
This commit is contained in:
Bjorn Helgaas
commit
cd48bff78a
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@ -0,0 +1,158 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCIe Endpoint Controller binding
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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allOf:
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- $ref: "pci-ep.yaml#"
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properties:
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compatible:
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const: qcom,sdx55-pcie-ep
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reg:
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items:
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- description: Qualcomm-specific PARF configuration registers
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- description: DesignWare PCIe registers
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- description: External local bus interface registers
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- description: Address Translation Unit (ATU) registers
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- description: Memory region used to map remote RC address space
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- description: BAR memory region
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reg-names:
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: atu
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- const: addr_space
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- const: mmio
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clocks:
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items:
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- description: PCIe Auxiliary clock
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- description: PCIe CFG AHB clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe Slave Q2A AXI clock
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- description: PCIe Sleep clock
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- description: PCIe Reference clock
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clock-names:
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items:
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- const: aux
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- const: cfg
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- const: bus_master
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- const: bus_slave
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- const: slave_q2a
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- const: sleep
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- const: ref
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qcom,perst-regs:
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description: Reference to a syscon representing TCSR followed by the two
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offsets within syscon for Perst enable and Perst separation
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enable registers
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$ref: "/schemas/types.yaml#/definitions/phandle-array"
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items:
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minItems: 3
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maxItems: 3
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interrupts:
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items:
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- description: PCIe Global interrupt
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- description: PCIe Doorbell interrupt
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interrupt-names:
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items:
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- const: global
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- const: doorbell
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reset-gpios:
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description: GPIO used as PERST# input signal
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maxItems: 1
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wake-gpios:
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description: GPIO used as WAKE# output signal
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: core
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power-domains:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pciephy
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num-lanes:
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default: 2
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- qcom,perst-regs
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- interrupts
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- interrupt-names
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- reset-gpios
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- resets
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- reset-names
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_ep: pcie-ep@40000000 {
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compatible = "qcom,sdx55-pcie-ep";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xc8>,
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<0x40001000 0x1000>,
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<0x40002000 0x1000>,
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<0x01c03000 0x3000>;
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reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
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"mmio";
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clocks = <&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_CLK>;
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clock-names = "aux", "cfg", "bus_master", "bus_slave",
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"slave_q2a", "sleep", "ref";
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qcom,perst-regs = <&tcsr 0xb258 0xb270>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell";
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reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
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resets = <&gcc GCC_PCIE_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_GDSC>;
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phys = <&pcie0_lane>;
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phy-names = "pciephy";
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max-link-speed = <3>;
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num-lanes = <2>;
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};
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@ -12,6 +12,7 @@
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- "qcom,pcie-ipq4019" for ipq4019
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- "qcom,pcie-ipq8074" for ipq8074
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- "qcom,pcie-qcs404" for qcs404
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- "qcom,pcie-sc8180x" for sc8180x
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- "qcom,pcie-sdm845" for sdm845
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- "qcom,pcie-sm8250" for sm8250
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- "qcom,pcie-ipq6018" for ipq6018
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@ -156,7 +157,7 @@
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- "pipe" PIPE clock
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- clock-names:
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Usage: required for sm8250
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Usage: required for sc8180x and sm8250
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "aux" Auxiliary clock
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@ -245,7 +246,7 @@
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- "ahb" AHB reset
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- reset-names:
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Usage: required for sdm845 and sm8250
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Usage: required for sc8180x, sdm845 and sm8250
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Value type: <stringlist>
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Definition: Should contain the following entries
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- "pci" PCIe core reset
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|
|
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10
MAINTAINERS
10
MAINTAINERS
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@ -14618,7 +14618,15 @@ M: Stanimir Varbanov <svarbanov@mm-sol.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: drivers/pci/controller/dwc/*qcom*
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F: drivers/pci/controller/dwc/pcie-qcom.c
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PCIE ENDPOINT DRIVER FOR QUALCOMM
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M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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L: linux-pci@vger.kernel.org
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
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F: drivers/pci/controller/dwc/pcie-qcom-ep.c
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PCIE DRIVER FOR ROCKCHIP
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M: Shawn Lin <shawn.lin@rock-chips.com>
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@ -178,6 +178,16 @@ config PCIE_QCOM
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PCIe controller uses the DesignWare core plus Qualcomm-specific
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hardware wrappers.
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config PCIE_QCOM_EP
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tristate "Qualcomm PCIe controller - Endpoint mode"
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depends on OF && (ARCH_QCOM || COMPILE_TEST)
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Say Y here to enable support for the PCIe controllers on Qualcomm SoCs
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to work in endpoint mode. The PCIe controller uses the DesignWare core
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plus Qualcomm-specific hardware wrappers.
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config PCIE_ARMADA_8K
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bool "Marvell Armada-8K PCIe controller"
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depends on ARCH_MVEBU || COMPILE_TEST
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@ -12,6 +12,7 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o
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@ -486,6 +486,7 @@ int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq);
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int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
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u8 interrupt_num)
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@ -537,6 +538,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
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return 0;
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}
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EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msi_irq);
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int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
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u16 interrupt_num)
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@ -0,0 +1,721 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm PCIe Endpoint controller driver
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*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Author: Siddartha Mohanadoss <smohanad@codeaurora.org
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*
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* Copyright (c) 2021, Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/mfd/syscon.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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/* PARF registers */
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#define PARF_SYS_CTRL 0x00
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#define PARF_DB_CTRL 0x10
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#define PARF_PM_CTRL 0x20
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#define PARF_MHI_BASE_ADDR_LOWER 0x178
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#define PARF_MHI_BASE_ADDR_UPPER 0x17c
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#define PARF_DEBUG_INT_EN 0x190
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#define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
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#define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
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#define PARF_Q2A_FLUSH 0x1ac
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#define PARF_LTSSM 0x1b0
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#define PARF_CFG_BITS 0x210
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#define PARF_INT_ALL_STATUS 0x224
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#define PARF_INT_ALL_CLEAR 0x228
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#define PARF_INT_ALL_MASK 0x22c
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#define PARF_SLV_ADDR_MSB_CTRL 0x2c0
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#define PARF_DBI_BASE_ADDR 0x350
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#define PARF_DBI_BASE_ADDR_HI 0x354
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#define PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
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#define PARF_ATU_BASE_ADDR 0x634
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#define PARF_ATU_BASE_ADDR_HI 0x638
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#define PARF_SRIS_MODE 0x644
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#define PARF_DEVICE_TYPE 0x1000
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#define PARF_BDF_TO_SID_CFG 0x2c00
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/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
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#define PARF_INT_ALL_LINK_DOWN BIT(1)
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||||
#define PARF_INT_ALL_BME BIT(2)
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#define PARF_INT_ALL_PM_TURNOFF BIT(3)
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#define PARF_INT_ALL_DEBUG BIT(4)
|
||||
#define PARF_INT_ALL_LTR BIT(5)
|
||||
#define PARF_INT_ALL_MHI_Q6 BIT(6)
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||||
#define PARF_INT_ALL_MHI_A7 BIT(7)
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||||
#define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
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||||
#define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
|
||||
#define PARF_INT_ALL_MMIO_WRITE BIT(10)
|
||||
#define PARF_INT_ALL_CFG_WRITE BIT(11)
|
||||
#define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
|
||||
#define PARF_INT_ALL_LINK_UP BIT(13)
|
||||
#define PARF_INT_ALL_AER_LEGACY BIT(14)
|
||||
#define PARF_INT_ALL_PLS_ERR BIT(15)
|
||||
#define PARF_INT_ALL_PME_LEGACY BIT(16)
|
||||
#define PARF_INT_ALL_PLS_PME BIT(17)
|
||||
|
||||
/* PARF_BDF_TO_SID_CFG register fields */
|
||||
#define PARF_BDF_TO_SID_BYPASS BIT(0)
|
||||
|
||||
/* PARF_DEBUG_INT_EN register fields */
|
||||
#define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
|
||||
#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
|
||||
#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
|
||||
|
||||
/* PARF_DEVICE_TYPE register fields */
|
||||
#define PARF_DEVICE_TYPE_EP 0x0
|
||||
|
||||
/* PARF_PM_CTRL register fields */
|
||||
#define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
|
||||
#define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
|
||||
#define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
|
||||
|
||||
/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
|
||||
#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
|
||||
|
||||
/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
|
||||
#define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
|
||||
|
||||
/* PARF_Q2A_FLUSH register fields */
|
||||
#define PARF_Q2A_FLUSH_EN BIT(16)
|
||||
|
||||
/* PARF_SYS_CTRL register fields */
|
||||
#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
|
||||
#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
|
||||
#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
|
||||
|
||||
/* PARF_DB_CTRL register fields */
|
||||
#define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
|
||||
#define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
|
||||
#define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
|
||||
#define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
|
||||
#define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
|
||||
|
||||
/* PARF_CFG_BITS register fields */
|
||||
#define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
|
||||
|
||||
/* ELBI registers */
|
||||
#define ELBI_SYS_STTS 0x08
|
||||
|
||||
/* DBI registers */
|
||||
#define DBI_CON_STATUS 0x44
|
||||
|
||||
/* DBI register fields */
|
||||
#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
|
||||
|
||||
#define XMLH_LINK_UP 0x400
|
||||
#define CORE_RESET_TIME_US_MIN 1000
|
||||
#define CORE_RESET_TIME_US_MAX 1005
|
||||
#define WAKE_DELAY_US 2000 /* 2 ms */
|
||||
|
||||
#define to_pcie_ep(x) dev_get_drvdata((x)->dev)
|
||||
|
||||
enum qcom_pcie_ep_link_status {
|
||||
QCOM_PCIE_EP_LINK_DISABLED,
|
||||
QCOM_PCIE_EP_LINK_ENABLED,
|
||||
QCOM_PCIE_EP_LINK_UP,
|
||||
QCOM_PCIE_EP_LINK_DOWN,
|
||||
};
|
||||
|
||||
static struct clk_bulk_data qcom_pcie_ep_clks[] = {
|
||||
{ .id = "cfg" },
|
||||
{ .id = "aux" },
|
||||
{ .id = "bus_master" },
|
||||
{ .id = "bus_slave" },
|
||||
{ .id = "ref" },
|
||||
{ .id = "sleep" },
|
||||
{ .id = "slave_q2a" },
|
||||
};
|
||||
|
||||
struct qcom_pcie_ep {
|
||||
struct dw_pcie pci;
|
||||
|
||||
void __iomem *parf;
|
||||
void __iomem *elbi;
|
||||
struct regmap *perst_map;
|
||||
struct resource *mmio_res;
|
||||
|
||||
struct reset_control *core_reset;
|
||||
struct gpio_desc *reset;
|
||||
struct gpio_desc *wake;
|
||||
struct phy *phy;
|
||||
|
||||
u32 perst_en;
|
||||
u32 perst_sep_en;
|
||||
|
||||
enum qcom_pcie_ep_link_status link_status;
|
||||
int global_irq;
|
||||
int perst_irq;
|
||||
};
|
||||
|
||||
static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
|
||||
{
|
||||
struct dw_pcie *pci = &pcie_ep->pci;
|
||||
struct device *dev = pci->dev;
|
||||
int ret;
|
||||
|
||||
ret = reset_control_assert(pcie_ep->core_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot assert core reset\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
|
||||
|
||||
ret = reset_control_deassert(pcie_ep->core_reset);
|
||||
if (ret) {
|
||||
dev_err(dev, "Cannot de-assert core reset\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
|
||||
* device reset during host reboot and hibernation. The driver is
|
||||
* expected to handle this situation.
|
||||
*/
|
||||
static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
|
||||
{
|
||||
regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
|
||||
regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
|
||||
}
|
||||
|
||||
static int qcom_pcie_dw_link_up(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
|
||||
|
||||
return reg & XMLH_LINK_UP;
|
||||
}
|
||||
|
||||
static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
|
||||
|
||||
enable_irq(pcie_ep->perst_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
|
||||
|
||||
disable_irq(pcie_ep->perst_irq);
|
||||
}
|
||||
|
||||
static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
|
||||
struct device *dev = pci->dev;
|
||||
u32 val, offset;
|
||||
int ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_pcie_ep_core_reset(pcie_ep);
|
||||
if (ret)
|
||||
goto err_disable_clk;
|
||||
|
||||
ret = phy_init(pcie_ep->phy);
|
||||
if (ret)
|
||||
goto err_disable_clk;
|
||||
|
||||
ret = phy_power_on(pcie_ep->phy);
|
||||
if (ret)
|
||||
goto err_phy_exit;
|
||||
|
||||
/* Assert WAKE# to RC to indicate device is ready */
|
||||
gpiod_set_value_cansleep(pcie_ep->wake, 1);
|
||||
usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
|
||||
gpiod_set_value_cansleep(pcie_ep->wake, 0);
|
||||
|
||||
qcom_pcie_ep_configure_tcsr(pcie_ep);
|
||||
|
||||
/* Disable BDF to SID mapping */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
|
||||
val |= PARF_BDF_TO_SID_BYPASS;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
|
||||
|
||||
/* Enable debug IRQ */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
|
||||
val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
|
||||
PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
|
||||
PARF_DEBUG_INT_PM_DSTATE_CHANGE;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
|
||||
|
||||
/* Configure PCIe to endpoint mode */
|
||||
writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
|
||||
|
||||
/* Allow entering L1 state */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
|
||||
val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
|
||||
|
||||
/* Read halts write */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
|
||||
val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
|
||||
|
||||
/* Write after write halt */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
|
||||
val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
|
||||
|
||||
/* Q2A flush disable */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
|
||||
val &= ~PARF_Q2A_FLUSH_EN;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
|
||||
|
||||
/* Disable DBI Wakeup, core clock CGC and enable AUX power */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
|
||||
val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
|
||||
PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
|
||||
PARF_SYS_CTRL_AUX_PWR_DET;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
|
||||
|
||||
/* Disable the debouncers */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
|
||||
val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
|
||||
PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
|
||||
PARF_DB_CTRL_MST_WKP_BLOCK;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
|
||||
|
||||
/* Request to exit from L1SS for MSI and LTR MSG */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
|
||||
val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
|
||||
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
|
||||
/* Set the L0s Exit Latency to 2us-4us = 0x6 */
|
||||
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
||||
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
|
||||
val &= ~PCI_EXP_LNKCAP_L0SEL;
|
||||
val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
|
||||
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
|
||||
|
||||
/* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
|
||||
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
|
||||
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
|
||||
val &= ~PCI_EXP_LNKCAP_L1EL;
|
||||
val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
|
||||
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
|
||||
|
||||
dw_pcie_dbi_ro_wr_dis(pci);
|
||||
|
||||
writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
|
||||
val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
|
||||
PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
|
||||
PARF_INT_ALL_LINK_UP;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
|
||||
|
||||
ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to complete initialization: %d\n", ret);
|
||||
goto err_phy_power_off;
|
||||
}
|
||||
|
||||
/*
|
||||
* The physical address of the MMIO region which is exposed as the BAR
|
||||
* should be written to MHI BASE registers.
|
||||
*/
|
||||
writel_relaxed(pcie_ep->mmio_res->start,
|
||||
pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
|
||||
writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
|
||||
|
||||
dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
|
||||
|
||||
/* Enable LTSSM */
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
|
||||
val |= BIT(8);
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
|
||||
|
||||
return 0;
|
||||
|
||||
err_phy_power_off:
|
||||
phy_power_off(pcie_ep->phy);
|
||||
err_phy_exit:
|
||||
phy_exit(pcie_ep->phy);
|
||||
err_disable_clk:
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void qcom_pcie_perst_assert(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
|
||||
struct device *dev = pci->dev;
|
||||
|
||||
if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) {
|
||||
dev_dbg(dev, "Link is already disabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
phy_power_off(pcie_ep->phy);
|
||||
phy_exit(pcie_ep->phy);
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
|
||||
}
|
||||
|
||||
/* Common DWC controller ops */
|
||||
static const struct dw_pcie_ops pci_ops = {
|
||||
.link_up = qcom_pcie_dw_link_up,
|
||||
.start_link = qcom_pcie_dw_start_link,
|
||||
.stop_link = qcom_pcie_dw_stop_link,
|
||||
};
|
||||
|
||||
static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
|
||||
struct qcom_pcie_ep *pcie_ep)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct dw_pcie *pci = &pcie_ep->pci;
|
||||
struct device_node *syscon;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
|
||||
if (IS_ERR(pcie_ep->parf))
|
||||
return PTR_ERR(pcie_ep->parf);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||||
pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(pci->dbi_base))
|
||||
return PTR_ERR(pci->dbi_base);
|
||||
pci->dbi_base2 = pci->dbi_base;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
|
||||
pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
|
||||
if (IS_ERR(pcie_ep->elbi))
|
||||
return PTR_ERR(pcie_ep->elbi);
|
||||
|
||||
pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"mmio");
|
||||
|
||||
syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
|
||||
if (!syscon) {
|
||||
dev_err(dev, "Failed to parse qcom,perst-regs\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pcie_ep->perst_map = syscon_node_to_regmap(syscon);
|
||||
of_node_put(syscon);
|
||||
if (IS_ERR(pcie_ep->perst_map))
|
||||
return PTR_ERR(pcie_ep->perst_map);
|
||||
|
||||
ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
|
||||
1, &pcie_ep->perst_en);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "No Perst Enable offset in syscon\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
|
||||
2, &pcie_ep->perst_sep_en);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "No Perst Separation Enable offset in syscon\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
|
||||
struct qcom_pcie_ep *pcie_ep)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to get io resources %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
|
||||
if (IS_ERR(pcie_ep->core_reset))
|
||||
return PTR_ERR(pcie_ep->core_reset);
|
||||
|
||||
pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
|
||||
if (IS_ERR(pcie_ep->reset))
|
||||
return PTR_ERR(pcie_ep->reset);
|
||||
|
||||
pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
|
||||
if (IS_ERR(pcie_ep->wake))
|
||||
return PTR_ERR(pcie_ep->wake);
|
||||
|
||||
pcie_ep->phy = devm_phy_optional_get(&pdev->dev, "pciephy");
|
||||
if (IS_ERR(pcie_ep->phy))
|
||||
ret = PTR_ERR(pcie_ep->phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* TODO: Notify clients about PCIe state change */
|
||||
static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = data;
|
||||
struct dw_pcie *pci = &pcie_ep->pci;
|
||||
struct device *dev = pci->dev;
|
||||
u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
|
||||
u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK);
|
||||
u32 dstate, val;
|
||||
|
||||
writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
|
||||
status &= mask;
|
||||
|
||||
if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
|
||||
dev_dbg(dev, "Received Linkdown event\n");
|
||||
pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
|
||||
} else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
|
||||
dev_dbg(dev, "Received BME event. Link is enabled!\n");
|
||||
pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
|
||||
} else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
|
||||
dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
|
||||
val |= PARF_PM_CTRL_READY_ENTR_L23;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
|
||||
} else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
|
||||
dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
|
||||
DBI_CON_STATUS_POWER_STATE_MASK;
|
||||
dev_dbg(dev, "Received D%d state event\n", dstate);
|
||||
if (dstate == 3) {
|
||||
val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
|
||||
val |= PARF_PM_CTRL_REQ_EXIT_L1;
|
||||
writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
|
||||
}
|
||||
} else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
|
||||
dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
|
||||
dw_pcie_ep_linkup(&pci->ep);
|
||||
pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
|
||||
} else {
|
||||
dev_dbg(dev, "Received unknown event: %d\n", status);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = data;
|
||||
struct dw_pcie *pci = &pcie_ep->pci;
|
||||
struct device *dev = pci->dev;
|
||||
u32 perst;
|
||||
|
||||
perst = gpiod_get_value(pcie_ep->reset);
|
||||
if (perst) {
|
||||
dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
|
||||
qcom_pcie_perst_assert(pci);
|
||||
} else {
|
||||
dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
|
||||
qcom_pcie_perst_deassert(pci);
|
||||
}
|
||||
|
||||
irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
|
||||
(perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
|
||||
struct qcom_pcie_ep *pcie_ep)
|
||||
{
|
||||
int irq, ret;
|
||||
|
||||
irq = platform_get_irq_byname(pdev, "global");
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get Global IRQ\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
|
||||
qcom_pcie_ep_global_irq_thread,
|
||||
IRQF_ONESHOT,
|
||||
"global_irq", pcie_ep);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request Global IRQ\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
|
||||
irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
|
||||
ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
|
||||
qcom_pcie_ep_perst_irq_thread,
|
||||
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
|
||||
"perst_irq", pcie_ep);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
|
||||
disable_irq(irq);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||||
enum pci_epc_irq_type type, u16 interrupt_num)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
|
||||
switch (type) {
|
||||
case PCI_EPC_IRQ_LEGACY:
|
||||
return dw_pcie_ep_raise_legacy_irq(ep, func_no);
|
||||
case PCI_EPC_IRQ_MSI:
|
||||
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
|
||||
default:
|
||||
dev_err(pci->dev, "Unknown IRQ type\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pci_epc_features qcom_pcie_epc_features = {
|
||||
.linkup_notifier = true,
|
||||
.core_init_notifier = true,
|
||||
.msi_capable = true,
|
||||
.msix_capable = false,
|
||||
};
|
||||
|
||||
static const struct pci_epc_features *
|
||||
qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
|
||||
{
|
||||
return &qcom_pcie_epc_features;
|
||||
}
|
||||
|
||||
static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
enum pci_barno bar;
|
||||
|
||||
for (bar = BAR_0; bar <= BAR_5; bar++)
|
||||
dw_pcie_ep_reset_bar(pci, bar);
|
||||
}
|
||||
|
||||
static struct dw_pcie_ep_ops pci_ep_ops = {
|
||||
.ep_init = qcom_pcie_ep_init,
|
||||
.raise_irq = qcom_pcie_ep_raise_irq,
|
||||
.get_features = qcom_pcie_epc_get_features,
|
||||
};
|
||||
|
||||
static int qcom_pcie_ep_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct qcom_pcie_ep *pcie_ep;
|
||||
int ret;
|
||||
|
||||
pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
|
||||
if (!pcie_ep)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie_ep->pci.dev = dev;
|
||||
pcie_ep->pci.ops = &pci_ops;
|
||||
pcie_ep->pci.ep.ops = &pci_ep_ops;
|
||||
platform_set_drvdata(pdev, pcie_ep);
|
||||
|
||||
ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_pcie_ep_core_reset(pcie_ep);
|
||||
if (ret)
|
||||
goto err_disable_clk;
|
||||
|
||||
ret = phy_init(pcie_ep->phy);
|
||||
if (ret)
|
||||
goto err_disable_clk;
|
||||
|
||||
/* PHY needs to be powered on for dw_pcie_ep_init() */
|
||||
ret = phy_power_on(pcie_ep->phy);
|
||||
if (ret)
|
||||
goto err_phy_exit;
|
||||
|
||||
ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
|
||||
goto err_phy_power_off;
|
||||
}
|
||||
|
||||
ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
|
||||
if (ret)
|
||||
goto err_phy_power_off;
|
||||
|
||||
return 0;
|
||||
|
||||
err_phy_power_off:
|
||||
phy_power_off(pcie_ep->phy);
|
||||
err_phy_exit:
|
||||
phy_exit(pcie_ep->phy);
|
||||
err_disable_clk:
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qcom_pcie_ep_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
|
||||
|
||||
if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
|
||||
return 0;
|
||||
|
||||
phy_power_off(pcie_ep->phy);
|
||||
phy_exit(pcie_ep->phy);
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_pcie_ep_match[] = {
|
||||
{ .compatible = "qcom,sdx55-pcie-ep", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver qcom_pcie_ep_driver = {
|
||||
.probe = qcom_pcie_ep_probe,
|
||||
.remove = qcom_pcie_ep_remove,
|
||||
.driver = {
|
||||
.name = "qcom-pcie-ep",
|
||||
.of_match_table = qcom_pcie_ep_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(qcom_pcie_ep_driver);
|
||||
|
||||
MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
|
||||
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
|
||||
MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {
|
|||
struct regulator_bulk_data supplies[2];
|
||||
struct reset_control *pci_reset;
|
||||
struct clk *pipe_clk;
|
||||
struct clk *pipe_clk_src;
|
||||
struct clk *phy_pipe_clk;
|
||||
struct clk *ref_clk_src;
|
||||
};
|
||||
|
||||
union qcom_pcie_resources {
|
||||
|
|
@ -189,6 +192,11 @@ struct qcom_pcie_ops {
|
|||
int (*config_sid)(struct qcom_pcie *pcie);
|
||||
};
|
||||
|
||||
struct qcom_pcie_cfg {
|
||||
const struct qcom_pcie_ops *ops;
|
||||
unsigned int pipe_clk_need_muxing:1;
|
||||
};
|
||||
|
||||
struct qcom_pcie {
|
||||
struct dw_pcie *pci;
|
||||
void __iomem *parf; /* DT parf */
|
||||
|
|
@ -197,6 +205,7 @@ struct qcom_pcie {
|
|||
struct phy *phy;
|
||||
struct gpio_desc *reset;
|
||||
const struct qcom_pcie_ops *ops;
|
||||
unsigned int pipe_clk_need_muxing:1;
|
||||
};
|
||||
|
||||
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
|
||||
|
|
@ -1167,6 +1176,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
|
|||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (pcie->pipe_clk_need_muxing) {
|
||||
res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
|
||||
if (IS_ERR(res->pipe_clk_src))
|
||||
return PTR_ERR(res->pipe_clk_src);
|
||||
|
||||
res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
|
||||
if (IS_ERR(res->phy_pipe_clk))
|
||||
return PTR_ERR(res->phy_pipe_clk);
|
||||
|
||||
res->ref_clk_src = devm_clk_get(dev, "ref");
|
||||
if (IS_ERR(res->ref_clk_src))
|
||||
return PTR_ERR(res->ref_clk_src);
|
||||
}
|
||||
|
||||
res->pipe_clk = devm_clk_get(dev, "pipe");
|
||||
return PTR_ERR_OR_ZERO(res->pipe_clk);
|
||||
}
|
||||
|
|
@ -1185,6 +1208,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Set TCXO as clock source for pcie_pipe_clk_src */
|
||||
if (pcie->pipe_clk_need_muxing)
|
||||
clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
|
||||
|
||||
ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
|
||||
if (ret < 0)
|
||||
goto err_disable_regulators;
|
||||
|
|
@ -1256,6 +1283,10 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
|
|||
{
|
||||
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
|
||||
|
||||
/* Set pipe clock as clock source for pcie_pipe_clk_src */
|
||||
if (pcie->pipe_clk_need_muxing)
|
||||
clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
|
||||
|
||||
return clk_prepare_enable(res->pipe_clk);
|
||||
}
|
||||
|
||||
|
|
@ -1456,6 +1487,39 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
|
|||
.config_sid = qcom_pcie_config_sid_sm8250,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg apq8084_cfg = {
|
||||
.ops = &ops_1_0_0,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg ipq8064_cfg = {
|
||||
.ops = &ops_2_1_0,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg msm8996_cfg = {
|
||||
.ops = &ops_2_3_2,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg ipq8074_cfg = {
|
||||
.ops = &ops_2_3_3,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg ipq4019_cfg = {
|
||||
.ops = &ops_2_4_0,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg sdm845_cfg = {
|
||||
.ops = &ops_2_7_0,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg sm8250_cfg = {
|
||||
.ops = &ops_1_9_0,
|
||||
};
|
||||
|
||||
static const struct qcom_pcie_cfg sc7280_cfg = {
|
||||
.ops = &ops_1_9_0,
|
||||
.pipe_clk_need_muxing = true,
|
||||
};
|
||||
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.link_up = qcom_pcie_link_up,
|
||||
.start_link = qcom_pcie_start_link,
|
||||
|
|
@ -1467,6 +1531,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
|
|||
struct pcie_port *pp;
|
||||
struct dw_pcie *pci;
|
||||
struct qcom_pcie *pcie;
|
||||
const struct qcom_pcie_cfg *pcie_cfg;
|
||||
int ret;
|
||||
|
||||
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
||||
|
|
@ -1488,7 +1553,14 @@ static int qcom_pcie_probe(struct platform_device *pdev)
|
|||
|
||||
pcie->pci = pci;
|
||||
|
||||
pcie->ops = of_device_get_match_data(dev);
|
||||
pcie_cfg = of_device_get_match_data(dev);
|
||||
if (!pcie_cfg || !pcie_cfg->ops) {
|
||||
dev_err(dev, "Invalid platform data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pcie->ops = pcie_cfg->ops;
|
||||
pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing;
|
||||
|
||||
pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(pcie->reset)) {
|
||||
|
|
@ -1545,16 +1617,18 @@ err_pm_runtime_put:
|
|||
}
|
||||
|
||||
static const struct of_device_id qcom_pcie_match[] = {
|
||||
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
|
||||
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
|
||||
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
|
||||
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
|
||||
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
|
||||
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
|
||||
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
|
||||
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
|
||||
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
|
||||
{ .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
|
||||
{ .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
|
||||
{ .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
|
||||
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
|
||||
{ .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
|
||||
{ .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
|
||||
{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
|
||||
{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
|
||||
{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
|
||||
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
|
||||
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
|
||||
{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
|
||||
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue