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PCI/ACPI: Add ThunderX pass2.x 2nd node MCFG quirk 

Currently SoCs pass2.x do not emulate EA headers for ACPI boot method at
all.  However, for pass2.x some devices (like EDAC) advertise incorrect
base addresses in their BARs which results in driver probe failure during
resource request.  Since all problematic blocks are on 2nd NUMA node under
domain 10 add necessary quirk entry to obtain BAR addresses correction
using EA header emulation.

Fixes: 44f22bd91e ("PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller")
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Robert Richter <rrichter@cavium.com>
CC: stable@vger.kernel.org	# v4.10+
This commit is contained in:
Tomasz Nowicki 2017-03-29 14:16:13 +02:00 committed by Bjorn Helgaas
parent ced414a14f
commit cd18374048
1 changed files with 1 additions and 0 deletions
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drivers/acpi/pci_mcfg.c
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@ -101,6 +101,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
/* SoC pass2.x */ /* SoC pass2.x */
THUNDER_PEM_QUIRK(1, 0), THUNDER_PEM_QUIRK(1, 0),
THUNDER_PEM_QUIRK(1, 1), THUNDER_PEM_QUIRK(1, 1),
THUNDER_ECAM_QUIRK(1, 10),
/* SoC pass1.x */ /* SoC pass1.x */
THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */