MIPS: JZ4740: GPIO: Use shared irq chip for all gpios
Currently there is one irq_chip per gpio_chip with the only difference being the name. Since the information whether the irq belong to GPIO bank A, B, C or D is not that important rewrite the code to simply use a single irq_chip for all gpio_chips. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2182/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -86,7 +86,6 @@ struct jz_gpio_chip {
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spinlock_t lock;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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struct sys_device sysdev;
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};
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@ -435,6 +434,17 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
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return 0;
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}
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static struct irq_chip jz_gpio_irq_chip = {
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.name = "GPIO",
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.irq_mask = jz_gpio_irq_mask,
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.irq_unmask = jz_gpio_irq_unmask,
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.irq_ack = jz_gpio_irq_ack,
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.irq_startup = jz_gpio_irq_startup,
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.irq_shutdown = jz_gpio_irq_shutdown,
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.irq_set_type = jz_gpio_irq_set_type,
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.irq_set_wake = jz_gpio_irq_set_wake,
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};
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/*
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* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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@ -453,16 +463,6 @@ static struct lock_class_key gpio_lock_class;
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.base = JZ4740_GPIO_BASE_ ## _bank, \
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.ngpio = JZ4740_GPIO_NUM_ ## _bank, \
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}, \
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.irq_chip = { \
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.name = "GPIO Bank " # _bank, \
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.irq_mask = jz_gpio_irq_mask, \
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.irq_unmask = jz_gpio_irq_unmask, \
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.irq_ack = jz_gpio_irq_ack, \
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.irq_startup = jz_gpio_irq_startup, \
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.irq_shutdown = jz_gpio_irq_shutdown, \
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.irq_set_type = jz_gpio_irq_set_type, \
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.irq_set_wake = jz_gpio_irq_set_wake, \
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}, \
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}
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static struct jz_gpio_chip jz4740_gpio_chips[] = {
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@ -529,7 +529,8 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
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for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
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lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
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set_irq_chip_data(irq, chip);
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set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
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set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
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handle_level_irq);
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}
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return 0;
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