[ARM] 4790/1: S3C2412: Fix parent selection for msysclk.
The msysclk clock was checking for the wrong PLL for the parent in s3c2412_setparent_msysclk(), trying the UPLL instead of the MPLL output. Also ensure the mpll and fclks are at the same rate at init time. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -217,7 +217,7 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
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if (parent == &clk_mdivclk)
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if (parent == &clk_mdivclk)
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clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
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clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
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else if (parent == &clk_upll)
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else if (parent == &clk_mpll)
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clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
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clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
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else
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else
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return -EINVAL;
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return -EINVAL;
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@ -168,6 +168,8 @@ void __init s3c2412_init_clocks(int xtal)
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fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
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fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
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clk_mpll.rate = fclk;
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tmp = __raw_readl(S3C2410_CLKDIVN);
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tmp = __raw_readl(S3C2410_CLKDIVN);
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/* work out clock scalings */
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/* work out clock scalings */
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