drm/exynos: implement atomic_{begin/flush} of DECON
Each CRTC's atomic_{begin/flush} must stop/start the update of shadow registers to active register in the functions. This patch achieves these purpose by moving the setting of protection bits to those functions from decon_update_plane. v2: rebased to the branch exynos-drm-next Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -219,6 +219,17 @@ static void decon_shadow_protect_win(struct decon_context *ctx, int win,
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writel(val, ctx->addr + DECON_SHADOWCON);
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}
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static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct decon_context *ctx = crtc->ctx;
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if (ctx->suspended)
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return;
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decon_shadow_protect_win(ctx, plane->zpos, true);
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}
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static void decon_update_plane(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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@ -232,8 +243,6 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
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if (ctx->suspended)
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return;
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decon_shadow_protect_win(ctx, win, true);
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val = COORDINATE_X(plane->crtc_x) | COORDINATE_Y(plane->crtc_y);
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writel(val, ctx->addr + DECON_VIDOSDxA(win));
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@ -265,15 +274,10 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
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val |= WINCONx_ENWIN_F;
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writel(val, ctx->addr + DECON_WINCONx(win));
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decon_shadow_protect_win(ctx, win, false);
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/* standalone update */
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val = readl(ctx->addr + DECON_UPDATE);
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val |= STANDALONE_UPDATE_F;
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writel(val, ctx->addr + DECON_UPDATE);
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if (ctx->i80_if)
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atomic_set(&ctx->win_updated, 1);
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}
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static void decon_disable_plane(struct exynos_drm_crtc *crtc,
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@ -301,6 +305,20 @@ static void decon_disable_plane(struct exynos_drm_crtc *crtc,
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writel(val, ctx->addr + DECON_UPDATE);
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}
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static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct decon_context *ctx = crtc->ctx;
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if (ctx->suspended)
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return;
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decon_shadow_protect_win(ctx, plane->zpos, false);
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if (ctx->i80_if)
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atomic_set(&ctx->win_updated, 1);
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}
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static void decon_swreset(struct decon_context *ctx)
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{
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unsigned int tries;
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@ -455,8 +473,10 @@ static struct exynos_drm_crtc_ops decon_crtc_ops = {
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.enable_vblank = decon_enable_vblank,
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.disable_vblank = decon_disable_vblank,
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.commit = decon_commit,
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.atomic_begin = decon_atomic_begin,
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.update_plane = decon_update_plane,
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.disable_plane = decon_disable_plane,
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.atomic_flush = decon_atomic_flush,
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.te_handler = decon_te_irq_handler,
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};
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@ -383,6 +383,17 @@ static void decon_shadow_protect_win(struct decon_context *ctx,
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writel(val, ctx->regs + SHADOWCON);
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}
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static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct decon_context *ctx = crtc->ctx;
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if (ctx->suspended)
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return;
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decon_shadow_protect_win(ctx, plane->zpos, true);
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}
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static void decon_update_plane(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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@ -410,9 +421,6 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
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* is set.
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*/
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/* protect windows */
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decon_shadow_protect_win(ctx, win, true);
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/* buffer start address */
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val = (unsigned long)plane->dma_addr[0];
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writel(val, ctx->regs + VIDW_BUF_START(win));
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@ -510,14 +518,22 @@ static void decon_disable_plane(struct exynos_drm_crtc *crtc,
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val &= ~WINCONx_ENWIN;
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writel(val, ctx->regs + WINCON(win));
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/* unprotect windows */
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decon_shadow_protect_win(ctx, win, false);
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val = readl(ctx->regs + DECON_UPDATE);
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val |= DECON_UPDATE_STANDALONE_F;
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writel(val, ctx->regs + DECON_UPDATE);
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}
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static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
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struct exynos_drm_plane *plane)
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{
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struct decon_context *ctx = crtc->ctx;
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if (ctx->suspended)
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return;
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decon_shadow_protect_win(ctx, plane->zpos, false);
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}
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static void decon_init(struct decon_context *ctx)
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{
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u32 val;
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@ -614,8 +630,10 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = {
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.enable_vblank = decon_enable_vblank,
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.disable_vblank = decon_disable_vblank,
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.wait_for_vblank = decon_wait_for_vblank,
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.atomic_begin = decon_atomic_begin,
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.update_plane = decon_update_plane,
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.disable_plane = decon_disable_plane,
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.atomic_flush = decon_atomic_flush,
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};
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