rtl8xxxu: Set sequence number correctly for 40 byte TX descriptors
SEQ changed location in the 40 byte TX descriptor. Set it correctly. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -6943,6 +6943,7 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
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struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
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struct rtl8xxxu_priv *priv = hw->priv;
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struct rtl8723au_tx_desc *tx_desc;
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struct rtl8723bu_tx_desc *tx_desc40;
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struct rtl8xxxu_tx_urb *tx_urb;
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struct ieee80211_sta *sta = NULL;
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struct ieee80211_vif *vif = tx_info->control.vif;
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@ -6953,7 +6954,7 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
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u16 rate_flag = tx_info->control.rates[0].flags;
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int tx_desc_size = priv->fops->tx_desc_size;
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int ret;
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bool txdesc40, ampdu_enable;
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bool usedesc40, ampdu_enable;
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if (skb_headroom(skb) < tx_desc_size) {
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dev_warn(dev,
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@ -6981,7 +6982,7 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
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if (ieee80211_is_action(hdr->frame_control))
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rtl8xxxu_dump_action(dev, hdr);
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txdesc40 = (tx_desc_size == 40);
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usedesc40 = (tx_desc_size == 40);
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tx_info->rate_driver_data[0] = hw;
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if (control && control->sta)
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@ -7017,9 +7018,6 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
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}
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}
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seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
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tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
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if (rate_flag & IEEE80211_TX_RC_MCS)
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rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
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else
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@ -7043,16 +7041,26 @@ static void rtl8xxxu_tx(struct ieee80211_hw *hw,
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}
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}
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if (!txdesc40) {
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seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
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if (!usedesc40) {
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tx_desc->txdw3 =
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cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT_8723A);
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if (ampdu_enable)
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tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE_8723A);
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else
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tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_BREAK_8723A);
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} else {
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tx_desc40 = (struct rtl8723bu_tx_desc *)tx_desc;
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tx_desc40->txdw9 =
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cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT_8723B);
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if (ampdu_enable)
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tx_desc->txdw2 |= cpu_to_le32(TXDESC_AGG_ENABLE_8723B);
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tx_desc40->txdw2 |=
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cpu_to_le32(TXDESC_AGG_ENABLE_8723B);
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else
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tx_desc->txdw2 |= cpu_to_le32(TXDESC_AGG_BREAK_8723B);
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tx_desc40->txdw2 |= cpu_to_le32(TXDESC_AGG_BREAK_8723B);
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};
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if (ieee80211_is_data_qos(hdr->frame_control))
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@ -467,8 +467,8 @@ struct rtl8723bu_tx_desc {
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#define TXDESC_GID_8723B BIT(24)
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/* Word 3 */
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#define TXDESC_SEQ_SHIFT 16
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#define TXDESC_SEQ_MASK 0x0fff0000
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#define TXDESC_SEQ_SHIFT_8723A 16
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#define TXDESC_SEQ_MASK_8723A 0x0fff0000
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/* Word 4 */
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#define TXDESC_QOS BIT(6)
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@ -498,6 +498,10 @@ struct rtl8723bu_tx_desc {
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/* Word 6 */
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#define TXDESC_MAX_AGG_SHIFT 11
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/* Word 9 */
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#define TXDESC_SEQ_SHIFT_8723B 12
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#define TXDESC_SEQ_MASK_8723B 0x00fff000
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struct phy_rx_agc_info {
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#ifdef __LITTLE_ENDIAN
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u8 gain:7, trsw:1;
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