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Merge branch 'pci/misc' into next 

* pci/misc:
  PCI: Fix comment typo for pci_add_cap_save_buffer()
  PCI: Return -ENOSYS for SR-IOV operations on non-SR-IOV devices
  PCI: Update NumVFs register when disabling SR-IOV
  x86/PCI: MMCONFIG: Check earlier for MMCONFIG region at address zero
  PCI: Convert class code to use dev_groups
  frv/PCI: Mark pcibios_fixup_bus() as non-init
  x86/pci/mrst: Cleanup checkpatch.pl warnings
  PCI: Rename "PCI Express support" kconfig title
  PCI: Fix comment typo in iov.c
This commit is contained in:
Bjorn Helgaas 2013-08-01 11:03:52 -06:00
parent 28fa60a830 ce1be10bf6
commit cbe2bb4f2b
9 changed files with 65 additions and 48 deletions
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2
arch/frv/mb93090-mb00/pci-vdk.c
View File

@ -320,7 +320,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
* are examined. * are examined.
*/ */
void __init pcibios_fixup_bus(struct pci_bus *bus) void pcibios_fixup_bus(struct pci_bus *bus)
{ {
#if 0 #if 0
printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number); printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);

7
arch/x86/pci/mmconfig-shared.c
View File

@ -700,7 +700,7 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed) if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
return -ENODEV; return -ENODEV;
if (start > end) if (start > end || !addr)
return -EINVAL; return -EINVAL;
mutex_lock(&pci_mmcfg_lock); mutex_lock(&pci_mmcfg_lock);
@ -716,11 +716,6 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
return -EEXIST; return -EEXIST;
} }
if (!addr) {
mutex_unlock(&pci_mmcfg_lock);
return -EINVAL;
}
rc = -EBUSY; rc = -EBUSY;
cfg = pci_mmconfig_alloc(seg, start, end, addr); cfg = pci_mmconfig_alloc(seg, start, end, addr);
if (cfg == NULL) { if (cfg == NULL) {

41
arch/x86/pci/mrst.c
View File

@ -23,11 +23,11 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/dmi.h> #include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <asm/acpi.h>
#include <asm/segment.h> #include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/pci_x86.h> #include <asm/pci_x86.h>
#include <asm/hw_irq.h> #include <asm/hw_irq.h>
#include <asm/io_apic.h> #include <asm/io_apic.h>
@ -43,7 +43,7 @@
#define PCI_FIXED_BAR_4_SIZE 0x14 #define PCI_FIXED_BAR_4_SIZE 0x14
#define PCI_FIXED_BAR_5_SIZE 0x1c #define PCI_FIXED_BAR_5_SIZE 0x1c
static int pci_soc_mode = 0; static int pci_soc_mode;
/** /**
* fixed_bar_cap - return the offset of the fixed BAR cap if found * fixed_bar_cap - return the offset of the fixed BAR cap if found
@ -141,7 +141,8 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
*/ */
static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
{ {
/* This is a workaround for A0 LNC bug where PCI status register does /*
* This is a workaround for A0 LNC bug where PCI status register does
* not have new CAP bit set. can not be written by SW either. * not have new CAP bit set. can not be written by SW either.
* *
* PCI header type in real LNC indicates a single function device, this * PCI header type in real LNC indicates a single function device, this
@ -154,7 +155,7 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
|| devfn == PCI_DEVFN(0, 0) || devfn == PCI_DEVFN(0, 0)
|| devfn == PCI_DEVFN(3, 0))) || devfn == PCI_DEVFN(3, 0)))
return 1; return 1;
return 0; /* langwell on others */ return 0; /* Langwell on others */
} }
static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
@ -172,7 +173,8 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
{ {
int offset; int offset;
/* On MRST, there is no PCI ROM BAR, this will cause a subsequent read /*
* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
* to ROM BAR return 0 then being ignored. * to ROM BAR return 0 then being ignored.
*/ */
if (where == PCI_ROM_ADDRESS) if (where == PCI_ROM_ADDRESS)
@ -210,7 +212,8 @@ static int mrst_pci_irq_enable(struct pci_dev *dev)
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
/* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to /*
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device. * IOAPIC RTE entries, so we just enable RTE for the device.
*/ */
irq_attr.ioapic = mp_find_ioapic(dev->irq); irq_attr.ioapic = mp_find_ioapic(dev->irq);
@ -235,7 +238,7 @@ struct pci_ops pci_mrst_ops = {
*/ */
int __init pci_mrst_init(void) int __init pci_mrst_init(void)
{ {
printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n"); pr_info("Intel MID platform detected, using MID PCI ops\n");
pci_mmcfg_late_init(); pci_mmcfg_late_init();
pcibios_enable_irq = mrst_pci_irq_enable; pcibios_enable_irq = mrst_pci_irq_enable;
pci_root_ops = pci_mrst_ops; pci_root_ops = pci_mrst_ops;
@ -244,17 +247,21 @@ int __init pci_mrst_init(void)
return 1; return 1;
} }
/* Langwell devices are not true pci devices, they are not subject to 10 ms /*
* d3 to d0 delay required by pci spec. * Langwell devices are not true PCI devices; they are not subject to 10 ms
* d3 to d0 delay required by PCI spec.
*/ */
static void pci_d3delay_fixup(struct pci_dev *dev) static void pci_d3delay_fixup(struct pci_dev *dev)
{ {
/* PCI fixups are effectively decided compile time. If we have a dual /*
SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */ * PCI fixups are effectively decided compile time. If we have a dual
if (!pci_soc_mode) * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
return; */
/* true pci devices in lincroft should allow type 1 access, the rest if (!pci_soc_mode)
* are langwell fake pci devices. return;
/*
* True PCI devices in Lincroft should allow type 1 access, the rest
* are Langwell fake PCI devices.
*/ */
if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID)) if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
return; return;

23
drivers/pci/iov.c
View File

@ -286,7 +286,6 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
(!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial))) (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))
return -EINVAL; return -EINVAL;
pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset); pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset);
pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride); pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride);
if (!offset || (nr_virtfn > 1 && !stride)) if (!offset || (nr_virtfn > 1 && !stride))
@ -324,7 +323,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
if (!pdev->is_physfn) { if (!pdev->is_physfn) {
pci_dev_put(pdev); pci_dev_put(pdev);
return -ENODEV; return -ENOSYS;
} }
rc = sysfs_create_link(&dev->dev.kobj, rc = sysfs_create_link(&dev->dev.kobj,
@ -334,6 +333,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
return rc; return rc;
} }
pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
pci_cfg_access_lock(dev); pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
@ -368,6 +368,7 @@ failed:
iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE); iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
pci_cfg_access_lock(dev); pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);
ssleep(1); ssleep(1);
pci_cfg_access_unlock(dev); pci_cfg_access_unlock(dev);
@ -401,6 +402,7 @@ static void sriov_disable(struct pci_dev *dev)
sysfs_remove_link(&dev->dev.kobj, "dep_link"); sysfs_remove_link(&dev->dev.kobj, "dep_link");
iov->num_VFs = 0; iov->num_VFs = 0;
pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, 0);
} }
static int sriov_init(struct pci_dev *dev, int pos) static int sriov_init(struct pci_dev *dev, int pos)
@ -662,7 +664,7 @@ int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
might_sleep(); might_sleep();
if (!dev->is_physfn) if (!dev->is_physfn)
return -ENODEV; return -ENOSYS;
return sriov_enable(dev, nr_virtfn); return sriov_enable(dev, nr_virtfn);
} }
@ -722,7 +724,7 @@ EXPORT_SYMBOL_GPL(pci_num_vf);
* @dev: the PCI device * @dev: the PCI device
* *
* Returns number of VFs belonging to this device that are assigned to a guest. * Returns number of VFs belonging to this device that are assigned to a guest.
* If device is not a physical function returns -ENODEV. * If device is not a physical function returns 0.
*/ */
int pci_vfs_assigned(struct pci_dev *dev) int pci_vfs_assigned(struct pci_dev *dev)
{ {
@ -767,12 +769,15 @@ EXPORT_SYMBOL_GPL(pci_vfs_assigned);
* device's mutex held. * device's mutex held.
* *
* Returns 0 if PF is an SRIOV-capable device and * Returns 0 if PF is an SRIOV-capable device and
* value of numvfs valid. If not a PF with VFS, return -EINVAL; * value of numvfs valid. If not a PF return -ENOSYS;
* if numvfs is invalid return -EINVAL;
* if VFs already enabled, return -EBUSY. * if VFs already enabled, return -EBUSY.
*/ */
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
{ {
if (!dev->is_physfn || (numvfs > dev->sriov->total_VFs)) if (!dev->is_physfn)
return -ENOSYS;
if (numvfs > dev->sriov->total_VFs)
return -EINVAL; return -EINVAL;
/* Shouldn't change if VFs already enabled */ /* Shouldn't change if VFs already enabled */
@ -786,17 +791,17 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
EXPORT_SYMBOL_GPL(pci_sriov_set_totalvfs); EXPORT_SYMBOL_GPL(pci_sriov_set_totalvfs);
/** /**
* pci_sriov_get_totalvfs -- get total VFs supported on this devic3 * pci_sriov_get_totalvfs -- get total VFs supported on this device
* @dev: the PCI PF device * @dev: the PCI PF device
* *
* For a PCIe device with SRIOV support, return the PCIe * For a PCIe device with SRIOV support, return the PCIe
* SRIOV capability value of TotalVFs or the value of driver_max_VFs * SRIOV capability value of TotalVFs or the value of driver_max_VFs
* if the driver reduced it. Otherwise, -EINVAL. * if the driver reduced it. Otherwise 0.
*/ */
int pci_sriov_get_totalvfs(struct pci_dev *dev) int pci_sriov_get_totalvfs(struct pci_dev *dev)
{ {
if (!dev->is_physfn) if (!dev->is_physfn)
return -EINVAL; return 0;
if (dev->sriov->driver_max_VFs) if (dev->sriov->driver_max_VFs)
return dev->sriov->driver_max_VFs; return dev->sriov->driver_max_VFs;

32
drivers/pci/pci-sysfs.c
View File

@ -131,19 +131,19 @@ static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
return ret; return ret;
} }
static inline ssize_t pci_bus_show_cpumaskaffinity(struct device *dev, static ssize_t cpuaffinity_show(struct device *dev,
struct device_attribute *attr, struct device_attribute *attr, char *buf)
char *buf)
{ {
return pci_bus_show_cpuaffinity(dev, 0, attr, buf); return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
} }
static DEVICE_ATTR_RO(cpuaffinity);
static inline ssize_t pci_bus_show_cpulistaffinity(struct device *dev, static ssize_t cpulistaffinity_show(struct device *dev,
struct device_attribute *attr, struct device_attribute *attr, char *buf)
char *buf)
{ {
return pci_bus_show_cpuaffinity(dev, 1, attr, buf); return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
} }
static DEVICE_ATTR_RO(cpulistaffinity);
/* show resources */ /* show resources */
static ssize_t static ssize_t
@ -379,6 +379,7 @@ dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
} }
return count; return count;
} }
static DEVICE_ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store);
#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI) #if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
static ssize_t d3cold_allowed_store(struct device *dev, static ssize_t d3cold_allowed_store(struct device *dev,
@ -514,11 +515,20 @@ struct device_attribute pci_dev_attrs[] = {
__ATTR_NULL, __ATTR_NULL,
}; };
struct device_attribute pcibus_dev_attrs[] = { static struct attribute *pcibus_attrs[] = {
__ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store), &dev_attr_rescan.attr,
__ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL), &dev_attr_cpuaffinity.attr,
__ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL), &dev_attr_cpulistaffinity.attr,
__ATTR_NULL, NULL,
};
static const struct attribute_group pcibus_group = {
.attrs = pcibus_attrs,
};
const struct attribute_group *pcibus_groups[] = {
&pcibus_group,
NULL,
}; };
static ssize_t static ssize_t

2
drivers/pci/pci.c
View File

@ -1992,7 +1992,7 @@ static void pci_add_saved_cap(struct pci_dev *pci_dev,
} }
/** /**
* pci_add_save_buffer - allocate buffer for saving given capability registers * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
* @dev: the PCI device * @dev: the PCI device
* @cap: the capability to allocate the buffer for * @cap: the capability to allocate the buffer for
* @size: requested size of the buffer * @size: requested size of the buffer

2
drivers/pci/pci.h
View File

@ -151,7 +151,7 @@ static inline int pci_no_d1d2(struct pci_dev *dev)
} }
extern struct device_attribute pci_dev_attrs[]; extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute pcibus_dev_attrs[]; extern const struct attribute_group *pcibus_groups[];
extern struct device_type pci_dev_type; extern struct device_type pci_dev_type;
extern struct bus_attribute pci_bus_attrs[]; extern struct bus_attribute pci_bus_attrs[];

2
drivers/pci/pcie/Kconfig
View File

@ -2,7 +2,7 @@
# PCI Express Port Bus Configuration # PCI Express Port Bus Configuration
# #
config PCIEPORTBUS config PCIEPORTBUS
bool "PCI Express support" bool "PCI Express Port Bus support"
depends on PCI depends on PCI
help help
This automatically enables PCI Express Port Bus support. Users can This automatically enables PCI Express Port Bus support. Users can

2
drivers/pci/probe.c
View File

@ -96,7 +96,7 @@ static void release_pcibus_dev(struct device *dev)
static struct class pcibus_class = { static struct class pcibus_class = {
.name = "pci_bus", .name = "pci_bus",
.dev_release = &release_pcibus_dev, .dev_release = &release_pcibus_dev,
.dev_attrs = pcibus_dev_attrs, .dev_groups = pcibus_groups,
}; };
static int __init pcibus_class_init(void) static int __init pcibus_class_init(void)