Two smaller pin control fixes for the v4.11 series:
- Add a get_direction() function to the qcom driver. - Fix two pin names in the uniphier driver. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJYwu4/AAoJEEEQszewGV1zncUQAMZJuxdElAQUHjLi1kILmghW 8aeTfXSD5dhVgBPZPnvmEpgjL32gOVtrXG0PWmoDL1BE2Kq+RXYopgdaNShxLkA7 +8aw6vvr6bHv430Eg4ofLwzrLaMzgKh7nSekZBzdBRmnj0oXhTcDDxGHPiBPXxnz 51lX/hY8aenJiY4+Fhu7wZH14cxWlStVOHoP2KFZGuHtupBccPHsvbCD4Qkyyj0i 00Io/YlVuW6ZMRedL7rs7HRo+x0XcQQ2T/8BY/Nr/EmVTPnXPq1slyThHwPXK+fZ v4lyLeF/AhgOkdV7WIV1ae9peuLAPqYbjdfX/+JU4etsfjuH7QufDjG6yTuvSUuR gUy0CBcCdU32y7bopExNTBUs07tNZqZ5xPQ2+3Qm9EsPqHF6LzYn2hOYJU7X0CUF B0ZfOlrjNiHMxjcehYbc7xsAtM5kCeg01yi3GbrrifjrQI52mvFiwsgdZ9ofFtSd S2OKkg2UPguh2tF96FPBrrkO3dn3ToRThSHx55vAtjL5rU7wiVfGeI+TVrfB1hjF NsZ1OZe3bBmcYsl4QoEZEb1ew82Bq5VELHtS3CYL1ioeIEFSi2/EhyFQxq9F0UlS 8np6qc3SZkSEwk3kJVaWUD4VG0HcksYvBgBNtPELgc0sq/fOqB7aL2FhA+J4j+Ma D938VxZi0/pD/xWJfVQ1 =QWle -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pinctrl fixes from Linus Walleij: "Two smaller pin control fixes for the v4.11 series: - Add a get_direction() function to the qcom driver - Fix two pin names in the uniphier driver" * tag 'pinctrl-v4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: uniphier: change pin names of aio/xirq for LD11 pinctrl: qcom: add get_direction function
This commit is contained in:
commit
cb853a82df
|
@ -422,6 +422,20 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
const struct msm_pingroup *g;
|
||||
u32 val;
|
||||
|
||||
g = &pctrl->soc->groups[offset];
|
||||
|
||||
val = readl(pctrl->regs + g->ctl_reg);
|
||||
|
||||
/* 0 = output, 1 = input */
|
||||
return val & BIT(g->oe_bit) ? 0 : 1;
|
||||
}
|
||||
|
||||
static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
const struct msm_pingroup *g;
|
||||
|
@ -510,6 +524,7 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|||
static struct gpio_chip msm_gpio_template = {
|
||||
.direction_input = msm_gpio_direction_input,
|
||||
.direction_output = msm_gpio_direction_output,
|
||||
.get_direction = msm_gpio_get_direction,
|
||||
.get = msm_gpio_get,
|
||||
.set = msm_gpio_set,
|
||||
.request = gpiochip_generic_request,
|
||||
|
|
|
@ -390,22 +390,22 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
|
|||
UNIPHIER_PINCTRL_PIN(140, "AO1D0", 140,
|
||||
140, UNIPHIER_PIN_DRV_1BIT,
|
||||
140, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(141, "TCON0", 141,
|
||||
UNIPHIER_PINCTRL_PIN(141, "AO1D1", 141,
|
||||
141, UNIPHIER_PIN_DRV_1BIT,
|
||||
141, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(142, "TCON1", 142,
|
||||
UNIPHIER_PINCTRL_PIN(142, "AO1D2", 142,
|
||||
142, UNIPHIER_PIN_DRV_1BIT,
|
||||
142, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(143, "TCON2", 143,
|
||||
UNIPHIER_PINCTRL_PIN(143, "XIRQ9", 143,
|
||||
143, UNIPHIER_PIN_DRV_1BIT,
|
||||
143, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(144, "TCON3", 144,
|
||||
UNIPHIER_PINCTRL_PIN(144, "XIRQ10", 144,
|
||||
144, UNIPHIER_PIN_DRV_1BIT,
|
||||
144, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(145, "TCON4", 145,
|
||||
UNIPHIER_PINCTRL_PIN(145, "XIRQ11", 145,
|
||||
145, UNIPHIER_PIN_DRV_1BIT,
|
||||
145, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(146, "TCON5", 146,
|
||||
UNIPHIER_PINCTRL_PIN(146, "XIRQ13", 146,
|
||||
146, UNIPHIER_PIN_DRV_1BIT,
|
||||
146, UNIPHIER_PIN_PULL_DOWN),
|
||||
UNIPHIER_PINCTRL_PIN(147, "PWMA", 147,
|
||||
|
|
Loading…
Reference in New Issue