powerpc/powernv: Drop PHB operation reset()
The patch drops PHB EEH operation reset() and merges its logic to eeh_ops::reset(). Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Gavin Shan
Benjamin Herrenschmidt
parent
2a485ad7c8
commit
cadf364d14
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@ -34,240 +34,5 @@
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#include "powernv.h"
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#include "pci.h"
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static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
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{
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s64 rc = OPAL_HARDWARE;
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while (1) {
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rc = opal_pci_poll(phb->opal_id);
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if (rc <= 0)
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break;
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if (system_state < SYSTEM_RUNNING)
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udelay(1000 * rc);
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else
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msleep(rc);
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}
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return rc;
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}
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int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
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{
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struct pnv_phb *phb = hose->private_data;
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s64 rc = OPAL_HARDWARE;
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pr_debug("%s: Reset PHB#%x, option=%d\n",
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__func__, hose->global_number, option);
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/* Issue PHB complete reset request */
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if (option == EEH_RESET_FUNDAMENTAL ||
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option == EEH_RESET_HOT)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PHB_COMPLETE,
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OPAL_ASSERT_RESET);
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else if (option == EEH_RESET_DEACTIVATE)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PHB_COMPLETE,
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OPAL_DEASSERT_RESET);
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if (rc < 0)
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goto out;
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/*
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* Poll state of the PHB until the request is done
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* successfully. The PHB reset is usually PHB complete
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* reset followed by hot reset on root bus. So we also
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* need the PCI bus settlement delay.
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*/
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rc = ioda_eeh_phb_poll(phb);
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if (option == EEH_RESET_DEACTIVATE) {
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if (system_state < SYSTEM_RUNNING)
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udelay(1000 * EEH_PE_RST_SETTLE_TIME);
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else
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msleep(EEH_PE_RST_SETTLE_TIME);
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}
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out:
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if (rc != OPAL_SUCCESS)
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return -EIO;
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return 0;
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}
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static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
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{
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struct pnv_phb *phb = hose->private_data;
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s64 rc = OPAL_SUCCESS;
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pr_debug("%s: Reset PHB#%x, option=%d\n",
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__func__, hose->global_number, option);
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/*
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* During the reset deassert time, we needn't care
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* the reset scope because the firmware does nothing
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* for fundamental or hot reset during deassert phase.
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*/
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if (option == EEH_RESET_FUNDAMENTAL)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PCI_FUNDAMENTAL,
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OPAL_ASSERT_RESET);
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else if (option == EEH_RESET_HOT)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PCI_HOT,
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OPAL_ASSERT_RESET);
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else if (option == EEH_RESET_DEACTIVATE)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PCI_HOT,
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OPAL_DEASSERT_RESET);
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if (rc < 0)
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goto out;
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/* Poll state of the PHB until the request is done */
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rc = ioda_eeh_phb_poll(phb);
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if (option == EEH_RESET_DEACTIVATE)
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msleep(EEH_PE_RST_SETTLE_TIME);
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out:
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if (rc != OPAL_SUCCESS)
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return -EIO;
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return 0;
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}
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static int ioda_eeh_bridge_reset(struct pci_dev *dev, int option)
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{
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struct device_node *dn = pci_device_to_OF_node(dev);
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struct eeh_dev *edev = of_node_to_eeh_dev(dn);
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int aer = edev ? edev->aer_cap : 0;
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u32 ctrl;
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pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
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__func__, pci_domain_nr(dev->bus),
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dev->bus->number, option);
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switch (option) {
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case EEH_RESET_FUNDAMENTAL:
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case EEH_RESET_HOT:
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/* Don't report linkDown event */
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if (aer) {
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eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, &ctrl);
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ctrl |= PCI_ERR_UNC_SURPDN;
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eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, ctrl);
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}
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eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
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ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
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eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
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msleep(EEH_PE_RST_HOLD_TIME);
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break;
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case EEH_RESET_DEACTIVATE:
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eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
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ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
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eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
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msleep(EEH_PE_RST_SETTLE_TIME);
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/* Continue reporting linkDown event */
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if (aer) {
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eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, &ctrl);
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ctrl &= ~PCI_ERR_UNC_SURPDN;
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eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, ctrl);
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}
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break;
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}
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return 0;
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}
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void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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if (pci_is_root_bus(dev->bus)) {
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hose = pci_bus_to_host(dev->bus);
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ioda_eeh_root_reset(hose, EEH_RESET_HOT);
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ioda_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
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} else {
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ioda_eeh_bridge_reset(dev, EEH_RESET_HOT);
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ioda_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
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}
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}
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/**
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* ioda_eeh_reset - Reset the indicated PE
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* @pe: EEH PE
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* @option: reset option
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*
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* Do reset on the indicated PE. For PCI bus sensitive PE,
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* we need to reset the parent p2p bridge. The PHB has to
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* be reinitialized if the p2p bridge is root bridge. For
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* PCI device sensitive PE, we will try to reset the device
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* through FLR. For now, we don't have OPAL APIs to do HARD
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* reset yet, so all reset would be SOFT (HOT) reset.
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*/
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static int ioda_eeh_reset(struct eeh_pe *pe, int option)
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{
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struct pci_controller *hose = pe->phb;
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struct pci_bus *bus;
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int ret;
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/*
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* For PHB reset, we always have complete reset. For those PEs whose
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* primary bus derived from root complex (root bus) or root port
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* (usually bus#1), we apply hot or fundamental reset on the root port.
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* For other PEs, we always have hot reset on the PE primary bus.
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*
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* Here, we have different design to pHyp, which always clear the
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* frozen state during PE reset. However, the good idea here from
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* benh is to keep frozen state before we get PE reset done completely
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* (until BAR restore). With the frozen state, HW drops illegal IO
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* or MMIO access, which can incur recrusive frozen PE during PE
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* reset. The side effect is that EEH core has to clear the frozen
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* state explicitly after BAR restore.
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*/
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if (pe->type & EEH_PE_PHB) {
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ret = ioda_eeh_phb_reset(hose, option);
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} else {
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struct pnv_phb *phb;
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s64 rc;
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/*
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* The frozen PE might be caused by PAPR error injection
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* registers, which are expected to be cleared after hitting
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* frozen PE as stated in the hardware spec. Unfortunately,
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* that's not true on P7IOC. So we have to clear it manually
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* to avoid recursive EEH errors during recovery.
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*/
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phb = hose->private_data;
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if (phb->model == PNV_PHB_MODEL_P7IOC &&
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(option == EEH_RESET_HOT ||
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option == EEH_RESET_FUNDAMENTAL)) {
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PHB_ERROR,
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OPAL_ASSERT_RESET);
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if (rc != OPAL_SUCCESS) {
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pr_warn("%s: Failure %lld clearing "
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"error injection registers\n",
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__func__, rc);
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return -EIO;
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}
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}
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bus = eeh_pe_bus_get(pe);
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if (pci_is_root_bus(bus) ||
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pci_is_root_bus(bus->parent))
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ret = ioda_eeh_root_reset(hose, option);
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else
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ret = ioda_eeh_bridge_reset(bus->self, option);
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}
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return ret;
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}
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struct pnv_eeh_ops ioda_eeh_ops = {
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.reset = ioda_eeh_reset,
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};
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@ -665,21 +665,236 @@ static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
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return ret;
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}
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static s64 pnv_eeh_phb_poll(struct pnv_phb *phb)
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{
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s64 rc = OPAL_HARDWARE;
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while (1) {
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rc = opal_pci_poll(phb->opal_id);
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if (rc <= 0)
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break;
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if (system_state < SYSTEM_RUNNING)
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udelay(1000 * rc);
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else
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msleep(rc);
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}
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return rc;
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}
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int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
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{
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struct pnv_phb *phb = hose->private_data;
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s64 rc = OPAL_HARDWARE;
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pr_debug("%s: Reset PHB#%x, option=%d\n",
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__func__, hose->global_number, option);
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/* Issue PHB complete reset request */
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if (option == EEH_RESET_FUNDAMENTAL ||
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option == EEH_RESET_HOT)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PHB_COMPLETE,
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OPAL_ASSERT_RESET);
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else if (option == EEH_RESET_DEACTIVATE)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PHB_COMPLETE,
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OPAL_DEASSERT_RESET);
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if (rc < 0)
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goto out;
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/*
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* Poll state of the PHB until the request is done
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* successfully. The PHB reset is usually PHB complete
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* reset followed by hot reset on root bus. So we also
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* need the PCI bus settlement delay.
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*/
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rc = pnv_eeh_phb_poll(phb);
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if (option == EEH_RESET_DEACTIVATE) {
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if (system_state < SYSTEM_RUNNING)
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udelay(1000 * EEH_PE_RST_SETTLE_TIME);
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else
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msleep(EEH_PE_RST_SETTLE_TIME);
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}
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out:
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if (rc != OPAL_SUCCESS)
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return -EIO;
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return 0;
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}
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static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
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{
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struct pnv_phb *phb = hose->private_data;
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s64 rc = OPAL_HARDWARE;
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pr_debug("%s: Reset PHB#%x, option=%d\n",
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__func__, hose->global_number, option);
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/*
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* During the reset deassert time, we needn't care
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* the reset scope because the firmware does nothing
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* for fundamental or hot reset during deassert phase.
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*/
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if (option == EEH_RESET_FUNDAMENTAL)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PCI_FUNDAMENTAL,
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OPAL_ASSERT_RESET);
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else if (option == EEH_RESET_HOT)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PCI_HOT,
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OPAL_ASSERT_RESET);
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else if (option == EEH_RESET_DEACTIVATE)
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rc = opal_pci_reset(phb->opal_id,
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OPAL_RESET_PCI_HOT,
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OPAL_DEASSERT_RESET);
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if (rc < 0)
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goto out;
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/* Poll state of the PHB until the request is done */
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rc = pnv_eeh_phb_poll(phb);
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if (option == EEH_RESET_DEACTIVATE)
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msleep(EEH_PE_RST_SETTLE_TIME);
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out:
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if (rc != OPAL_SUCCESS)
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return -EIO;
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return 0;
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}
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static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
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{
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struct device_node *dn = pci_device_to_OF_node(dev);
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struct eeh_dev *edev = of_node_to_eeh_dev(dn);
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int aer = edev ? edev->aer_cap : 0;
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u32 ctrl;
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pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
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__func__, pci_domain_nr(dev->bus),
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dev->bus->number, option);
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switch (option) {
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case EEH_RESET_FUNDAMENTAL:
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case EEH_RESET_HOT:
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/* Don't report linkDown event */
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if (aer) {
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eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, &ctrl);
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ctrl |= PCI_ERR_UNC_SURPDN;
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eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, ctrl);
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}
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eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
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ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
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eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
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msleep(EEH_PE_RST_HOLD_TIME);
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break;
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case EEH_RESET_DEACTIVATE:
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eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
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ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
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eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
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msleep(EEH_PE_RST_SETTLE_TIME);
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/* Continue reporting linkDown event */
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if (aer) {
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eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, &ctrl);
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ctrl &= ~PCI_ERR_UNC_SURPDN;
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eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
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4, ctrl);
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}
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break;
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}
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return 0;
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}
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void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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if (pci_is_root_bus(dev->bus)) {
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hose = pci_bus_to_host(dev->bus);
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pnv_eeh_root_reset(hose, EEH_RESET_HOT);
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pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
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} else {
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pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
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pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
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}
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}
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/**
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* pnv_eeh_reset - Reset the specified PE
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* @pe: EEH PE
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* @option: reset option
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*
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* Reset the specified PE
|
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* Do reset on the indicated PE. For PCI bus sensitive PE,
|
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* we need to reset the parent p2p bridge. The PHB has to
|
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* be reinitialized if the p2p bridge is root bridge. For
|
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* PCI device sensitive PE, we will try to reset the device
|
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* through FLR. For now, we don't have OPAL APIs to do HARD
|
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* reset yet, so all reset would be SOFT (HOT) reset.
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*/
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static int pnv_eeh_reset(struct eeh_pe *pe, int option)
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{
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struct pci_controller *hose = pe->phb;
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struct pnv_phb *phb = hose->private_data;
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int ret = -EEXIST;
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struct pci_bus *bus;
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int ret;
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if (phb->eeh_ops && phb->eeh_ops->reset)
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ret = phb->eeh_ops->reset(pe, option);
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/*
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* For PHB reset, we always have complete reset. For those PEs whose
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* primary bus derived from root complex (root bus) or root port
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* (usually bus#1), we apply hot or fundamental reset on the root port.
|
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* For other PEs, we always have hot reset on the PE primary bus.
|
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*
|
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* Here, we have different design to pHyp, which always clear the
|
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* frozen state during PE reset. However, the good idea here from
|
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* benh is to keep frozen state before we get PE reset done completely
|
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* (until BAR restore). With the frozen state, HW drops illegal IO
|
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* or MMIO access, which can incur recrusive frozen PE during PE
|
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* reset. The side effect is that EEH core has to clear the frozen
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* state explicitly after BAR restore.
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*/
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if (pe->type & EEH_PE_PHB) {
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ret = pnv_eeh_phb_reset(hose, option);
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} else {
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struct pnv_phb *phb;
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s64 rc;
|
||||
|
||||
/*
|
||||
* The frozen PE might be caused by PAPR error injection
|
||||
* registers, which are expected to be cleared after hitting
|
||||
* frozen PE as stated in the hardware spec. Unfortunately,
|
||||
* that's not true on P7IOC. So we have to clear it manually
|
||||
* to avoid recursive EEH errors during recovery.
|
||||
*/
|
||||
phb = hose->private_data;
|
||||
if (phb->model == PNV_PHB_MODEL_P7IOC &&
|
||||
(option == EEH_RESET_HOT ||
|
||||
option == EEH_RESET_FUNDAMENTAL)) {
|
||||
rc = opal_pci_reset(phb->opal_id,
|
||||
OPAL_RESET_PHB_ERROR,
|
||||
OPAL_ASSERT_RESET);
|
||||
if (rc != OPAL_SUCCESS) {
|
||||
pr_warn("%s: Failure %lld clearing "
|
||||
"error injection registers\n",
|
||||
__func__, rc);
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
|
||||
bus = eeh_pe_bus_get(pe);
|
||||
if (pci_is_root_bus(bus) ||
|
||||
pci_is_root_bus(bus->parent))
|
||||
ret = pnv_eeh_root_reset(hose, option);
|
||||
else
|
||||
ret = pnv_eeh_bridge_reset(bus->self, option);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2121,8 +2121,8 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
|
|||
*/
|
||||
if (is_kdump_kernel()) {
|
||||
pr_info(" Issue PHB reset ...\n");
|
||||
ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
|
||||
ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
|
||||
pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
|
||||
pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
|
||||
}
|
||||
|
||||
/* Remove M64 resource if we can't configure it successfully */
|
||||
|
|
|
|||
|
|
@ -78,7 +78,6 @@ struct pnv_ioda_pe {
|
|||
/* IOC dependent EEH operations */
|
||||
#ifdef CONFIG_EEH
|
||||
struct pnv_eeh_ops {
|
||||
int (*reset)(struct eeh_pe *pe, int option);
|
||||
};
|
||||
#endif /* CONFIG_EEH */
|
||||
|
||||
|
|
@ -223,6 +222,6 @@ extern void pnv_pci_init_ioda2_phb(struct device_node *np);
|
|||
extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
|
||||
__be64 *startp, __be64 *endp, bool rm);
|
||||
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
|
||||
extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option);
|
||||
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
|
||||
|
||||
#endif /* __POWERNV_PCI_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue