drm/tegra: use reset framework
Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
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ca48080a03
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@ -2,6 +2,7 @@ config DRM_TEGRA
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bool "NVIDIA Tegra DRM"
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depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
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depends on DRM
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depends on RESET_CONTROLLER
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select TEGRA_HOST1X
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select DRM_KMS_HELPER
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select DRM_KMS_FB_HELPER
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@ -8,8 +8,8 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/debugfs.h>
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#include <linux/reset.h>
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#include "dc.h"
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#include "drm.h"
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@ -712,7 +712,7 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc)
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unsigned long value;
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/* hardware initialization */
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tegra_periph_reset_deassert(dc->clk);
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reset_control_deassert(dc->rst);
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usleep_range(10000, 20000);
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if (dc->pipe)
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@ -1187,6 +1187,12 @@ static int tegra_dc_probe(struct platform_device *pdev)
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return PTR_ERR(dc->clk);
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}
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dc->rst = devm_reset_control_get(&pdev->dev, "dc");
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if (IS_ERR(dc->rst)) {
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dev_err(&pdev->dev, "failed to get reset\n");
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return PTR_ERR(dc->rst);
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}
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err = clk_prepare_enable(dc->clk);
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if (err < 0)
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return err;
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@ -19,6 +19,8 @@
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fixed.h>
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struct reset_control;
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struct tegra_fb {
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struct drm_framebuffer base;
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struct tegra_bo **planes;
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@ -93,6 +95,7 @@ struct tegra_dc {
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int pipe;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *regs;
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int irq;
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@ -11,6 +11,7 @@
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#include <linux/host1x.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/tegra-powergate.h>
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#include "drm.h"
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@ -22,6 +23,8 @@ struct gr3d {
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struct host1x_channel *channel;
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struct clk *clk_secondary;
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struct clk *clk;
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struct reset_control *rst_secondary;
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struct reset_control *rst;
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DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
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};
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@ -255,12 +258,25 @@ static int gr3d_probe(struct platform_device *pdev)
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return PTR_ERR(gr3d->clk);
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}
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gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
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if (IS_ERR(gr3d->rst)) {
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dev_err(&pdev->dev, "cannot get reset\n");
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return PTR_ERR(gr3d->rst);
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}
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if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
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gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
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if (IS_ERR(gr3d->clk)) {
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dev_err(&pdev->dev, "cannot get secondary clock\n");
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return PTR_ERR(gr3d->clk);
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}
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gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
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"3d2");
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if (IS_ERR(gr3d->rst_secondary)) {
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dev_err(&pdev->dev, "cannot get secondary reset\n");
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return PTR_ERR(gr3d->rst_secondary);
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}
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}
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err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk);
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@ -8,10 +8,10 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk/tegra.h>
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#include <linux/debugfs.h>
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#include <linux/hdmi.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include "hdmi.h"
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#include "drm.h"
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@ -49,6 +49,7 @@ struct tegra_hdmi {
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struct clk *clk_parent;
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struct clk *clk;
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struct reset_control *rst;
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const struct tegra_hdmi_config *config;
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@ -731,9 +732,9 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
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return err;
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}
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tegra_periph_reset_assert(hdmi->clk);
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reset_control_assert(hdmi->rst);
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usleep_range(1000, 2000);
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tegra_periph_reset_deassert(hdmi->clk);
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reset_control_deassert(hdmi->rst);
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tegra_dc_writel(dc, VSYNC_H_POSITION(1),
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DC_DISP_DISP_TIMING_OPTIONS);
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@ -912,7 +913,7 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
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{
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struct tegra_hdmi *hdmi = to_hdmi(output);
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tegra_periph_reset_assert(hdmi->clk);
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reset_control_assert(hdmi->rst);
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clk_disable(hdmi->clk);
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regulator_disable(hdmi->pll);
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@ -1338,6 +1339,12 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
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return PTR_ERR(hdmi->clk);
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}
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hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
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if (IS_ERR(hdmi->rst)) {
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dev_err(&pdev->dev, "failed to get reset\n");
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return PTR_ERR(hdmi->rst);
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}
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err = clk_prepare(hdmi->clk);
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if (err < 0)
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return err;
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