ARC: Checksum/byteorder/swab routines
TBD: do_csum still needs to be written in asm Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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Vineet Gupta
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARC_BYTEORDER_H
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#define __ASM_ARC_BYTEORDER_H
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#include <linux/byteorder/big_endian.h>
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#else
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#include <linux/byteorder/little_endian.h>
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#endif
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#endif /* ASM_ARC_BYTEORDER_H */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Joern Rennecke <joern.rennecke@embecosm.com>: Jan 2012
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* -Insn Scheduling improvements to csum core routines.
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* = csum_fold( ) largely derived from ARM version.
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* = ip_fast_cum( ) to have module scheduling
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* -gcc 4.4.x broke networking. Alias analysis needed to be primed.
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* worked around by adding memory clobber to ip_fast_csum( )
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*
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* vineetg: May 2010
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* -Rewrote ip_fast_cscum( ) and csum_fold( ) with fast inline asm
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*/
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#ifndef _ASM_ARC_CHECKSUM_H
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#define _ASM_ARC_CHECKSUM_H
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/*
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* Fold a partial checksum
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*
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* The 2 swords comprising the 32bit sum are added, any carry to 16th bit
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* added back and final sword result inverted.
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*/
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static inline __sum16 csum_fold(__wsum s)
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{
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unsigned r = s << 16 | s >> 16; /* ror */
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s = ~s;
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s -= r;
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return s >> 16;
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}
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/*
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* This is a version of ip_compute_csum() optimized for IP headers,
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* which always checksum on 4 octet boundaries.
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*/
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static inline __sum16
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ip_fast_csum(const void *iph, unsigned int ihl)
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{
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const void *ptr = iph;
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unsigned int tmp, tmp2, sum;
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__asm__(
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" ld.ab %0, [%3, 4] \n"
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" ld.ab %2, [%3, 4] \n"
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" sub %1, %4, 2 \n"
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" lsr.f lp_count, %1, 1 \n"
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" bcc 0f \n"
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" add.f %0, %0, %2 \n"
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" ld.ab %2, [%3, 4] \n"
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"0: lp 1f \n"
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" ld.ab %1, [%3, 4] \n"
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" adc.f %0, %0, %2 \n"
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" ld.ab %2, [%3, 4] \n"
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" adc.f %0, %0, %1 \n"
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"1: adc.f %0, %0, %2 \n"
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" add.cs %0,%0,1 \n"
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: "=&r"(sum), "=r"(tmp), "=&r"(tmp2), "+&r" (ptr)
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: "r"(ihl)
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: "cc", "lp_count", "memory");
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return csum_fold(sum);
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}
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/*
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* TCP pseudo Header is 12 bytes:
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* SA [4], DA [4], zeroes [1], Proto[1], TCP Seg(hdr+data) Len [2]
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*/
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static inline __wsum
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csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
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unsigned short proto, __wsum sum)
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{
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__asm__ __volatile__(
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" add.f %0, %0, %1 \n"
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" adc.f %0, %0, %2 \n"
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" adc.f %0, %0, %3 \n"
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" adc.f %0, %0, %4 \n"
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" adc %0, %0, 0 \n"
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: "+&r"(sum)
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: "r"(saddr), "r"(daddr),
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#ifdef CONFIG_CPU_BIG_ENDIAN
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"r"(len),
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#else
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"r"(len << 8),
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#endif
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"r"(htons(proto))
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: "cc");
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return sum;
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}
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#define csum_fold csum_fold
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#define ip_fast_csum ip_fast_csum
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#define csum_tcpudp_nofold csum_tcpudp_nofold
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#include <asm-generic/checksum.h>
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#endif /* _ASM_ARC_CHECKSUM_H */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: May 2011
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* -Support single cycle endian-swap insn in ARC700 4.10
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*
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* vineetg: June 2009
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* -Better htonl implementation (5 instead of 9 ALU instructions)
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* -Hardware assisted single cycle bswap (Use Case of ARC custom instrn)
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*/
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#ifndef __ASM_ARC_SWAB_H
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#define __ASM_ARC_SWAB_H
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#include <linux/types.h>
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/* Native single cycle endian swap insn */
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#ifdef CONFIG_ARC_HAS_SWAPE
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#define __arch_swab32(x) \
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({ \
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unsigned int tmp = x; \
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__asm__( \
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" swape %0, %1 \n" \
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: "=r" (tmp) \
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: "r" (tmp)); \
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tmp; \
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})
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#else
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/* Several ways of Endian-Swap Emulation for ARC
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* 0: kernel generic
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* 1: ARC optimised "C"
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* 2: ARC Custom instruction
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*/
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#define ARC_BSWAP_TYPE 1
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#if (ARC_BSWAP_TYPE == 1) /******* Software only ********/
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/* The kernel default implementation of htonl is
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* return x<<24 | x>>24 |
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* (x & (__u32)0x0000ff00UL)<<8 | (x & (__u32)0x00ff0000UL)>>8;
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*
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* This generates 9 instructions on ARC (excluding the ld/st)
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*
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* 8051fd8c: ld r3,[r7,20] ; Mem op : Get the value to be swapped
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* 8051fd98: asl r5,r3,24 ; get 3rd Byte
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* 8051fd9c: lsr r2,r3,24 ; get 0th Byte
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* 8051fda0: and r4,r3,0xff00
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* 8051fda8: asl r4,r4,8 ; get 1st Byte
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* 8051fdac: and r3,r3,0x00ff0000
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* 8051fdb4: or r2,r2,r5 ; combine 0th and 3rd Bytes
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* 8051fdb8: lsr r3,r3,8 ; 2nd Byte at correct place in Dst Reg
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* 8051fdbc: or r2,r2,r4 ; combine 0,3 Bytes with 1st Byte
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* 8051fdc0: or r2,r2,r3 ; combine 0,3,1 Bytes with 2nd Byte
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* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
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*
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* Joern suggested a better "C" algorithm which is great since
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* (1) It is portable to any architecure
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* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
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*/
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#define __arch_swab32(x) \
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({ unsigned long __in = (x), __tmp; \
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__tmp = __in << 8 | __in >> 24; /* ror tmp,in,24 */ \
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__in = __in << 24 | __in >> 8; /* ror in,in,8 */ \
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__tmp ^= __in; \
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__tmp &= 0xff00ff; \
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__tmp ^ __in; \
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})
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#elif (ARC_BSWAP_TYPE == 2) /* Custom single cycle bwap instruction */
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#define __arch_swab32(x) \
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({ \
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unsigned int tmp = x; \
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__asm__( \
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" .extInstruction bswap, 7, 0x00, SUFFIX_NONE, SYNTAX_2OP \n"\
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" bswap %0, %1 \n"\
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: "=r" (tmp) \
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: "r" (tmp)); \
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tmp; \
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})
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#endif /* ARC_BSWAP_TYPE=zzz */
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#endif /* CONFIG_ARC_HAS_SWAPE */
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#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
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#define __SWAB_64_THRU_32__
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#endif
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#endif
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