phy: qcom-ufs: add support for 14nm phy
This change adds a support for a 14nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
This commit is contained in:
Yaniv Gardi
Christoph Hellwig
parent
39e794bff7
commit
ca14ab55fb
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@ -36,3 +36,4 @@ obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
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obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
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obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
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obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
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@ -0,0 +1,201 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include "phy-qcom-ufs-qmp-14nm.h"
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#define UFS_PHY_NAME "ufs_phy_qmp_14nm"
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#define UFS_PHY_VDDA_PHY_UV (925000)
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static
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int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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bool is_rate_B)
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{
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int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
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int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
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int err;
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err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
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tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
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if (err)
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dev_err(ufs_qcom_phy->dev,
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"%s: ufs_qcom_phy_calibrate() failed %d\n",
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__func__, err);
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return err;
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}
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static
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void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
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{
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phy_common->quirks =
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UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
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}
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static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
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{
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struct ufs_qcom_phy_qmp_14nm *phy = phy_get_drvdata(generic_phy);
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struct ufs_qcom_phy *phy_common = &phy->common_cfg;
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int err;
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err = ufs_qcom_phy_init_clks(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n",
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__func__, err);
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goto out;
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}
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err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common);
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if (err) {
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dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n",
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__func__, err);
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goto out;
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}
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phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
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phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
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ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
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out:
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return err;
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}
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static
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void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
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{
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writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
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/*
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* Before any transactions involving PHY, ensure PHY knows
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* that it's analog rail is powered ON (or OFF).
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*/
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mb();
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}
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static inline
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void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
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{
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/*
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* 14nm PHY does not have TX_LANE_ENABLE register.
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* Implement this function so as not to propagate error to caller.
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*/
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}
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static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
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{
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u32 tmp;
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tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
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tmp &= ~MASK_SERDES_START;
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tmp |= (1 << OFFSET_SERDES_START);
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writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
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/* Ensure register value is committed */
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mb();
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}
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static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
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{
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int err = 0;
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u32 val;
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err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
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val, (val & MASK_PCS_READY), 10, 1000000);
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if (err)
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dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
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__func__, err);
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return err;
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}
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static struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
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.init = ufs_qcom_phy_qmp_14nm_init,
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.exit = ufs_qcom_phy_exit,
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.power_on = ufs_qcom_phy_power_on,
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.power_off = ufs_qcom_phy_power_off,
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.owner = THIS_MODULE,
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};
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static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
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.calibrate_phy = ufs_qcom_phy_qmp_14nm_phy_calibrate,
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.start_serdes = ufs_qcom_phy_qmp_14nm_start_serdes,
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.is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
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.set_tx_lane_enable = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
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.power_control = ufs_qcom_phy_qmp_14nm_power_control,
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};
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static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy;
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struct ufs_qcom_phy_qmp_14nm *phy;
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int err = 0;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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dev_err(dev, "%s: failed to allocate phy\n", __func__);
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err = -ENOMEM;
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goto out;
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}
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generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
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&ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
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if (!generic_phy) {
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dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
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__func__);
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err = -EIO;
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goto out;
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}
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phy_set_drvdata(generic_phy, phy);
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strlcpy(phy->common_cfg.name, UFS_PHY_NAME,
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sizeof(phy->common_cfg.name));
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out:
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return err;
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}
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static int ufs_qcom_phy_qmp_14nm_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct phy *generic_phy = to_phy(dev);
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struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
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int err = 0;
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err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy);
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if (err)
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dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n",
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__func__, err);
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return err;
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}
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static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
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{.compatible = "qcom,ufs-phy-qmp-14nm"},
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{},
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};
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MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
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static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
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.probe = ufs_qcom_phy_qmp_14nm_probe,
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.remove = ufs_qcom_phy_qmp_14nm_remove,
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.driver = {
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.of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
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.name = "ufs_qcom_phy_qmp_14nm",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
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MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,177 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef UFS_QCOM_PHY_QMP_14NM_H_
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#define UFS_QCOM_PHY_QMP_14NM_H_
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#include "phy-qcom-ufs-i.h"
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/* QCOM UFS PHY control registers */
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#define COM_OFF(x) (0x000 + x)
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#define PHY_OFF(x) (0xC00 + x)
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#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
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#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
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/* UFS PHY QSERDES COM registers */
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#define QSERDES_COM_BG_TIMER COM_OFF(0x0C)
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34)
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#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C)
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#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x4C)
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#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x50)
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#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0x54)
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#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0x58)
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#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0x5C)
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#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0x60)
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#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78)
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#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C)
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#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84)
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#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88)
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#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90)
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#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94)
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#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC)
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#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4)
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#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8)
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#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC)
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#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0)
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#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4)
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#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC)
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#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0)
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#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4)
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#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8)
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#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC)
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#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0)
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#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108)
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#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C)
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#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110)
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#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114)
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#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124)
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#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128)
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#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C)
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#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130)
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#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134)
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#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138)
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#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144)
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#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148)
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#define QSERDES_COM_CLK_SELECT COM_OFF(0x174)
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#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178)
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#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184)
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#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C)
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#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194)
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#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C)
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#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC)
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/* UFS PHY registers */
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#define UFS_PHY_PHY_START PHY_OFF(0x00)
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#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
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#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168)
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/* UFS PHY TX registers */
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#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0, 0x68)
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#define QSERDES_TX_LANE_MODE TX_OFF(0, 0x94)
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/* UFS PHY RX registers */
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#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x40)
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#define QSERDES_RX_RX_TERM_BW RX_OFF(0, 0x90)
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#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0, 0xC4)
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#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0, 0xC8)
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#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0, 0xCC)
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#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0, 0xD0)
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#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xD8)
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#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0, 0x114)
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#define QSERDES_RX_SIGDET_LVL RX_OFF(0, 0x118)
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#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x11C)
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#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0, 0x12C)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This structure represents the 14nm specific phy.
|
||||||
|
* common_cfg MUST remain the first field in this structure
|
||||||
|
* in case extra fields are added. This way, when calling
|
||||||
|
* get_ufs_qcom_phy() of generic phy, we can extract the
|
||||||
|
* common phy structure (struct ufs_qcom_phy) out of it
|
||||||
|
* regardless of the relevant specific phy.
|
||||||
|
*/
|
||||||
|
struct ufs_qcom_phy_qmp_14nm {
|
||||||
|
struct ufs_qcom_phy common_cfg;
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x06),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
|
||||||
|
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x02),
|
||||||
|
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x02),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0F),
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
|
||||||
|
UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54),
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue