dma-mapping: turn dma_cache_sync into a dma_map_ops method
After we removed all the dead wood it turns out only two architectures actually implement dma_cache_sync as a real op: mips and parisc. Add a cache_sync method to struct dma_map_ops and implement it for the mips defualt DMA ops, and the parisc pa11 ops. Note that arm, arc and openrisc support DMA_ATTR_NON_CONSISTENT, but never provided a functional dma_cache_sync implementations, which seems somewhat odd. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
This commit is contained in:
parent
e0c6584df9
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c9eb6172c3
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@ -8,6 +8,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return dma_ops;
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}
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#define dma_cache_sync(dev, va, size, dir) ((void)0)
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#endif /* _ALPHA_DMA_MAPPING_H */
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@ -16,10 +16,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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}
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#endif
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif
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@ -14,10 +14,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &frv_dma_ops;
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}
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static inline
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void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif /* _ASM_DMA_MAPPING_H */
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@ -37,9 +37,6 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return dma_ops;
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}
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extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction);
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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@ -44,10 +44,4 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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return daddr;
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}
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static inline void
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dma_cache_sync (struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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#endif /* _ASM_IA64_DMA_MAPPING_H */
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@ -13,11 +13,6 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &dma_noop_ops;
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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@ -8,10 +8,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &m68k_dma_ops;
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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/* we use coherent allocation, so not much to do here. */
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}
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#endif /* _M68K_DMA_MAPPING_H */
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@ -8,14 +8,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &metag_dma_ops;
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}
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/*
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* dma_alloc_attrs() always returns non-cacheable memory, so there's no need to
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* do any flushing here.
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*/
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif
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@ -25,9 +25,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &dma_direct_ops;
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif /* _ASM_MICROBLAZE_DMA_MAPPING_H */
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@ -26,9 +26,6 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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static inline void dma_mark_clean(void *addr, size_t size) {}
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extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction);
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#define arch_setup_dma_ops arch_setup_dma_ops
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static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
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u64 size, const struct iommu_ops *iommu,
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@ -383,7 +383,7 @@ static int mips_dma_supported(struct device *dev, u64 mask)
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return plat_dma_supported(dev, mask);
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}
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void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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static void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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@ -392,8 +392,6 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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__dma_sync_virtual(vaddr, size, direction);
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}
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EXPORT_SYMBOL(dma_cache_sync);
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static const struct dma_map_ops mips_default_dma_map_ops = {
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.alloc = mips_dma_alloc_coherent,
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.free = mips_dma_free_coherent,
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@ -407,7 +405,8 @@ static const struct dma_map_ops mips_default_dma_map_ops = {
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.sync_sg_for_cpu = mips_dma_sync_sg_for_cpu,
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.sync_sg_for_device = mips_dma_sync_sg_for_device,
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.mapping_error = mips_dma_mapping_error,
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.dma_supported = mips_dma_supported
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.dma_supported = mips_dma_supported,
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.cache_sync = mips_dma_cache_sync,
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};
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const struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
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@ -18,10 +18,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &mn10300_dma_ops;
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}
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static inline
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void dma_cache_sync(void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif
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@ -17,13 +17,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return &nios2_dma_ops;
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}
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/*
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* dma_alloc_attrs() always returns non-cacheable memory, so there's no need to
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* do any flushing here.
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*/
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif /* _ASM_NIOS2_DMA_MAPPING_H */
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@ -32,14 +32,6 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return hppa_dma_ops;
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}
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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if (hppa_dma_ops->sync_single_for_cpu)
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flush_kernel_dcache_range((unsigned long)vaddr, size);
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}
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static inline void *
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parisc_walk_tree(struct device *dev)
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{
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@ -571,6 +571,12 @@ static void pa11_dma_sync_sg_for_device(struct device *dev, struct scatterlist *
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flush_kernel_vmap_range(sg_virt(sg), sg->length);
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}
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static void pa11_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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flush_kernel_dcache_range((unsigned long)vaddr, size);
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}
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const struct dma_map_ops pcxl_dma_ops = {
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.dma_supported = pa11_dma_supported,
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.alloc = pa11_dma_alloc,
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.sync_single_for_device = pa11_dma_sync_single_for_device,
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.sync_sg_for_cpu = pa11_dma_sync_sg_for_cpu,
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.sync_sg_for_device = pa11_dma_sync_sg_for_device,
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.cache_sync = pa11_dma_cache_sync,
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};
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static void *pcx_dma_alloc(struct device *dev, size_t size,
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.sync_single_for_device = pa11_dma_sync_single_for_device,
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.sync_sg_for_cpu = pa11_dma_sync_sg_for_cpu,
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.sync_sg_for_device = pa11_dma_sync_sg_for_device,
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.cache_sync = pa11_dma_cache_sync,
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};
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#define ARCH_HAS_DMA_MMAP_COHERENT
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_DMA_MAPPING_H */
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return &dma_noop_ops;
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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return dma_ops;
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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/* arch/sh/mm/consistent.c */
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extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addr, gfp_t flag,
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unsigned long attrs);
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#include <linux/mm.h>
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#include <linux/dma-debug.h>
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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/* Since dma_{alloc,free}_noncoherent() allocated coherent memory, this
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* routine can be a nop.
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*/
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}
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extern const struct dma_map_ops *dma_ops;
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extern const struct dma_map_ops pci32_dma_ops;
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#define HAVE_ARCH_DMA_SET_MASK 1
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int dma_set_mask(struct device *dev, u64 mask);
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/*
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* dma_alloc_attrs() always returns non-cacheable memory, so there's no need to
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* do any flushing here.
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*/
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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#endif /* _ASM_TILE_DMA_MAPPING_H */
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static inline void dma_mark_clean(void *addr, size_t size) {}
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static inline void dma_cache_sync(struct device *dev, void *vaddr,
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size_t size, enum dma_data_direction direction)
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{
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}
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#endif /* __KERNEL__ */
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#endif
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}
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#endif /* CONFIG_X86_DMA_REMAP */
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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}
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static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
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gfp_t gfp)
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{
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return &xtensa_dma_map_ops;
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}
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static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return (dma_addr_t)paddr;
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void (*sync_sg_for_device)(struct device *dev,
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struct scatterlist *sg, int nents,
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enum dma_data_direction dir);
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void (*cache_sync)(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction);
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int (*mapping_error)(struct device *dev, dma_addr_t dma_addr);
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int (*dma_supported)(struct device *dev, u64 mask);
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#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
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#define dma_map_page(d, p, o, s, r) dma_map_page_attrs(d, p, o, s, r, 0)
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#define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0)
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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const struct dma_map_ops *ops = get_dma_ops(dev);
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BUG_ON(!valid_dma_direction(dir));
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if (ops->cache_sync)
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ops->cache_sync(dev, vaddr, size, dir);
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}
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extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
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void *cpu_addr, dma_addr_t dma_addr, size_t size);
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