irqchip fixes for 5.4, take #1
- Add retrigger support to Amazon's al-fic driver - Add SAM9X60 support to Atmel's AIC5 irqchip - Fix GICv3 maximum interrupt calculation - Convert SiFive's PLIC to the fasteoi IRQ flow -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl2TG74PHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDaCsQAJNOv7mE6d52LPA5e9Vx/HP2shKjTNdpyD4C vi5tE7bvQ7VKZuoQ7S7zF3RrrG4z/Fth7Qe0v2T+2OecXBlejB64z642CIY0aVhh SPWf1pUimHCosQnY2xEi/8Db6i0ZzlaYo5FlhTK+OKnaEuhXdoGVRVxyk+AhSq5n jruA+GO/V2OfbbEkmXwJViEF6w0jzuQEaJIm9M2Z0S5QG3tsnC2+OrsBDJZqxT9/ 7Jvx6IB/dk3yuQC7byT7bBLlEnw8nPe8yVua8N8LtTiZi/JjpfIl3qgXJx/h9iyc jkuOZn2GpWwzi/i6SFQLTVKxeChqPTa61tTX67Y4LnCF8iOhzNY/Ev9OqLztTW+J tVYaW6zp/shKOze1GmDXcG/9OMgQ7prR05nK2hnbGaI+dRHiw+zvgS0Sd6pPilDx V/FtdCCD3JkKUgu+O6qBkJZb1RXbwGs7RdpkWHaxuYu3F47lGkoWpKPc689DWXyI FL9bqcr3i4hPfWn4a/fVjYBvov91SCWRLWhhB5ViZ59ldE7WG2A5g62X9f6+mUk8 PrPFT0eldnCzeEf81suj7X0Phv8ftzigTm9ByJh8AV1/uuBi+AKjsYxDsp7CxMPj 9YYozRHakyp0c9hpwXRjozlVGKC6JpZLBBFga5+zI62IoIdEJCdnGFfdbxcqPRJE oCXSSXXG =AV7P -----END PGP SIGNATURE----- Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip fixes from Marc Zyngier: - Add retrigger support to Amazon's al-fic driver - Add SAM9X60 support to Atmel's AIC5 irqchip - Fix GICv3 maximum interrupt calculation - Convert SiFive's PLIC to the fasteoi IRQ flow
This commit is contained in:
Thomas Gleixner
commit
c9b59181c2
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@ -1,8 +1,11 @@
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* Advanced Interrupt Controller (AIC)
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Required properties:
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- compatible: Should be "atmel,<chip>-aic"
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<chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4"
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- compatible: Should be:
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- "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
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"sama5d3" or "sama5d4"
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- "microchip,<chip>-aic" where <chip> can be "sam9x60"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
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The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
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@ -15,6 +15,7 @@
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/* FIC Registers */
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#define AL_FIC_CAUSE 0x00
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#define AL_FIC_SET_CAUSE 0x08
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#define AL_FIC_MASK 0x10
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#define AL_FIC_CONTROL 0x28
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@ -126,6 +127,16 @@ static void al_fic_irq_handler(struct irq_desc *desc)
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chained_irq_exit(irqchip, desc);
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}
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static int al_fic_irq_retrigger(struct irq_data *data)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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struct al_fic *fic = gc->private;
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writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
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return 1;
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}
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static int al_fic_register(struct device_node *node,
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struct al_fic *fic)
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{
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@ -159,6 +170,7 @@ static int al_fic_register(struct device_node *node,
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gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit;
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gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit;
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gc->chip_types->chip.irq_set_type = al_fic_irq_set_type;
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gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger;
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gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE;
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gc->private = fic;
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@ -313,6 +313,7 @@ static void __init sama5d3_aic_irq_fixup(void)
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static const struct of_device_id aic5_irq_fixups[] __initconst = {
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{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
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{ .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
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{ .compatible = "microchip,sam9x60", .data = sama5d3_aic_irq_fixup },
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{ /* sentinel */ },
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};
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@ -390,3 +391,12 @@ static int __init sama5d4_aic5_of_init(struct device_node *node,
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return aic5_of_init(node, parent, NR_SAMA5D4_IRQS);
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}
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IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
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#define NR_SAM9X60_IRQS 50
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static int __init sam9x60_aic5_of_init(struct device_node *node,
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struct device_node *parent)
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{
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return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
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}
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IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
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@ -59,7 +59,7 @@ static struct gic_chip_data gic_data __read_mostly;
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static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
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#define GIC_LINE_NR max(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
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#define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
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#define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
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/*
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@ -97,7 +97,7 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
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}
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}
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static void plic_irq_enable(struct irq_data *d)
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static void plic_irq_unmask(struct irq_data *d)
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{
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unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
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cpu_online_mask);
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@ -106,7 +106,7 @@ static void plic_irq_enable(struct irq_data *d)
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plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
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}
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static void plic_irq_disable(struct irq_data *d)
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static void plic_irq_mask(struct irq_data *d)
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{
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plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
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}
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@ -125,10 +125,8 @@ static int plic_set_affinity(struct irq_data *d,
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if (cpu >= nr_cpu_ids)
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return -EINVAL;
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if (!irqd_irq_disabled(d)) {
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plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
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plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
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}
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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@ -136,14 +134,18 @@ static int plic_set_affinity(struct irq_data *d,
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}
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#endif
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static void plic_irq_eoi(struct irq_data *d)
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{
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struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
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writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
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}
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static struct irq_chip plic_chip = {
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.name = "SiFive PLIC",
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/*
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* There is no need to mask/unmask PLIC interrupts. They are "masked"
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* by reading claim and "unmasked" when writing it back.
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*/
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.irq_enable = plic_irq_enable,
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.irq_disable = plic_irq_disable,
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.irq_mask = plic_irq_mask,
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.irq_unmask = plic_irq_unmask,
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.irq_eoi = plic_irq_eoi,
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#ifdef CONFIG_SMP
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.irq_set_affinity = plic_set_affinity,
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#endif
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@ -152,7 +154,7 @@ static struct irq_chip plic_chip = {
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static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &plic_chip, handle_simple_irq);
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irq_set_chip_and_handler(irq, &plic_chip, handle_fasteoi_irq);
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irq_set_chip_data(irq, NULL);
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irq_set_noprobe(irq);
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return 0;
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@ -188,7 +190,6 @@ static void plic_handle_irq(struct pt_regs *regs)
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hwirq);
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else
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generic_handle_irq(irq);
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writel(hwirq, claim);
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}
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csr_set(sie, SIE_SEIE);
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}
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