[PATCH] cell: enable pause(0) in cpu_idle
This patch enables support for pause(0) power management state for the Cell Broadband Processor, which is import for power efficient operation. The pervasive infrastructure will in the future enable us to introduce more functionality specific to the Cell's pervasive unit. From: Maximino Aguilar <maguilar@us.ibm.com> Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Arnd Bergmann
Paul Mackerras
parent
017e0fad3e
commit
c902be71dc
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@ -273,7 +273,7 @@ struct cpu_spec cpu_specs[] = {
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.oprofile_model = &op_model_power4,
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#endif
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},
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{ /* BE DD1.x */
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{ /* Cell Broadband Engine */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00700000,
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.cpu_name = "Cell Broadband Engine",
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@ -230,8 +230,10 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
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void system_reset_exception(struct pt_regs *regs)
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{
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/* See if any machine dependent calls */
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if (ppc_md.system_reset_exception)
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ppc_md.system_reset_exception(regs);
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if (ppc_md.system_reset_exception) {
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if (ppc_md.system_reset_exception(regs))
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return;
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}
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die("System Reset", regs, SIGABRT);
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@ -1,4 +1,6 @@
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obj-y += interrupt.o iommu.o setup.o spider-pic.o
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obj-y += pervasive.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_SPU_FS) += spufs/ spu_base.o
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builtin-spufs-$(CONFIG_SPU_FS) += spu_syscalls.o
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@ -0,0 +1,229 @@
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/*
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* CBE Pervasive Monitor and Debug
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*
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* (C) Copyright IBM Corporation 2005
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*
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* Authors: Maximino Aguilar (maguilar@us.ibm.com)
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* Michael N. Day (mnday@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/percpu.h>
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#include <linux/types.h>
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#include <linux/kallsyms.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/pgtable.h>
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#include <asm/reg.h>
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#include "pervasive.h"
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static DEFINE_SPINLOCK(cbe_pervasive_lock);
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struct cbe_pervasive {
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struct pmd_regs __iomem *regs;
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unsigned int thread;
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};
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/* can't use per_cpu from setup_arch */
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static struct cbe_pervasive cbe_pervasive[NR_CPUS];
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static void __init cbe_enable_pause_zero(void)
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{
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unsigned long thread_switch_control;
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unsigned long temp_register;
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struct cbe_pervasive *p;
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int thread;
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spin_lock_irq(&cbe_pervasive_lock);
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p = &cbe_pervasive[smp_processor_id()];
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if (!cbe_pervasive->regs)
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goto out;
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pr_debug("Power Management: CPU %d\n", smp_processor_id());
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/* Enable Pause(0) control bit */
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temp_register = in_be64(&p->regs->pm_control);
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out_be64(&p->regs->pm_control,
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temp_register|PMD_PAUSE_ZERO_CONTROL);
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/* Enable DEC and EE interrupt request */
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thread_switch_control = mfspr(SPRN_TSC_CELL);
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thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
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switch ((mfspr(SPRN_CTRLF) & CTRL_CT)) {
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case CTRL_CT0:
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thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
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thread = 0;
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break;
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case CTRL_CT1:
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thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
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thread = 1;
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break;
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default:
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printk(KERN_WARNING "%s: unknown configuration\n",
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__FUNCTION__);
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thread = -1;
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break;
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}
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if (p->thread != thread)
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printk(KERN_WARNING "%s: device tree inconsistant, "
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"cpu %i: %d/%d\n", __FUNCTION__,
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smp_processor_id(),
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p->thread, thread);
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mtspr(SPRN_TSC_CELL, thread_switch_control);
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out:
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spin_unlock_irq(&cbe_pervasive_lock);
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}
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static void cbe_idle(void)
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{
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unsigned long ctrl;
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cbe_enable_pause_zero();
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while (1) {
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if (!need_resched()) {
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local_irq_disable();
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while (!need_resched()) {
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/* go into low thread priority */
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HMT_low();
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/*
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* atomically disable thread execution
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* and runlatch.
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* External and Decrementer exceptions
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* are still handled when the thread
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* is disabled but now enter in
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* cbe_system_reset_exception()
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*/
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ctrl = mfspr(SPRN_CTRLF);
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ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
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mtspr(SPRN_CTRLT, ctrl);
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}
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/* restore thread prio */
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HMT_medium();
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local_irq_enable();
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}
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/*
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* turn runlatch on again before scheduling the
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* process we just woke up
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*/
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ppc64_runlatch_on();
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preempt_enable_no_resched();
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schedule();
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preempt_disable();
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}
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}
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int cbe_system_reset_exception(struct pt_regs *regs)
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{
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switch (regs->msr & SRR1_WAKEMASK) {
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case SRR1_WAKEEE:
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do_IRQ(regs);
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break;
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case SRR1_WAKEDEC:
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timer_interrupt(regs);
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break;
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case SRR1_WAKEMT:
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/* no action required */
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break;
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default:
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/* do system reset */
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return 0;
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}
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/* everything handled */
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return 1;
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}
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static int __init cbe_find_pmd_mmio(int cpu, struct cbe_pervasive *p)
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{
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struct device_node *node;
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unsigned int *int_servers;
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char *addr;
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unsigned long real_address;
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unsigned int size;
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struct pmd_regs __iomem *pmd_mmio_area;
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int hardid, thread;
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int proplen;
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pmd_mmio_area = NULL;
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hardid = get_hard_smp_processor_id(cpu);
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for (node = NULL; (node = of_find_node_by_type(node, "cpu"));) {
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int_servers = (void *) get_property(node,
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"ibm,ppc-interrupt-server#s", &proplen);
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if (!int_servers) {
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printk(KERN_WARNING "%s misses "
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"ibm,ppc-interrupt-server#s property",
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node->full_name);
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continue;
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}
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for (thread = 0; thread < proplen / sizeof (int); thread++) {
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if (hardid == int_servers[thread]) {
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addr = get_property(node, "pervasive", NULL);
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goto found;
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}
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}
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}
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printk(KERN_WARNING "%s: CPU %d not found\n", __FUNCTION__, cpu);
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return -EINVAL;
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found:
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real_address = *(unsigned long*) addr;
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addr += sizeof (unsigned long);
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size = *(unsigned int*) addr;
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pr_debug("pervasive area for CPU %d at %lx, size %x\n",
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cpu, real_address, size);
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p->regs = __ioremap(real_address, size, _PAGE_NO_CACHE);
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p->thread = thread;
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return 0;
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}
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void __init cell_pervasive_init(void)
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{
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struct cbe_pervasive *p;
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int cpu;
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int ret;
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if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
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return;
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for_each_cpu(cpu) {
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p = &cbe_pervasive[cpu];
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ret = cbe_find_pmd_mmio(cpu, p);
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if (ret)
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return;
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}
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ppc_md.idle_loop = cbe_idle;
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ppc_md.system_reset_exception = cbe_system_reset_exception;
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}
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@ -0,0 +1,62 @@
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/*
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* Cell Pervasive Monitor and Debug interface and HW structures
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*
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* (C) Copyright IBM Corporation 2005
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*
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* Authors: Maximino Aguilar (maguilar@us.ibm.com)
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* David J. Erb (djerb@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef PERVASIVE_H
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#define PERVASIVE_H
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struct pmd_regs {
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u8 pad_0x0000_0x0800[0x0800 - 0x0000]; /* 0x0000 */
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/* Thermal Sensor Registers */
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u64 ts_ctsr1; /* 0x0800 */
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u64 ts_ctsr2; /* 0x0808 */
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u64 ts_mtsr1; /* 0x0810 */
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u64 ts_mtsr2; /* 0x0818 */
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u64 ts_itr1; /* 0x0820 */
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u64 ts_itr2; /* 0x0828 */
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u64 ts_gitr; /* 0x0830 */
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u64 ts_isr; /* 0x0838 */
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u64 ts_imr; /* 0x0840 */
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u64 tm_cr1; /* 0x0848 */
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u64 tm_cr2; /* 0x0850 */
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u64 tm_simr; /* 0x0858 */
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u64 tm_tpr; /* 0x0860 */
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u64 tm_str1; /* 0x0868 */
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u64 tm_str2; /* 0x0870 */
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u64 tm_tsr; /* 0x0878 */
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/* Power Management */
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u64 pm_control; /* 0x0880 */
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#define PMD_PAUSE_ZERO_CONTROL 0x10000
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u64 pm_status; /* 0x0888 */
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/* Time Base Register */
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u64 tbr; /* 0x0890 */
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u8 pad_0x0898_0x1000 [0x1000 - 0x0898]; /* 0x0898 */
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};
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void __init cell_pervasive_init(void);
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#endif
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@ -49,6 +49,7 @@
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#include "interrupt.h"
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#include "iommu.h"
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#include "pervasive.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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@ -165,6 +166,7 @@ static void __init cell_setup_arch(void)
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init_pci_config_tokens();
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find_and_init_phbs();
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spider_init_IRQ();
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cell_pervasive_init();
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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@ -51,6 +51,8 @@
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#include <asm/udbg.h>
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#include <asm/firmware.h>
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#include "ras.h"
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static unsigned char ras_log_buf[RTAS_ERROR_LOG_MAX];
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static DEFINE_SPINLOCK(ras_log_buf_lock);
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@ -278,7 +280,7 @@ static void fwnmi_release_errinfo(void)
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printk("FWNMI: nmi-interlock failed: %d\n", ret);
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}
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void pSeries_system_reset_exception(struct pt_regs *regs)
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int pSeries_system_reset_exception(struct pt_regs *regs)
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{
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if (fwnmi_active) {
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struct rtas_error_log *errhdr = fwnmi_get_errinfo(regs);
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@ -287,6 +289,7 @@ void pSeries_system_reset_exception(struct pt_regs *regs)
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}
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fwnmi_release_errinfo();
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}
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return 0; /* need to perform reset */
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}
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/*
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@ -0,0 +1,9 @@
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#ifndef _PSERIES_RAS_H
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#define _PSERIES_RAS_H
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struct pt_regs;
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extern int pSeries_system_reset_exception(struct pt_regs *regs);
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extern int pSeries_machine_check_exception(struct pt_regs *regs);
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#endif /* _PSERIES_RAS_H */
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@ -69,6 +69,7 @@
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#include <asm/smp.h>
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#include "plpar_wrappers.h"
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#include "ras.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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@ -80,9 +81,6 @@ extern void find_udbg_vterm(void);
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int fwnmi_active; /* TRUE if an FWNMI handler is present */
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extern void pSeries_system_reset_exception(struct pt_regs *regs);
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extern int pSeries_machine_check_exception(struct pt_regs *regs);
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static void pseries_shared_idle(void);
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static void pseries_dedicated_idle(void);
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@ -105,6 +105,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
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#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
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#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
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#else
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/* ensure on 32b processors the flags are available for compiling but
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* don't do anything */
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@ -304,7 +305,8 @@ enum {
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CPU_FTR_MMCRA_SIHV,
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CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
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CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
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CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
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#endif
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|
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@ -134,7 +134,7 @@ struct machdep_calls {
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void (*nvram_sync)(void);
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/* Exception handlers */
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void (*system_reset_exception)(struct pt_regs *regs);
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int (*system_reset_exception)(struct pt_regs *regs);
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int (*machine_check_exception)(struct pt_regs *regs);
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/* Motherboard/chipset features. This is a kind of general purpose
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|
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@ -145,6 +145,10 @@
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#define SPRN_CTR 0x009 /* Count Register */
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#define SPRN_CTRLF 0x088
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#define SPRN_CTRLT 0x098
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#define CTRL_CT 0xc0000000 /* current thread */
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#define CTRL_CT0 0x80000000 /* thread 0 */
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#define CTRL_CT1 0x40000000 /* thread 1 */
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#define CTRL_TE 0x00c00000 /* thread enable */
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#define CTRL_RUNLATCH 0x1
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#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
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#define DABR_TRANSLATION (1UL << 2)
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@ -257,11 +261,11 @@
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#define SPRN_HID6 0x3F9 /* BE HID 6 */
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#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
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#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
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#define SPRN_TSCR 0x399 /* Thread switch control on BE */
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#define SPRN_TTR 0x39A /* Thread switch timeout on BE */
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#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */
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#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */
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#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */
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#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
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#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
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#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
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#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
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#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
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#define SPRN_TSC 0x3FD /* Thread switch control on others */
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#define SPRN_TST 0x3FC /* Thread switch timeout on others */
|
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#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
|
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|
|
@ -375,6 +379,14 @@
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#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
|
||||
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
|
||||
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
|
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#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
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||||
#define SRR1_WAKERESET 0x00380000 /* System reset */
|
||||
#define SRR1_WAKESYSERR 0x00300000 /* System error */
|
||||
#define SRR1_WAKEEE 0x00200000 /* External interrupt */
|
||||
#define SRR1_WAKEMT 0x00280000 /* mtctrl */
|
||||
#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
|
||||
#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
|
||||
|
||||
#ifndef SPRN_SVR
|
||||
#define SPRN_SVR 0x11E /* System Version Register */
|
||||
#endif
|
||||
|
|
|
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Loading…
Reference in New Issue