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phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845 

Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.

Fixes: ef17f6e212 ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Manu Gautam 2018-10-16 12:52:07 +05:30 committed by Kishon Vijay Abraham I
parent 6e34d358b2
commit c88520db18
1 changed files with 1 additions and 0 deletions
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drivers/phy/qualcomm/phy-qcom-qusb2.c
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@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg = {
.mask_core_ready = CORE_READY_STATUS, .mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true, .has_pll_override = true,
.autoresume_en = BIT(0), .autoresume_en = BIT(0),
.update_tune1_with_efuse = true,
}; };
static const char * const qusb2_phy_vreg_names[] = { static const char * const qusb2_phy_vreg_names[] = {