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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Ingo Molnar.

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/smp: Fix topology checks on AMD MCM CPUs
  x86/mm: Fix some kernel-doc warnings
  x86, um: Correct syscall table type attributes breaking gcc 4.8
This commit is contained in:
Linus Torvalds 2012-06-15 16:59:19 -07:00
parent ed21a66c18 161270fc1f
commit c83119a980
4 changed files with 10 additions and 7 deletions
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7
arch/x86/kernel/smpboot.c
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@ -349,9 +349,12 @@ static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
{ {
if (c->phys_proc_id == o->phys_proc_id) if (c->phys_proc_id == o->phys_proc_id) {
return topology_sane(c, o, "mc"); if (cpu_has(c, X86_FEATURE_AMD_DCM))
return true;
return topology_sane(c, o, "mc");
}
return false; return false;
} }

4
arch/x86/mm/ioremap.c
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@ -180,7 +180,7 @@ err_free_memtype:
/** /**
* ioremap_nocache - map bus memory into CPU space * ioremap_nocache - map bus memory into CPU space
* @offset: bus address of the memory * @phys_addr: bus address of the memory
* @size: size of the resource to map * @size: size of the resource to map
* *
* ioremap_nocache performs a platform specific sequence of operations to * ioremap_nocache performs a platform specific sequence of operations to
@ -217,7 +217,7 @@ EXPORT_SYMBOL(ioremap_nocache);
/** /**
* ioremap_wc - map memory into CPU space write combined * ioremap_wc - map memory into CPU space write combined
* @offset: bus address of the memory * @phys_addr: bus address of the memory
* @size: size of the resource to map * @size: size of the resource to map
* *
* This version of ioremap ensures that the memory is marked write combining. * This version of ioremap ensures that the memory is marked write combining.

2
arch/x86/mm/pageattr.c
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@ -122,7 +122,7 @@ within(unsigned long addr, unsigned long start, unsigned long end)
/** /**
* clflush_cache_range - flush a cache range with clflush * clflush_cache_range - flush a cache range with clflush
* @addr: virtual start address * @vaddr: virtual start address
* @size: number of bytes to flush * @size: number of bytes to flush
* *
* clflush is an unordered instruction which needs fencing with mfence * clflush is an unordered instruction which needs fencing with mfence

4
arch/x86/um/sys_call_table_32.c
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@ -39,9 +39,9 @@
#undef __SYSCALL_I386 #undef __SYSCALL_I386
#define __SYSCALL_I386(nr, sym, compat) [ nr ] = sym, #define __SYSCALL_I386(nr, sym, compat) [ nr ] = sym,
typedef void (*sys_call_ptr_t)(void); typedef asmlinkage void (*sys_call_ptr_t)(void);
extern void sys_ni_syscall(void); extern asmlinkage void sys_ni_syscall(void);
const sys_call_ptr_t sys_call_table[] __cacheline_aligned = { const sys_call_ptr_t sys_call_table[] __cacheline_aligned = {
/* /*