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Merge tag 'br-v5.18q' of git://linuxtv.org/hverkuil/media_tree into media_stage

Tag branch

* tag 'br-v5.18q' of git://linuxtv.org/hverkuil/media_tree:
  media: cec: seco: Drop pointless include
  media: hantro: sunxi: Fix VP9 steps
  media: imx: csis: Store pads format separately
  doc: media: Document VP9 reference_mode miss-placement
  doc: media: Document MM21 tiled format
  media: imx: imx8mq-mipi-csi2: Remove YUV422 2X8
  media: v4l2-core: Initialize h264 scaling matrix
  media: imx: imx-mipi-csis: Add output format
  media: imx: imx-mipi-csis: Add BGR888
  media: imx: imx-mipi-csis: Add RGB565_1X16
  media: imx: imx-mipi-csis: Set PIXEL_MODE for YUV422
  media: imx: imx7-media-csi: Use dual sampling for YUV 1X16
  media: imx: Rename imx7-mipi-csis.c to imx-mipi-csis.c
  media: imx: De-stage imx7-mipi-csis

Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Mauro Carvalho Chehab 2022-03-07 16:26:54 +01:00
parent 8268d06750 0bff66dcbe
commit c81652a4a8
18 changed files with 183 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/admin-guide/media/imx7.rst
View File

@ -33,7 +33,7 @@ reference manual [#f1]_.
Entities
--------
imx7-mipi-csi2
imx-mipi-csi2
--------------
This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel

2
Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml → Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
$id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver

7
Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
View File

@ -1698,7 +1698,12 @@ See section '7.3.1 Tx mode semantics' of the :ref:`vp9` specification for more d
* - __u8
- ``reference_mode``
- Specifies the type of inter prediction to be used. See
:ref:`Reference Mode<vp9_reference_mode>` for more details.
:ref:`Reference Mode<vp9_reference_mode>` for more details. Note that
this is derived as part of the compressed header parsing process and
for this reason should have been part of
:c:type: `v4l2_ctrl_vp9_compressed_hdr` optional control. It is safe to
set this value to zero if the driver does not require compressed
headers.
* - __u8
- ``reserved[7]``
- Applications and drivers must set this to zero.

15
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst
View File

@ -233,19 +233,12 @@ please make a proposal on the linux-media mailing list.
- ``V4L2_PIX_FMT_MT21C``
- 'MT21'
- Compressed two-planar YVU420 format used by Mediatek MT8173.
The compression is lossless.
It is an opaque intermediate format and the MDP hardware must be
- Compressed two-planar YVU420 format used by Mediatek MT8173, MT8192,
MT8195 and more. The compression is lossless. This format have
similitude with ``V4L2_PIX_FMT_MM21`` in term of alignment and tiling.
It remains an opaque intermediate format and the MDP hardware must be
used to convert ``V4L2_PIX_FMT_MT21C`` to ``V4L2_PIX_FMT_NV12M``,
``V4L2_PIX_FMT_YUV420M`` or ``V4L2_PIX_FMT_YVU420``.
* .. _V4L2-PIX-FMT-MM21:
- ``V4L2_PIX_FMT_MM21``
- 'MM21'
- Non-compressed, tiled two-planar format used by Mediatek MT8183.
This is an opaque intermediate format and the MDP3 hardware can be
used to convert it to other formats.
.. raw:: latex
\normalsize

6
Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
View File

@ -296,6 +296,12 @@ tiles linearly in memory. The line stride and image height must be
aligned to a multiple of 32. The layouts of the luma and chroma planes are
identical.
``V4L2_PIX_FMT_MM21`` store luma pixel in 16x32 tiles, and chroma pixels
in 16x16 tiles. The line stride must be aligned to a multiple of 16 and the
image height must be aligned to a multiple of 32. The number of luma and chroma
tiles are identical, even though the tile size differ. The image is formed of
two non-contiguous planes.
.. _nv12mt:
.. kernel-figure:: nv12mt.svg

4
MAINTAINERS
View File

@ -11889,10 +11889,10 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/admin-guide/media/imx7.rst
F: Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
F: Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml
F: Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml
F: drivers/media/platform/imx/imx-mipi-csis.c
F: drivers/staging/media/imx/imx7-media-csi.c
F: drivers/staging/media/imx/imx7-mipi-csis.c
MEDIA DRIVERS FOR HELENE
M: Abylay Ospan <aospan@netup.ru>

3
drivers/media/cec/platform/seco/seco-cec.c
View File

@ -12,7 +12,6 @@
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/gpio/consumer.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
@ -551,7 +550,7 @@ static int secocec_acpi_probe(struct secocec_data *sdev)
struct gpio_desc *gpio;
int irq = 0;
gpio = devm_gpiod_get(dev, NULL, GPIOF_IN);
gpio = devm_gpiod_get(dev, NULL, GPIOD_IN);
if (IS_ERR(gpio)) {
dev_err(dev, "Cannot request interrupt gpio\n");
return PTR_ERR(gpio);

1
drivers/media/platform/Kconfig
View File

@ -171,6 +171,7 @@ source "drivers/media/platform/xilinx/Kconfig"
source "drivers/media/platform/rcar-vin/Kconfig"
source "drivers/media/platform/atmel/Kconfig"
source "drivers/media/platform/sunxi/Kconfig"
source "drivers/media/platform/imx/Kconfig"
config VIDEO_TI_CAL
tristate "TI CAL (Camera Adaptation Layer) driver"

1
drivers/media/platform/Makefile
View File

@ -20,6 +20,7 @@ obj-y += ti-vpe/
obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
obj-$(CONFIG_VIDEO_CODA) += coda/
obj-$(CONFIG_VIDEO_IMX) += imx/
obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o
obj-$(CONFIG_VIDEO_IMX8_JPEG) += imx-jpeg/

24
drivers/media/platform/imx/Kconfig Normal file
View File

@ -0,0 +1,24 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig VIDEO_IMX
bool "V4L2 capture drivers for NXP i.MX devices"
depends on ARCH_MXC || COMPILE_TEST
depends on VIDEO_DEV && VIDEO_V4L2
help
Say yes here to enable support for capture drivers on i.MX SoCs.
Support for the single SoC features are selectable in the sub-menu
options.
if VIDEO_IMX
config VIDEO_IMX_MIPI_CSIS
tristate "MIPI CSI-2 CSIS receiver found on i.MX7 and i.MX8 models"
select MEDIA_CONTROLLER
select V4L2_FWNODE
select VIDEO_V4L2_SUBDEV_API
default n
help
Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
endif # VIDEO_IMX

1
drivers/media/platform/imx/Makefile Normal file
View File

@ -0,0 +1 @@
obj-$(CONFIG_VIDEO_IMX_MIPI_CSIS) += imx-mipi-csis.o

73
drivers/staging/media/imx/imx7-mipi-csis.c → drivers/media/platform/imx/imx-mipi-csis.c
View File

@ -1,6 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
* Samsung CSIS MIPI CSI-2 receiver driver.
*
* The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
* i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features
* version 3.6.3.
*
* Copyright (C) 2019 Linaro Ltd
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
@ -31,7 +35,7 @@
#include <media/v4l2-mc.h>
#include <media/v4l2-subdev.h>
#define CSIS_DRIVER_NAME "imx7-mipi-csis"
#define CSIS_DRIVER_NAME "imx-mipi-csis"
#define CSIS_PAD_SINK 0
#define CSIS_PAD_SOURCE 1
@ -169,6 +173,7 @@
#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12)
#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12)
#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */
#define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12)
#define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
#define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2)
#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
@ -325,7 +330,7 @@ struct csi_state {
struct mutex lock; /* Protect csis_fmt, format_mbus and state */
const struct csis_pix_format *csis_fmt;
struct v4l2_mbus_framefmt format_mbus;
struct v4l2_mbus_framefmt format_mbus[CSIS_PADS_NUM];
u32 state;
spinlock_t slock; /* Protect events */
@ -344,6 +349,7 @@ struct csi_state {
struct csis_pix_format {
u32 code;
u32 output;
u32 data_type;
u8 width;
};
@ -352,84 +358,116 @@ static const struct csis_pix_format mipi_csis_formats[] = {
/* YUV formats. */
{
.code = MEDIA_BUS_FMT_UYVY8_1X16,
.output = MEDIA_BUS_FMT_UYVY8_1X16,
.data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
.width = 16,
},
/* RGB formats. */
{
.code = MEDIA_BUS_FMT_RGB565_1X16,
.output = MEDIA_BUS_FMT_RGB565_1X16,
.data_type = MIPI_CSI2_DATA_TYPE_RGB565,
.width = 16,
}, {
.code = MEDIA_BUS_FMT_BGR888_1X24,
.output = MEDIA_BUS_FMT_RGB888_1X24,
.data_type = MIPI_CSI2_DATA_TYPE_RGB888,
.width = 24,
},
/* RAW (Bayer and greyscale) formats. */
{
.code = MEDIA_BUS_FMT_SBGGR8_1X8,
.output = MEDIA_BUS_FMT_SBGGR8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SGBRG8_1X8,
.output = MEDIA_BUS_FMT_SGBRG8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SGRBG8_1X8,
.output = MEDIA_BUS_FMT_SGRBG8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SRGGB8_1X8,
.output = MEDIA_BUS_FMT_SRGGB8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_Y8_1X8,
.output = MEDIA_BUS_FMT_Y8_1X8,
.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
.width = 8,
}, {
.code = MEDIA_BUS_FMT_SBGGR10_1X10,
.output = MEDIA_BUS_FMT_SBGGR10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SGBRG10_1X10,
.output = MEDIA_BUS_FMT_SGBRG10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SGRBG10_1X10,
.output = MEDIA_BUS_FMT_SGRBG10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SRGGB10_1X10,
.output = MEDIA_BUS_FMT_SRGGB10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_Y10_1X10,
.output = MEDIA_BUS_FMT_Y10_1X10,
.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
.width = 10,
}, {
.code = MEDIA_BUS_FMT_SBGGR12_1X12,
.output = MEDIA_BUS_FMT_SBGGR12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SGBRG12_1X12,
.output = MEDIA_BUS_FMT_SGBRG12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SGRBG12_1X12,
.output = MEDIA_BUS_FMT_SGRBG12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SRGGB12_1X12,
.output = MEDIA_BUS_FMT_SRGGB12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_Y12_1X12,
.output = MEDIA_BUS_FMT_Y12_1X12,
.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
.width = 12,
}, {
.code = MEDIA_BUS_FMT_SBGGR14_1X14,
.output = MEDIA_BUS_FMT_SBGGR14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SGBRG14_1X14,
.output = MEDIA_BUS_FMT_SGBRG14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SGRBG14_1X14,
.output = MEDIA_BUS_FMT_SGRBG14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}, {
.code = MEDIA_BUS_FMT_SRGGB14_1X14,
.output = MEDIA_BUS_FMT_SRGGB14_1X14,
.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
.width = 14,
}
@ -497,12 +535,30 @@ static void mipi_csis_system_enable(struct csi_state *state, int on)
/* Called with the state.lock mutex held */
static void __mipi_csis_set_format(struct csi_state *state)
{
struct v4l2_mbus_framefmt *mf = &state->format_mbus;
struct v4l2_mbus_framefmt *mf = &state->format_mbus[CSIS_PAD_SINK];
u32 val;
/* Color format */
val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0));
val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
| MIPI_CSIS_ISPCFG_PIXEL_MASK);
/*
* YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
* (referred to in the documentation as single and dual pixel modes
* respectively, although the 8-bit mode transfers half a pixel per
* clock sample and the 16-bit mode one pixel). While both mode work
* when the CSIS is connected to a receiver that supports either option,
* single pixel mode requires clock rates twice as high. As all SoCs
* that integrate the CSIS can operate in 16-bit bit mode, and some do
* not support 8-bit mode (this is the case of the i.MX8MP), use dual
* pixel mode unconditionally.
*
* TODO: Verify which other formats require DUAL (or QUAD) modes.
*/
if (state->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8)
val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
val |= MIPI_CSIS_ISPCFG_FMT(state->csis_fmt->data_type);
mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val);
@ -911,7 +967,7 @@ mipi_csis_get_format(struct csi_state *state,
if (which == V4L2_SUBDEV_FORMAT_TRY)
return v4l2_subdev_get_try_format(&state->sd, sd_state, pad);
return &state->format_mbus;
return &state->format_mbus[pad];
}
static int mipi_csis_init_cfg(struct v4l2_subdev *sd,
@ -1074,6 +1130,9 @@ static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
CSIS_PAD_SOURCE);
*fmt = sdformat->format;
/* The format on the source pad might change due to unpacking. */
fmt->code = csis_fmt->output;
/* Store the CSIS format descriptor for active formats. */
if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
state->csis_fmt = csis_fmt;
@ -1519,4 +1578,4 @@ module_platform_driver(mipi_csis_driver);
MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:imx7-mipi-csi2");
MODULE_ALIAS("platform:imx-mipi-csi2");

10
drivers/media/v4l2-core/v4l2-ctrls-core.c
View File

@ -114,6 +114,7 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
struct v4l2_ctrl_vp8_frame *p_vp8_frame;
struct v4l2_ctrl_vp9_frame *p_vp9_frame;
struct v4l2_ctrl_fwht_params *p_fwht_params;
struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix;
void *p = ptr.p + idx * ctrl->elem_size;
if (ctrl->p_def.p_const)
@ -168,6 +169,15 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx,
p_fwht_params->flags = V4L2_FWHT_FL_PIXENC_YUV |
(2 << V4L2_FWHT_FL_COMPONENTS_NUM_OFFSET);
break;
case V4L2_CTRL_TYPE_H264_SCALING_MATRIX:
p_h264_scaling_matrix = p;
/*
* The default (flat) H.264 scaling matrix when none are
* specified in the bitstream, this is according to formulas
* (7-8) and (7-9) of the specification.
*/
memset(p_h264_scaling_matrix, 16, sizeof(*p_h264_scaling_matrix));
break;
}
}

4
drivers/staging/media/hantro/sunxi_vpu_hw.c
View File

@ -29,10 +29,10 @@ static const struct hantro_fmt sunxi_vpu_dec_fmts[] = {
.frmsize = {
.min_width = 48,
.max_width = 3840,
.step_width = MB_DIM,
.step_width = 32,
.min_height = 48,
.max_height = 2160,
.step_height = MB_DIM,
.step_height = 32,
},
},
};

1
drivers/staging/media/imx/Makefile
View File

@ -15,5 +15,4 @@ obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-media-csi.o
obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-mipi-csi2.o
obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-media-csi.o
obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-mipi-csis.o
obj-$(CONFIG_VIDEO_IMX7_CSI) += imx8mq-mipi-csi2.o

25
drivers/staging/media/imx/TODO
View File

@ -27,3 +27,28 @@
- i.MX7: all of the above, since it uses the imx media core
- i.MX7: use Frame Interval Monitor
- imx7-media-csi: Restrict the supported formats list to the SoC version.
The imx7 CSI bridge can be configured to sample pixel components from the Rx
queue in single (8bpp) or double (16bpp) component modes. Image format
variants with different sample sizes (ie YUYV_2X8 vs YUYV_1X16) determine the
pixel components sampling size per each clock cycle and their packing mode
(see imx7_csi_configure() for details).
As the imx7 CSI bridge can be interfaced with different IP blocks depending on
the SoC model it is integrated on, the Rx queue sampling size should match
the size of the samples transferred by the transmitting IP block.
To avoid mis-configurations of the capture pipeline, the enumeration of the
supported formats should be restricted to match the pixel source transmitting
mode.
Example: i.MX8MM SoC integrates the CSI bridge with the Samsung CSIS CSI-2
receiver which operates in dual pixel sampling mode. The CSI bridge should
only expose the 1X16 formats variant which instructs it to operate in dual
pixel sampling mode. When the CSI bridge is instead integrated on an i.MX7,
which supports both serial and parallel input, it should expose both variants.
This currently only applies to YUYV formats, but other formats might need
to be handled in the same way.

32
drivers/staging/media/imx/imx7-media-csi.c
View File

@ -498,16 +498,40 @@ static void imx7_csi_configure(struct imx7_csi *csi)
cr3 |= BIT_TWO_8BIT_SENSOR;
cr18 |= BIT_MIPI_DATA_FORMAT_RAW14;
break;
/*
* CSI-2 sources are supposed to use the 1X16 formats, but not
* all of them comply. Support both variants.
* The CSI bridge has a 16-bit input bus. Depending on the
* connected source, data may be transmitted with 8 or 10 bits
* per clock sample (in bits [9:2] or [9:0] respectively) or
* with 16 bits per clock sample (in bits [15:0]). The data is
* then packed into a 32-bit FIFO (as shown in figure 13-11 of
* the i.MX8MM reference manual rev. 3).
*
* The data packing in a 32-bit FIFO input word is controlled by
* the CR3 TWO_8BIT_SENSOR field (also known as SENSOR_16BITS in
* the i.MX8MM reference manual). When set to 0, data packing
* groups four 8-bit input samples (bits [9:2]). When set to 1,
* data packing groups two 16-bit input samples (bits [15:0]).
*
* The register field CR18 MIPI_DOUBLE_CMPNT also needs to be
* configured according to the input format for YUV 4:2:2 data.
* The field controls the gasket between the CSI-2 receiver and
* the CSI bridge. On i.MX7 and i.MX8MM, the field must be set
* to 1 when the CSIS outputs 16-bit samples. On i.MX8MQ, the
* gasket ignores the MIPI_DOUBLE_CMPNT bit and YUV 4:2:2 always
* uses 16-bit samples. Setting MIPI_DOUBLE_CMPNT in that case
* has no effect, but doesn't cause any issue.
*/
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YUYV8_1X16:
cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B;
break;
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_YUYV8_1X16:
cr3 |= BIT_TWO_8BIT_SENSOR;
cr18 |= BIT_MIPI_DATA_FORMAT_YUV422_8B |
BIT_MIPI_DOUBLE_CMPNT;
break;
}
}

7
drivers/staging/media/imx/imx8mq-mipi-csi2.c
View File

@ -200,12 +200,13 @@ static const struct csi2_pix_format imx8mq_mipi_csi_formats[] = {
}, {
.code = MEDIA_BUS_FMT_SRGGB14_1X14,
.width = 14,
}, {
},
/* YUV formats */
.code = MEDIA_BUS_FMT_YUYV8_2X8,
{
.code = MEDIA_BUS_FMT_YUYV8_1X16,
.width = 16,
}, {
.code = MEDIA_BUS_FMT_YUYV8_1X16,
.code = MEDIA_BUS_FMT_UYVY8_1X16,
.width = 16,
}
};