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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "MIPS fixes for various loose ends:

   - Fix workarounds for R4000 erratum.
   - Patch up DEC, Siemens-Nixdorf and Loongson hardware support.
   - Wire up renameat2 syscall.
   - Delete unused file - it was causing false warnings from maintenance
     scripts.
   - Revert a patch because it's functionality is now implemented twice
     which causes superfluous /proc/cpuinfo output.
   - Fix a microMIPS regression"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: mm: Fix broken microMIPS kernel regression.
  MIPS: Add new AUDIT_ARCH token for the N32 ABI on MIPS64
  MIPS: Wire up renameat2 syscall.
  MIPS: inst.h: Rename BITFIELD_FIELD to __BITFIELD_FIELD.
  MIPS: Remove file missed when removing rm9k support a while ago.
  MIPS/loongson2_cpufreq: Fix CPU clock rate setting
  MIPS: Loongson: No need to select GENERIC_HARDIRQS_NO__DO_IRQ
  MIPS: csum_partial.S CPU_DADDI_WORKAROUNDS bug fix
  MIPS: __strncpy_from_user_asm CPU_DADDI_WORKAROUNDS bug fix
  MIPS: __delay CPU_DADDI_WORKAROUNDS bug fix
  MIPS: DEC/SNI: O32 wrapper stack switching fixes
  MIPS: DEC: Bus error handler <asm/cpu-type.h> fixes
  MAINTAINERS: TURBOchannel: Update entry
  Revert "MIPS: MT: proc: Add support for printing VPE and TC ids"
This commit is contained in:
Linus Torvalds 2014-05-20 16:47:33 +09:00
parent 6ed8bf82fe 7bb3940940
commit c7d6891a77
26 changed files with 323 additions and 419 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MAINTAINERS
View File

@ -9116,6 +9116,9 @@ F: arch/um/os-Linux/drivers/
TURBOCHANNEL SUBSYSTEM
M: "Maciej W. Rozycki" <macro@linux-mips.org>
M: Ralf Baechle <ralf@linux-mips.org>
L: linux-mips@linux-mips.org
Q: http://patchwork.linux-mips.org/project/linux-mips/list/
S: Maintained
F: drivers/tc/
F: include/linux/tc.h

1
arch/mips/dec/ecc-berr.c
View File

@ -21,6 +21,7 @@
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/irq_regs.h>
#include <asm/processor.h>
#include <asm/ptrace.h>

1
arch/mips/dec/kn02xa-berr.c
View File

@ -19,6 +19,7 @@
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/cpu-type.h>
#include <asm/irq_regs.h>
#include <asm/ptrace.h>
#include <asm/traps.h>

1
arch/mips/dec/prom/Makefile
View File

@ -6,4 +6,3 @@
lib-y += init.o memory.o cmdline.o identify.o console.o
lib-$(CONFIG_32BIT) += locore.o
lib-$(CONFIG_64BIT) += call_o32.o

89
arch/mips/dec/prom/call_o32.S
View File

@ -1,89 +0,0 @@
/*
* O32 interface for the 64 (or N32) ABI.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for both of the above. */
#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC)
.text
/*
* O32 function call dispatcher, for interfacing 32-bit ROM routines.
*
* The standard 64 (N32) calling sequence is supported, with a0
* holding a function pointer, a1-a7 -- its first seven arguments
* and the stack -- remaining ones (up to O32_ARGC, including a1-a7).
* Static registers, gp and fp are preserved, v0 holds a result.
* This code relies on the called o32 function for sp and ra
* restoration and thus both this dispatcher and the current stack
* have to be placed in a KSEGx (or KUSEG) address space. Any
* pointers passed have to point to addresses within one of these
* spaces as well.
*/
NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ
REG_S ra,O32_FRAMESZ-1*SZREG(sp)
REG_S fp,O32_FRAMESZ-2*SZREG(sp)
REG_S gp,O32_FRAMESZ-3*SZREG(sp)
REG_S s7,O32_FRAMESZ-4*SZREG(sp)
REG_S s6,O32_FRAMESZ-5*SZREG(sp)
REG_S s5,O32_FRAMESZ-6*SZREG(sp)
REG_S s4,O32_FRAMESZ-7*SZREG(sp)
REG_S s3,O32_FRAMESZ-8*SZREG(sp)
REG_S s2,O32_FRAMESZ-9*SZREG(sp)
REG_S s1,O32_FRAMESZ-10*SZREG(sp)
REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0
sll a0,a1,zero
sll a1,a2,zero
sll a2,a3,zero
sll a3,a4,zero
sw a5,0x10(sp)
sw a6,0x14(sp)
sw a7,0x18(sp)
PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x1c(sp)
li t2,O32_ARGC-7
1:
lw t3,(t0)
REG_ADDU t0,SZREG
sw t3,(t1)
REG_SUBU t2,1
REG_ADDU t1,4
bnez t2,1b
jalr jp
REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp)
REG_L s2,O32_FRAMESZ-9*SZREG(sp)
REG_L s3,O32_FRAMESZ-8*SZREG(sp)
REG_L s4,O32_FRAMESZ-7*SZREG(sp)
REG_L s5,O32_FRAMESZ-6*SZREG(sp)
REG_L s6,O32_FRAMESZ-5*SZREG(sp)
REG_L s7,O32_FRAMESZ-4*SZREG(sp)
REG_L gp,O32_FRAMESZ-3*SZREG(sp)
REG_L fp,O32_FRAMESZ-2*SZREG(sp)
REG_L ra,O32_FRAMESZ-1*SZREG(sp)
REG_ADDU sp,O32_FRAMESZ
jr ra
END(call_o32)

57
arch/mips/fw/lib/call_o32.S
View File

@ -1,7 +1,7 @@
/*
* O32 interface for the 64 (or N32) ABI.
*
* Copyright (C) 2002 Maciej W. Rozycki
* Copyright (C) 2002, 2014 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -12,28 +12,37 @@
#include <asm/asm.h>
#include <asm/regdef.h>
/* O32 register size. */
#define O32_SZREG 4
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for static register */
#define O32_FRAMESZ (SZREG * O32_STATC)
/* Frame size on new stack */
#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC)
/* Argument area frame size. */
#define O32_ARGSZ (O32_SZREG * O32_ARGC)
/* Static register save area frame size. */
#define O32_STATSZ (SZREG * O32_STATC)
/* Stack pointer register save area frame size. */
#define O32_SPSZ SZREG
/* Combined area frame size. */
#define O32_FRAMESZ (O32_ARGSZ + O32_SPSZ + O32_STATSZ)
/* Switched stack frame size. */
#define O32_NFRAMESZ (O32_ARGSZ + O32_SPSZ)
.text
/*
* O32 function call dispatcher, for interfacing 32-bit ROM routines.
*
* The standard 64 (N32) calling sequence is supported, with a0
* holding a function pointer, a1 a new stack pointer, a2-a7 -- its
* first six arguments and the stack -- remaining ones (up to O32_ARGC,
* including a2-a7). Static registers, gp and fp are preserved, v0 holds
* a result. This code relies on the called o32 function for sp and ra
* restoration and this dispatcher has to be placed in a KSEGx (or KUSEG)
* address space. Any pointers passed have to point to addresses within
* one of these spaces as well.
* The standard 64 (N32) calling sequence is supported, with a0 holding
* a function pointer, a1 a pointer to the new stack to call the
* function with or 0 if no stack switching is requested, a2-a7 -- the
* function call's first six arguments, and the stack -- the remaining
* arguments (up to O32_ARGC, including a2-a7). Static registers, gp
* and fp are preserved, v0 holds the result. This code relies on the
* called o32 function for sp and ra restoration and this dispatcher has
* to be placed in a KSEGx (or KUSEG) address space. Any pointers
* passed have to point to addresses within one of these spaces as well.
*/
NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ
@ -51,32 +60,36 @@ NESTED(call_o32, O32_FRAMESZ, ra)
REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0
REG_SUBU s0,a1,O32_FRAMESZ_NEW
REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0)
move fp,sp
beqz a1,0f
REG_SUBU fp,a1,O32_NFRAMESZ
0:
REG_S sp,O32_NFRAMESZ-1*SZREG(fp)
sll a0,a2,zero
sll a1,a3,zero
sll a2,a4,zero
sll a3,a5,zero
sw a6,0x10(s0)
sw a7,0x14(s0)
sw a6,4*O32_SZREG(fp)
sw a7,5*O32_SZREG(fp)
PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x18(s0)
PTR_LA t1,6*O32_SZREG(fp)
li t2,O32_ARGC-6
1:
lw t3,(t0)
REG_ADDU t0,SZREG
sw t3,(t1)
REG_SUBU t2,1
REG_ADDU t1,4
REG_ADDU t1,O32_SZREG
bnez t2,1b
move sp,s0
move sp,fp
jalr jp
REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp)
REG_L sp,O32_NFRAMESZ-1*SZREG(sp)
REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp)

3
arch/mips/fw/sni/sniprom.c
View File

@ -40,7 +40,8 @@
#ifdef CONFIG_64BIT
static u8 o32_stk[16384];
/* O32 stack has to be 8-byte aligned. */
static u64 o32_stk[4096];
#define O32_STK &o32_stk[sizeof(o32_stk)]
#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \

40
arch/mips/include/asm/dec/prom.h
View File

@ -113,31 +113,31 @@ extern int (*__pmax_close)(int);
#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
__asm__(#fun " = call_o32")
int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
int __DEC_PROM_O32(_rex_bootinit, (int (*)(void), void *));
int __DEC_PROM_O32(_rex_bootread, (int (*)(void), void *));
int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), void *, memmap *));
unsigned long *__DEC_PROM_O32(_rex_slot_address,
(unsigned long *(*)(int), int));
void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
(unsigned long *(*)(int), void *, int));
void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void), void *));
int __DEC_PROM_O32(_rex_getsysid, (int (*)(void), void *));
void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void), void *));
int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
int __DEC_PROM_O32(_prom_getchar, (int (*)(void), void *));
char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), void *, char *));
int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), void *, char *, ...));
#define rex_bootinit() _rex_bootinit(__rex_bootinit)
#define rex_bootread() _rex_bootread(__rex_bootread)
#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x)
#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x)
#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo)
#define rex_getsysid() _rex_getsysid(__rex_getsysid)
#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache)
#define rex_bootinit() _rex_bootinit(__rex_bootinit, NULL)
#define rex_bootread() _rex_bootread(__rex_bootread, NULL)
#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, NULL, x)
#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, NULL, x)
#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo, NULL)
#define rex_getsysid() _rex_getsysid(__rex_getsysid, NULL)
#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache, NULL)
#define prom_getchar() _prom_getchar(__prom_getchar)
#define prom_getenv(x) _prom_getenv(__prom_getenv, x)
#define prom_printf(x...) _prom_printf(__prom_printf, x)
#define prom_getchar() _prom_getchar(__prom_getchar, NULL)
#define prom_getenv(x) _prom_getenv(__prom_getenv, NULL, x)
#define prom_printf(x...) _prom_printf(__prom_printf, NULL, x)
#else /* !CONFIG_64BIT */

56
arch/mips/include/asm/rm9k-ocd.h
View File

@ -1,56 +0,0 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if !defined(_ASM_RM9K_OCD_H)
#define _ASM_RM9K_OCD_H
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/io.h>
extern volatile void __iomem * const ocd_base;
extern volatile void __iomem * const titan_base;
#define ocd_addr(__x__) (ocd_base + (__x__))
#define titan_addr(__x__) (titan_base + (__x__))
#define scram_addr(__x__) (scram_base + (__x__))
/* OCD register access */
#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
#define ocd_writel(__val__, __offs__) \
__raw_writel((__val__), ocd_addr(__offs__))
#define ocd_writew(__val__, __offs__) \
__raw_writew((__val__), ocd_addr(__offs__))
#define ocd_writeb(__val__, __offs__) \
__raw_writeb((__val__), ocd_addr(__offs__))
/* TITAN register access - 32 bit-wide only */
#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
#define titan_writel(__val__, __offs__) \
__raw_writel((__val__), titan_addr(__offs__))
/* Protect access to shared TITAN registers */
extern spinlock_t titan_lock;
extern int titan_irqflags;
#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
#endif /* !defined(_ASM_RM9K_OCD_H) */

2
arch/mips/include/asm/syscall.h
View File

@ -133,6 +133,8 @@ static inline int syscall_get_arch(void)
#ifdef CONFIG_64BIT
if (!test_thread_flag(TIF_32BIT_REGS))
arch |= __AUDIT_ARCH_64BIT;
if (test_thread_flag(TIF_32BIT_ADDR))
arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
#endif
#if defined(__LITTLE_ENDIAN)
arch |= __AUDIT_ARCH_LE;

398
arch/mips/include/uapi/asm/inst.h
View File

@ -484,13 +484,13 @@ enum MIPS6e_i8_func {
* Damn ... bitfields depend from byteorder :-(
*/
#ifdef __MIPSEB__
#define BITFIELD_FIELD(field, more) \
#define __BITFIELD_FIELD(field, more) \
field; \
more
#elif defined(__MIPSEL__)
#define BITFIELD_FIELD(field, more) \
#define __BITFIELD_FIELD(field, more) \
more \
field;
@ -499,112 +499,112 @@ enum MIPS6e_i8_func {
#endif
struct j_format {
BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
BITFIELD_FIELD(unsigned int target : 26,
__BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
__BITFIELD_FIELD(unsigned int target : 26,
;))
};
struct i_format { /* signed immediate format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(signed int simmediate : 16,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(signed int simmediate : 16,
;))))
};
struct u_format { /* unsigned immediate format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int uimmediate : 16,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int uimmediate : 16,
;))))
};
struct c_format { /* Cache (>= R6000) format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int c_op : 3,
BITFIELD_FIELD(unsigned int cache : 2,
BITFIELD_FIELD(unsigned int simmediate : 16,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int c_op : 3,
__BITFIELD_FIELD(unsigned int cache : 2,
__BITFIELD_FIELD(unsigned int simmediate : 16,
;)))))
};
struct r_format { /* Register format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int re : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int re : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct p_format { /* Performance counter format (R10000) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int re : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int re : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct f_format { /* FPU register format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int : 1,
BITFIELD_FIELD(unsigned int fmt : 4,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int re : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int : 1,
__BITFIELD_FIELD(unsigned int fmt : 4,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int re : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;)))))))
};
struct ma_format { /* FPU multiply and add format (MIPS IV) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fr : 5,
BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 4,
BITFIELD_FIELD(unsigned int fmt : 2,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int fr : 5,
__BITFIELD_FIELD(unsigned int ft : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int func : 4,
__BITFIELD_FIELD(unsigned int fmt : 2,
;)))))))
};
struct b_format { /* BREAK and SYSCALL */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int code : 20,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int code : 20,
__BITFIELD_FIELD(unsigned int func : 6,
;)))
};
struct ps_format { /* MIPS-3D / paired single format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int ft : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct v_format { /* MDMX vector format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int sel : 4,
BITFIELD_FIELD(unsigned int fmt : 1,
BITFIELD_FIELD(unsigned int vt : 5,
BITFIELD_FIELD(unsigned int vs : 5,
BITFIELD_FIELD(unsigned int vd : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int sel : 4,
__BITFIELD_FIELD(unsigned int fmt : 1,
__BITFIELD_FIELD(unsigned int vt : 5,
__BITFIELD_FIELD(unsigned int vs : 5,
__BITFIELD_FIELD(unsigned int vd : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;)))))))
};
struct spec3_format { /* SPEC3 */
BITFIELD_FIELD(unsigned int opcode:6,
BITFIELD_FIELD(unsigned int rs:5,
BITFIELD_FIELD(unsigned int rt:5,
BITFIELD_FIELD(signed int simmediate:9,
BITFIELD_FIELD(unsigned int func:7,
__BITFIELD_FIELD(unsigned int opcode:6,
__BITFIELD_FIELD(unsigned int rs:5,
__BITFIELD_FIELD(unsigned int rt:5,
__BITFIELD_FIELD(signed int simmediate:9,
__BITFIELD_FIELD(unsigned int func:7,
;)))))
};
@ -616,141 +616,141 @@ struct spec3_format { /* SPEC3 */
* if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
*/
struct fb_format { /* FPU branch format (MIPS32) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int bc : 5,
BITFIELD_FIELD(unsigned int cc : 3,
BITFIELD_FIELD(unsigned int flag : 2,
BITFIELD_FIELD(signed int simmediate : 16,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int bc : 5,
__BITFIELD_FIELD(unsigned int cc : 3,
__BITFIELD_FIELD(unsigned int flag : 2,
__BITFIELD_FIELD(signed int simmediate : 16,
;)))))
};
struct fp0_format { /* FPU multiply and add format (MIPS32) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fmt : 5,
BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int fmt : 5,
__BITFIELD_FIELD(unsigned int ft : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int fmt : 3,
BITFIELD_FIELD(unsigned int op : 2,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int ft : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int fmt : 3,
__BITFIELD_FIELD(unsigned int op : 2,
__BITFIELD_FIELD(unsigned int func : 6,
;)))))))
};
struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int op : 5,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int op : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fmt : 2,
BITFIELD_FIELD(unsigned int op : 8,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fmt : 2,
__BITFIELD_FIELD(unsigned int op : 8,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int cc : 3,
BITFIELD_FIELD(unsigned int zero : 2,
BITFIELD_FIELD(unsigned int fmt : 2,
BITFIELD_FIELD(unsigned int op : 3,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int cc : 3,
__BITFIELD_FIELD(unsigned int zero : 2,
__BITFIELD_FIELD(unsigned int fmt : 2,
__BITFIELD_FIELD(unsigned int op : 3,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))))
};
struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fmt : 3,
BITFIELD_FIELD(unsigned int op : 7,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fmt : 3,
__BITFIELD_FIELD(unsigned int op : 7,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int cc : 3,
BITFIELD_FIELD(unsigned int fmt : 3,
BITFIELD_FIELD(unsigned int cond : 4,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int cc : 3,
__BITFIELD_FIELD(unsigned int fmt : 3,
__BITFIELD_FIELD(unsigned int cond : 4,
__BITFIELD_FIELD(unsigned int func : 6,
;)))))))
};
struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int index : 5,
BITFIELD_FIELD(unsigned int base : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int op : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int index : 5,
__BITFIELD_FIELD(unsigned int base : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int op : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct fp6_format { /* FPU madd and msub format (MIPS IV) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int fr : 5,
BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int fr : 5,
__BITFIELD_FIELD(unsigned int ft : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int ft : 5,
BITFIELD_FIELD(unsigned int fs : 5,
BITFIELD_FIELD(unsigned int fd : 5,
BITFIELD_FIELD(unsigned int fr : 5,
BITFIELD_FIELD(unsigned int func : 6,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int ft : 5,
__BITFIELD_FIELD(unsigned int fs : 5,
__BITFIELD_FIELD(unsigned int fd : 5,
__BITFIELD_FIELD(unsigned int fr : 5,
__BITFIELD_FIELD(unsigned int func : 6,
;))))))
};
struct mm_i_format { /* Immediate format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(unsigned int rs : 5,
BITFIELD_FIELD(signed int simmediate : 16,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(signed int simmediate : 16,
;))))
};
struct mm_m_format { /* Multi-word load/store format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int base : 5,
BITFIELD_FIELD(unsigned int func : 4,
BITFIELD_FIELD(signed int simmediate : 12,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int base : 5,
__BITFIELD_FIELD(unsigned int func : 4,
__BITFIELD_FIELD(signed int simmediate : 12,
;)))))
};
struct mm_x_format { /* Scaled indexed load format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int index : 5,
BITFIELD_FIELD(unsigned int base : 5,
BITFIELD_FIELD(unsigned int rd : 5,
BITFIELD_FIELD(unsigned int func : 11,
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int index : 5,
__BITFIELD_FIELD(unsigned int base : 5,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int func : 11,
;)))))
};
@ -758,51 +758,51 @@ struct mm_x_format { /* Scaled indexed load format (microMIPS) */
* microMIPS instruction formats (16-bit length)
*/
struct mm_b0_format { /* Unconditional branch format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(signed int simmediate : 10,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(signed int simmediate : 10,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;)))
};
struct mm_b1_format { /* Conditional branch format (microMIPS) */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rs : 3,
BITFIELD_FIELD(signed int simmediate : 7,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 3,
__BITFIELD_FIELD(signed int simmediate : 7,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))))
};
struct mm16_m_format { /* Multi-word load/store format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int func : 4,
BITFIELD_FIELD(unsigned int rlist : 2,
BITFIELD_FIELD(unsigned int imm : 4,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int func : 4,
__BITFIELD_FIELD(unsigned int rlist : 2,
__BITFIELD_FIELD(unsigned int imm : 4,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;)))))
};
struct mm16_rb_format { /* Signed immediate format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 3,
BITFIELD_FIELD(unsigned int base : 3,
BITFIELD_FIELD(signed int simmediate : 4,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 3,
__BITFIELD_FIELD(unsigned int base : 3,
__BITFIELD_FIELD(signed int simmediate : 4,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;)))))
};
struct mm16_r3_format { /* Load from global pointer format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 3,
BITFIELD_FIELD(signed int simmediate : 7,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 3,
__BITFIELD_FIELD(signed int simmediate : 7,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))))
};
struct mm16_r5_format { /* Load/store from stack pointer format */
BITFIELD_FIELD(unsigned int opcode : 6,
BITFIELD_FIELD(unsigned int rt : 5,
BITFIELD_FIELD(signed int simmediate : 5,
BITFIELD_FIELD(unsigned int : 16, /* Ignored */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(signed int simmediate : 5,
__BITFIELD_FIELD(unsigned int : 16, /* Ignored */
;))))
};
@ -810,57 +810,57 @@ struct mm16_r5_format { /* Load/store from stack pointer format */
* MIPS16e instruction formats (16-bit length)
*/
struct m16e_rr {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int rx : 3,
BITFIELD_FIELD(unsigned int nd : 1,
BITFIELD_FIELD(unsigned int l : 1,
BITFIELD_FIELD(unsigned int ra : 1,
BITFIELD_FIELD(unsigned int func : 5,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int rx : 3,
__BITFIELD_FIELD(unsigned int nd : 1,
__BITFIELD_FIELD(unsigned int l : 1,
__BITFIELD_FIELD(unsigned int ra : 1,
__BITFIELD_FIELD(unsigned int func : 5,
;))))))
};
struct m16e_jal {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int x : 1,
BITFIELD_FIELD(unsigned int imm20_16 : 5,
BITFIELD_FIELD(signed int imm25_21 : 5,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int x : 1,
__BITFIELD_FIELD(unsigned int imm20_16 : 5,
__BITFIELD_FIELD(signed int imm25_21 : 5,
;))))
};
struct m16e_i64 {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int func : 3,
BITFIELD_FIELD(unsigned int imm : 8,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int func : 3,
__BITFIELD_FIELD(unsigned int imm : 8,
;)))
};
struct m16e_ri64 {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int func : 3,
BITFIELD_FIELD(unsigned int ry : 3,
BITFIELD_FIELD(unsigned int imm : 5,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int func : 3,
__BITFIELD_FIELD(unsigned int ry : 3,
__BITFIELD_FIELD(unsigned int imm : 5,
;))))
};
struct m16e_ri {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int rx : 3,
BITFIELD_FIELD(unsigned int imm : 8,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int rx : 3,
__BITFIELD_FIELD(unsigned int imm : 8,
;)))
};
struct m16e_rri {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int rx : 3,
BITFIELD_FIELD(unsigned int ry : 3,
BITFIELD_FIELD(unsigned int imm : 5,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int rx : 3,
__BITFIELD_FIELD(unsigned int ry : 3,
__BITFIELD_FIELD(unsigned int imm : 5,
;))))
};
struct m16e_i8 {
BITFIELD_FIELD(unsigned int opcode : 5,
BITFIELD_FIELD(unsigned int func : 3,
BITFIELD_FIELD(unsigned int imm : 8,
__BITFIELD_FIELD(unsigned int opcode : 5,
__BITFIELD_FIELD(unsigned int func : 3,
__BITFIELD_FIELD(unsigned int imm : 8,
;)))
};

9
arch/mips/include/uapi/asm/unistd.h
View File

@ -371,11 +371,12 @@
#define __NR_finit_module (__NR_Linux + 348)
#define __NR_sched_setattr (__NR_Linux + 349)
#define __NR_sched_getattr (__NR_Linux + 350)
#define __NR_renameat2 (__NR_Linux + 351)
/*
* Offset of the last Linux o32 flavoured syscall
*/
#define __NR_Linux_syscalls 350
#define __NR_Linux_syscalls 351
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@ -699,11 +700,12 @@
#define __NR_getdents64 (__NR_Linux + 308)
#define __NR_sched_setattr (__NR_Linux + 309)
#define __NR_sched_getattr (__NR_Linux + 310)
#define __NR_renameat2 (__NR_Linux + 311)
/*
* Offset of the last Linux 64-bit flavoured syscall
*/
#define __NR_Linux_syscalls 310
#define __NR_Linux_syscalls 311
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
@ -1031,11 +1033,12 @@
#define __NR_finit_module (__NR_Linux + 312)
#define __NR_sched_setattr (__NR_Linux + 313)
#define __NR_sched_getattr (__NR_Linux + 314)
#define __NR_renameat2 (__NR_Linux + 315)
/*
* Offset of the last N32 flavoured syscall
*/
#define __NR_Linux_syscalls 314
#define __NR_Linux_syscalls 315
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */

9
arch/mips/kernel/proc.c
View File

@ -124,14 +124,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
if (cpu_has_mipsmt) {
seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
#if defined(CONFIG_MIPS_MT_SMTC)
seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
#endif
}
#endif
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count);

1
arch/mips/kernel/scall32-o32.S
View File

@ -577,3 +577,4 @@ EXPORT(sys_call_table)
PTR sys_finit_module
PTR sys_sched_setattr
PTR sys_sched_getattr /* 4350 */
PTR sys_renameat2

1
arch/mips/kernel/scall64-64.S
View File

@ -430,4 +430,5 @@ EXPORT(sys_call_table)
PTR sys_getdents64
PTR sys_sched_setattr
PTR sys_sched_getattr /* 5310 */
PTR sys_renameat2
.size sys_call_table,.-sys_call_table

1
arch/mips/kernel/scall64-n32.S
View File

@ -423,4 +423,5 @@ EXPORT(sysn32_call_table)
PTR sys_finit_module
PTR sys_sched_setattr
PTR sys_sched_getattr
PTR sys_renameat2 /* 6315 */
.size sysn32_call_table,.-sysn32_call_table

1
arch/mips/kernel/scall64-o32.S
View File

@ -556,4 +556,5 @@ EXPORT(sys32_call_table)
PTR sys_finit_module
PTR sys_sched_setattr
PTR sys_sched_getattr /* 4350 */
PTR sys_renameat2
.size sys32_call_table,.-sys32_call_table

9
arch/mips/lib/csum_partial.S
View File

@ -56,14 +56,20 @@
#define UNIT(unit) ((unit)*NBYTES)
#define ADDC(sum,reg) \
.set push; \
.set noat; \
ADD sum, reg; \
sltu v1, sum, reg; \
ADD sum, v1; \
.set pop
#define ADDC32(sum,reg) \
.set push; \
.set noat; \
addu sum, reg; \
sltu v1, sum, reg; \
addu sum, v1; \
.set pop
#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
LOAD _t0, (offset + UNIT(0))(src); \
@ -710,6 +716,8 @@ LEAF(csum_partial)
ADDC(sum, t2)
.Ldone\@:
/* fold checksum */
.set push
.set noat
#ifdef USE_DOUBLE
dsll32 v1, sum, 0
daddu sum, v1
@ -732,6 +740,7 @@ LEAF(csum_partial)
or sum, sum, t0
1:
#endif
.set pop
.set reorder
ADDC32(sum, psum)
jr ra

14
arch/mips/lib/delay.c
View File

@ -6,7 +6,7 @@
* Copyright (C) 1994 by Waldorf Electronics
* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2007 Maciej W. Rozycki
* Copyright (C) 2007, 2014 Maciej W. Rozycki
*/
#include <linux/module.h>
#include <linux/param.h>
@ -15,6 +15,12 @@
#include <asm/compiler.h>
#include <asm/war.h>
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
#define GCC_DADDI_IMM_ASM() "I"
#else
#define GCC_DADDI_IMM_ASM() "r"
#endif
void __delay(unsigned long loops)
{
__asm__ __volatile__ (
@ -22,13 +28,13 @@ void __delay(unsigned long loops)
" .align 3 \n"
"1: bnez %0, 1b \n"
#if BITS_PER_LONG == 32
" subu %0, 1 \n"
" subu %0, %1 \n"
#else
" dsubu %0, 1 \n"
" dsubu %0, %1 \n"
#endif
" .set reorder \n"
: "=r" (loops)
: "0" (loops));
: GCC_DADDI_IMM_ASM() (1), "0" (loops));
}
EXPORT_SYMBOL(__delay);

13
arch/mips/lib/strncpy_user.S
View File

@ -35,7 +35,6 @@ LEAF(__strncpy_from_\func\()_asm)
bnez v0, .Lfault\@
FEXPORT(__strncpy_from_\func\()_nocheck_asm)
.set noreorder
move t0, zero
move v1, a1
.ifeqs "\func","kernel"
@ -45,21 +44,21 @@ FEXPORT(__strncpy_from_\func\()_nocheck_asm)
.endif
PTR_ADDIU v1, 1
R10KCBARRIER(0(ra))
sb v0, (a0)
beqz v0, 2f
sb v0, (a0)
PTR_ADDIU t0, 1
PTR_ADDIU a0, 1
bne t0, a2, 1b
PTR_ADDIU a0, 1
2: PTR_ADDU v0, a1, t0
xor v0, a1
bltz v0, .Lfault\@
nop
move v0, t0
jr ra # return n
move v0, t0
END(__strncpy_from_\func\()_asm)
.Lfault\@: jr ra
li v0, -EFAULT
.Lfault\@:
li v0, -EFAULT
jr ra
.section __ex_table,"a"
PTR 1b, .Lfault\@

1
arch/mips/loongson/Kconfig
View File

@ -64,7 +64,6 @@ config LEMOTE_MACH3A
bool "Lemote Loongson 3A family machines"
select ARCH_SPARSEMEM_ENABLE
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select GENERIC_HARDIRQS_NO__DO_IRQ
select BOOT_ELF32
select BOARD_SCACHE
select CSRC_R4K

5
arch/mips/loongson/lemote-2f/clock.c
View File

@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int rate_khz = rate / 1000;
int ret = 0;
int regval;
int i;
@ -111,10 +112,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
if (loongson2_clockmod_table[i].frequency ==
CPUFREQ_ENTRY_INVALID)
continue;
if (rate == loongson2_clockmod_table[i].frequency)
if (rate_khz == loongson2_clockmod_table[i].frequency)
break;
}
if (rate != loongson2_clockmod_table[i].frequency)
if (rate_khz != loongson2_clockmod_table[i].frequency)
return -ENOTSUPP;
clk->rate = rate;

4
arch/mips/mm/tlb-funcs.S
View File

@ -16,8 +16,10 @@
#define FASTPATH_SIZE 128
EXPORT(tlbmiss_handler_setup_pgd_start)
LEAF(tlbmiss_handler_setup_pgd)
.space 16 * 4
1: j 1b /* Dummy, will be replaced. */
.space 64
END(tlbmiss_handler_setup_pgd)
EXPORT(tlbmiss_handler_setup_pgd_end)

7
arch/mips/mm/tlbex.c
View File

@ -1422,16 +1422,17 @@ static void build_r4000_tlb_refill_handler(void)
extern u32 handle_tlbl[], handle_tlbl_end[];
extern u32 handle_tlbs[], handle_tlbs_end[];
extern u32 handle_tlbm[], handle_tlbm_end[];
extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[];
extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
extern u32 tlbmiss_handler_setup_pgd_end[];
static void build_setup_pgd(void)
{
const int a0 = 4;
const int __maybe_unused a1 = 5;
const int __maybe_unused a2 = 6;
u32 *p = tlbmiss_handler_setup_pgd;
u32 *p = tlbmiss_handler_setup_pgd_start;
const int tlbmiss_handler_setup_pgd_size =
tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd;
tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
long pgdc = (long)pgd_current;
#endif

4
drivers/cpufreq/loongson2_cpufreq.c
View File

@ -62,7 +62,7 @@ static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
set_cpus_allowed_ptr(current, &cpus_allowed);
/* setting the cpu frequency */
clk_set_rate(policy->clk, freq);
clk_set_rate(policy->clk, freq * 1000);
return 0;
}
@ -92,7 +92,7 @@ static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
i++)
loongson2_clockmod_table[i].frequency = (rate * i) / 8;
ret = clk_set_rate(cpuclk, rate);
ret = clk_set_rate(cpuclk, rate * 1000);
if (ret) {
clk_put(cpuclk);
return ret;

12
include/uapi/linux/audit.h
View File

@ -331,9 +331,17 @@ enum {
#define AUDIT_FAIL_PRINTK 1
#define AUDIT_FAIL_PANIC 2
/*
* These bits disambiguate different calling conventions that share an
* ELF machine type, bitness, and endianness
*/
#define __AUDIT_ARCH_CONVENTION_MASK 0x30000000
#define __AUDIT_ARCH_CONVENTION_MIPS64_N32 0x20000000
/* distinguish syscall tables */
#define __AUDIT_ARCH_64BIT 0x80000000
#define __AUDIT_ARCH_LE 0x40000000
#define AUDIT_ARCH_ALPHA (EM_ALPHA|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_ARM (EM_ARM|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_ARMEB (EM_ARM)
@ -346,7 +354,11 @@ enum {
#define AUDIT_ARCH_MIPS (EM_MIPS)
#define AUDIT_ARCH_MIPSEL (EM_MIPS|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_MIPS64 (EM_MIPS|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_MIPS64N32 (EM_MIPS|__AUDIT_ARCH_64BIT|\
__AUDIT_ARCH_CONVENTION_MIPS64_N32)
#define AUDIT_ARCH_MIPSEL64 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_MIPSEL64N32 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE\
__AUDIT_ARCH_CONVENTION_MIPS64_N32)
#define AUDIT_ARCH_OPENRISC (EM_OPENRISC)
#define AUDIT_ARCH_PARISC (EM_PARISC)
#define AUDIT_ARCH_PARISC64 (EM_PARISC|__AUDIT_ARCH_64BIT)