MIPS: Loongson 3: Add HT-linked PCI support
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -15,6 +15,7 @@
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kconfig.h>
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#include <boot_param.h>
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/* loongson internal northbridge initialization */
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extern void bonito_irq_init(void);
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@ -101,7 +102,13 @@ static inline void do_perfcnt_IRQ(void)
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#define LOONGSON_PCICFG_BASE 0x1fe80000
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#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
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#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
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#if defined(CONFIG_HT_PCI)
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#define LOONGSON_PCIIO_BASE loongson_sysconf.pci_io_base
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#else
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#define LOONGSON_PCIIO_BASE 0x1fd00000
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#endif
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#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
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#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
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@ -40,8 +40,13 @@ extern struct pci_ops loongson_pci_ops;
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#else /* loongson2f/32bit & loongson2e */
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/* this pci memory space is mapped by pcimap in pci.c */
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#ifdef CONFIG_CPU_LOONGSON3
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#define LOONGSON_PCI_MEM_START 0x40000000UL
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#define LOONGSON_PCI_MEM_END 0x7effffffUL
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#else
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#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
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#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
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#endif
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/* this is an offset from mips_io_port_base */
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#define LOONGSON_PCI_IO_START 0x00004000UL
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@ -29,6 +29,7 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
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obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
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obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
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obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
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obj-$(CONFIG_LEMOTE_MACH3A) += fixup-loongson3.o ops-loongson3.o
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obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
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obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
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obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
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@ -0,0 +1,66 @@
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/*
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* fixup-loongson3.c
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*
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* Copyright (C) 2012 Lemote, Inc.
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* Author: Xiang Yu, xiangy@lemote.com
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* Chen Huacai, chenhc@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/pci.h>
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#include <boot_param.h>
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static void print_fixup_info(const struct pci_dev *pdev)
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{
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dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
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pdev->vendor, pdev->device, pdev->irq);
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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print_fixup_info(dev);
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return dev->irq;
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}
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static void pci_fixup_radeon(struct pci_dev *pdev)
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{
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if (pdev->resource[PCI_ROM_RESOURCE].start)
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return;
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if (!loongson_sysconf.vgabios_addr)
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return;
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pdev->resource[PCI_ROM_RESOURCE].start =
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loongson_sysconf.vgabios_addr;
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pdev->resource[PCI_ROM_RESOURCE].end =
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loongson_sysconf.vgabios_addr + 256*1024 - 1;
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pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_COPY;
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dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
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PCI_ROM_RESOURCE, &pdev->resource[PCI_ROM_RESOURCE]);
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}
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
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PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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@ -0,0 +1,101 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/mips-boards/bonito64.h>
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#include <loongson.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#define HT1LO_PCICFG_BASE 0x1a000000
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#define HT1LO_PCICFG_BASE_TP1 0x1b000000
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static int loongson3_pci_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn,
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int where, u32 *data)
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{
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unsigned char busnum = bus->number;
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u_int64_t addr, type;
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void *addrp;
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int device = PCI_SLOT(devfn);
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int function = PCI_FUNC(devfn);
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int reg = where & ~3;
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addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
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if (busnum == 0) {
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if (device > 31)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE) | (addr & 0xffff));
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type = 0;
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} else {
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addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE_TP1) | (addr));
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type = 0x10000;
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}
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if (access_type == PCI_ACCESS_WRITE)
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writel(*data, addrp);
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else {
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*data = readl(addrp);
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if (*data == 0xffffffff) {
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*data = -1;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data = 0;
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int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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int ret;
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if (size == 4)
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data = val;
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else {
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ret = loongson3_pci_config_access(PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
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bus, devfn, where, &data);
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return ret;
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}
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struct pci_ops loongson_pci_ops = {
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.read = loongson3_pci_pcibios_read,
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.write = loongson3_pci_pcibios_write
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};
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