hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties 

The cpu_lp clock property is only needed when the CPUfreq driver
supports CPU cluster switching. But it was not a design for this driver
and it didn't handle that as well. So removing this property.

Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Joseph Lo 2019-01-04 11:06:46 +08:00 committed by Thierry Reding
parent 73688f7d53
commit c79a3ccb19
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt
View File

@ -9,7 +9,6 @@ Required properties:
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- cpu_g: Clock mux for the fast CPU cluster.
- cpu_lp: Clock mux for the low-power CPU cluster.
- pll_x: Fast PLL clocksource.
- pll_p: Auxiliary PLL used during fast PLL rate changes.
- dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
@ -30,11 +29,10 @@ cpus {
reg = <0>;
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
<&tegra_car TEGRA124_CLK_CCLK_LP>,
<&tegra_car TEGRA124_CLK_PLL_X>,
<&tegra_car TEGRA124_CLK_PLL_P>,
<&dfll>;
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
clock-latency = <300000>;
};