hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[ARM] nommu: fixups for the exception vectors 

The high page vector (0xFFFF0000) does not supported in nommu mode.
This patch allows the vectors to be 0x00000000 or the begining of DRAM
in nommu mode.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Hyok S. Choi 2006-03-27 15:18:50 +01:00 committed by Russell King
parent f8c07de6be
commit c760fc1997
4 changed files with 31 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/Kconfig
View File

@ -72,6 +72,14 @@ config FIQ
config ARCH_MTD_XIP
bool
config VECTORS_BASE
hex
default 0xffff0000 if MMU
default DRAM_BASE if REMAP_VECTORS_TO_RAM
default 0x00000000
help
The base address of exception vectors.
source "init/Kconfig"
menu "System Type"

17
arch/arm/Kconfig-nommu
View File

@ -25,3 +25,20 @@ config FLASH_SIZE
hex 'FLASH Size' if SET_MEM_PARAM
default 0x00400000
config REMAP_VECTORS_TO_RAM
bool 'Install vectors to the begining of RAM' if DRAM_BASE
depends on DRAM_BASE
help
The kernel needs to change the hardware exception vectors.
In nommu mode, the hardware exception vectors are normally
placed at address 0x00000000. However, this region may be
occupied by read-only memory depending on H/W design.
If the region contains read-write memory, say 'n' here.
If your CPU provides a remap facility which allows the exception
vectors to be mapped to writable memory, say 'n' here.
Otherwise, say 'y' here. In this case, the kernel will require
external support to redirect the hardware exception vectors to
the writable versions located at DRAM_BASE.

2
arch/arm/kernel/signal.h
View File

@ -7,6 +7,6 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define KERN_SIGRETURN_CODE 0xffff0500
#define KERN_SIGRETURN_CODE (CONFIG_VECTORS_BASE + 0x00000500)
extern const unsigned long sigreturn_codes[7];

9
arch/arm/kernel/traps.c
View File

@ -688,6 +688,7 @@ EXPORT_SYMBOL(abort);
void __init trap_init(void)
{
unsigned long vectors = CONFIG_VECTORS_BASE;
extern char __stubs_start[], __stubs_end[];
extern char __vectors_start[], __vectors_end[];
extern char __kuser_helper_start[], __kuser_helper_end[];
@ -698,9 +699,9 @@ void __init trap_init(void)
* into the vector page, mapped at 0xffff0000, and ensure these
* are visible to the instruction stream.
*/
memcpy((void *)0xffff0000, __vectors_start, __vectors_end - __vectors_start);
memcpy((void *)0xffff0200, __stubs_start, __stubs_end - __stubs_start);
memcpy((void *)0xffff1000 - kuser_sz, __kuser_helper_start, kuser_sz);
memcpy((void *)vectors, __vectors_start, __vectors_end - __vectors_start);
memcpy((void *)vectors + 0x200, __stubs_start, __stubs_end - __stubs_start);
memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
/*
* Copy signal return handlers into the vector page, and
@ -709,6 +710,6 @@ void __init trap_init(void)
memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
sizeof(sigreturn_codes));
flush_icache_range(0xffff0000, 0xffff0000 + PAGE_SIZE);
flush_icache_range(vectors, vectors + PAGE_SIZE);
modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
}