i2c: add i2c bus driver for NVIDIA GPU
Latest NVIDIA GPU card has USB Type-C interface. There is a Type-C controller which can be accessed over I2C. This driver adds I2C bus driver to communicate with Type-C controller. I2C client driver will be part of USB Type-C UCSI driver. Signed-off-by: Ajay Gupta <ajayg@nvidia.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> [wsa: kept Makefile sorting] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Ajay Gupta
Wolfram Sang
parent
848bd3f3de
commit
c71bcdcb42
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@ -0,0 +1,18 @@
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Kernel driver i2c-nvidia-gpu
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Datasheet: not publicly available.
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Authors:
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Ajay Gupta <ajayg@nvidia.com>
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Description
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-----------
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i2c-nvidia-gpu is a driver for I2C controller included in NVIDIA Turing
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and later GPUs and it is used to communicate with Type-C controller on GPUs.
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If your 'lspci -v' listing shows something like the following,
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01:00.3 Serial bus controller [0c80]: NVIDIA Corporation Device 1ad9 (rev a1)
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then this driver should support the I2C controller of your GPU.
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@ -6861,6 +6861,13 @@ L: linux-acpi@vger.kernel.org
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S: Maintained
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F: drivers/i2c/i2c-core-acpi.c
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I2C CONTROLLER DRIVER FOR NVIDIA GPU
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M: Ajay Gupta <ajayg@nvidia.com>
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L: linux-i2c@vger.kernel.org
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S: Maintained
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F: Documentation/i2c/busses/i2c-nvidia-gpu
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F: drivers/i2c/busses/i2c-nvidia-gpu.c
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I2C MUXES
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M: Peter Rosin <peda@axentia.se>
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L: linux-i2c@vger.kernel.org
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@ -224,6 +224,15 @@ config I2C_NFORCE2_S4985
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This driver can also be built as a module. If so, the module
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will be called i2c-nforce2-s4985.
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config I2C_NVIDIA_GPU
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tristate "NVIDIA GPU I2C controller"
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depends on PCI
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help
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If you say yes to this option, support will be included for the
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NVIDIA GPU I2C controller which is used to communicate with the GPU's
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Type-C controller. This driver can also be built as a module called
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i2c-nvidia-gpu.
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config I2C_SIS5595
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tristate "SiS 5595"
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depends on PCI
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@ -19,6 +19,7 @@ obj-$(CONFIG_I2C_ISCH) += i2c-isch.o
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obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o
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obj-$(CONFIG_I2C_NFORCE2) += i2c-nforce2.o
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obj-$(CONFIG_I2C_NFORCE2_S4985) += i2c-nforce2-s4985.o
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obj-$(CONFIG_I2C_NVIDIA_GPU) += i2c-nvidia-gpu.o
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obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
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obj-$(CONFIG_I2C_SIS5595) += i2c-sis5595.o
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obj-$(CONFIG_I2C_SIS630) += i2c-sis630.o
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@ -0,0 +1,368 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Nvidia GPU I2C controller Driver
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*
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* Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
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* Author: Ajay Gupta <ajayg@nvidia.com>
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <asm/unaligned.h>
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/* I2C definitions */
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#define I2C_MST_CNTL 0x00
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#define I2C_MST_CNTL_GEN_START BIT(0)
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#define I2C_MST_CNTL_GEN_STOP BIT(1)
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#define I2C_MST_CNTL_CMD_READ (1 << 2)
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#define I2C_MST_CNTL_CMD_WRITE (2 << 2)
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#define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
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#define I2C_MST_CNTL_GEN_NACK BIT(28)
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#define I2C_MST_CNTL_STATUS GENMASK(30, 29)
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#define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
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#define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
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#define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
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#define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
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#define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
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#define I2C_MST_ADDR 0x04
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#define I2C_MST_I2C0_TIMING 0x08
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#define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
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#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
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#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
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#define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
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#define I2C_MST_DATA 0x0c
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#define I2C_MST_HYBRID_PADCTL 0x20
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#define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
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#define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
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#define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
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struct gpu_i2c_dev {
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struct device *dev;
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void __iomem *regs;
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struct i2c_adapter adapter;
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struct i2c_board_info *gpu_ccgx_ucsi;
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};
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static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
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{
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u32 val;
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/* enable I2C */
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val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
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val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
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I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
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I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
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writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
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/* enable 100KHZ mode */
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val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
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val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
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<< I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
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val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
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writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
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}
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static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
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{
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unsigned long target = jiffies + msecs_to_jiffies(1000);
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u32 val;
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do {
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val = readl(i2cd->regs + I2C_MST_CNTL);
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if (!(val & I2C_MST_CNTL_CYCLE_TRIGGER))
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break;
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if ((val & I2C_MST_CNTL_STATUS) !=
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I2C_MST_CNTL_STATUS_BUS_BUSY)
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break;
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usleep_range(500, 600);
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} while (time_is_after_jiffies(target));
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if (time_is_before_jiffies(target)) {
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dev_err(i2cd->dev, "i2c timeout error %x\n", val);
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return -ETIME;
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}
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val = readl(i2cd->regs + I2C_MST_CNTL);
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switch (val & I2C_MST_CNTL_STATUS) {
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case I2C_MST_CNTL_STATUS_OKAY:
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return 0;
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case I2C_MST_CNTL_STATUS_NO_ACK:
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return -EIO;
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case I2C_MST_CNTL_STATUS_TIMEOUT:
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return -ETIME;
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default:
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return 0;
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}
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}
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static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
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{
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int status;
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u32 val;
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val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
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(len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
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I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
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writel(val, i2cd->regs + I2C_MST_CNTL);
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status = gpu_i2c_check_status(i2cd);
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if (status < 0)
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return status;
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val = readl(i2cd->regs + I2C_MST_DATA);
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switch (len) {
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case 1:
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data[0] = val;
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break;
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case 2:
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put_unaligned_be16(val, data);
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break;
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case 3:
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put_unaligned_be16(val >> 8, data);
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data[2] = val;
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break;
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case 4:
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put_unaligned_be32(val, data);
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break;
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default:
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break;
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}
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return status;
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}
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static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
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{
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writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
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return gpu_i2c_check_status(i2cd);
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}
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static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
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{
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writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
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return gpu_i2c_check_status(i2cd);
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}
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static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
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{
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u32 val;
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writel(data, i2cd->regs + I2C_MST_DATA);
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val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
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writel(val, i2cd->regs + I2C_MST_CNTL);
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return gpu_i2c_check_status(i2cd);
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}
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static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
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int status, status2;
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int i, j;
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/*
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* The controller supports maximum 4 byte read due to known
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* limitation of sending STOP after every read.
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*/
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for (i = 0; i < num; i++) {
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if (msgs[i].flags & I2C_M_RD) {
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/* program client address before starting read */
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writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
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/* gpu_i2c_read has implicit start */
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status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
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if (status < 0)
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goto stop;
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} else {
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u8 addr = i2c_8bit_addr_from_msg(msgs + i);
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status = gpu_i2c_start(i2cd);
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if (status < 0) {
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if (i == 0)
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return status;
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goto stop;
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}
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status = gpu_i2c_write(i2cd, addr);
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if (status < 0)
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goto stop;
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for (j = 0; j < msgs[i].len; j++) {
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status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
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if (status < 0)
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goto stop;
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}
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}
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}
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status = gpu_i2c_stop(i2cd);
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if (status < 0)
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return status;
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return i;
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stop:
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status2 = gpu_i2c_stop(i2cd);
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if (status2 < 0)
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dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
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return status;
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}
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static const struct i2c_adapter_quirks gpu_i2c_quirks = {
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.max_read_len = 4,
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.flags = I2C_AQ_COMB_WRITE_THEN_READ,
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};
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static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm gpu_i2c_algorithm = {
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.master_xfer = gpu_i2c_master_xfer,
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.functionality = gpu_i2c_functionality,
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};
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/*
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* This driver is for Nvidia GPU cards with USB Type-C interface.
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* We want to identify the cards using vendor ID and class code only
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* to avoid dependency of adding product id for any new card which
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* requires this driver.
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* Currently there is no class code defined for UCSI device over PCI
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* so using UNKNOWN class for now and it will be updated when UCSI
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* over PCI gets a class code.
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* There is no other NVIDIA cards with UNKNOWN class code. Even if the
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* driver gets loaded for an undesired card then eventually i2c_read()
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* (initiated from UCSI i2c_client) will timeout or UCSI commands will
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* timeout.
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*/
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#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
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static const struct pci_device_id gpu_i2c_ids[] = {
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
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{ }
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};
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MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
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static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
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{
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struct i2c_client *ccgx_client;
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i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
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sizeof(*i2cd->gpu_ccgx_ucsi),
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GFP_KERNEL);
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if (!i2cd->gpu_ccgx_ucsi)
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return -ENOMEM;
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strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
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sizeof(i2cd->gpu_ccgx_ucsi->type));
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i2cd->gpu_ccgx_ucsi->addr = 0x8;
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i2cd->gpu_ccgx_ucsi->irq = irq;
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ccgx_client = i2c_new_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
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if (!ccgx_client)
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return -ENODEV;
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return 0;
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}
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static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct gpu_i2c_dev *i2cd;
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int status;
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i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
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if (!i2cd)
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return -ENOMEM;
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i2cd->dev = &pdev->dev;
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dev_set_drvdata(&pdev->dev, i2cd);
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status = pcim_enable_device(pdev);
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if (status < 0) {
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dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
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return status;
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}
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pci_set_master(pdev);
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i2cd->regs = pcim_iomap(pdev, 0, 0);
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if (!i2cd->regs) {
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dev_err(&pdev->dev, "pcim_iomap failed\n");
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return -ENOMEM;
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}
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status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
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if (status < 0) {
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dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
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return status;
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}
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gpu_enable_i2c_bus(i2cd);
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i2c_set_adapdata(&i2cd->adapter, i2cd);
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i2cd->adapter.owner = THIS_MODULE;
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strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
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sizeof(i2cd->adapter.name));
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i2cd->adapter.algo = &gpu_i2c_algorithm;
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i2cd->adapter.quirks = &gpu_i2c_quirks;
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i2cd->adapter.dev.parent = &pdev->dev;
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status = i2c_add_adapter(&i2cd->adapter);
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if (status < 0)
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goto free_irq_vectors;
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status = gpu_populate_client(i2cd, pdev->irq);
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if (status < 0) {
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dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
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goto del_adapter;
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}
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return 0;
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del_adapter:
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i2c_del_adapter(&i2cd->adapter);
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free_irq_vectors:
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pci_free_irq_vectors(pdev);
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return status;
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}
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static void gpu_i2c_remove(struct pci_dev *pdev)
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{
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struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
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i2c_del_adapter(&i2cd->adapter);
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pci_free_irq_vectors(pdev);
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}
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static int gpu_i2c_resume(struct device *dev)
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{
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struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
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gpu_enable_i2c_bus(i2cd);
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return 0;
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}
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UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, NULL, gpu_i2c_resume, NULL);
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|
||||
static struct pci_driver gpu_i2c_driver = {
|
||||
.name = "nvidia-gpu",
|
||||
.id_table = gpu_i2c_ids,
|
||||
.probe = gpu_i2c_probe,
|
||||
.remove = gpu_i2c_remove,
|
||||
.driver = {
|
||||
.pm = &gpu_i2c_driver_pm,
|
||||
},
|
||||
};
|
||||
|
||||
module_pci_driver(gpu_i2c_driver);
|
||||
|
||||
MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
|
||||
MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue