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This is the bulk of pin control changes for v4.19: 

Core changes:
 
 - Augment pinctrl_generic_add_group() and pinmux_generic_add_function()
   to return the selector for the added group/function to the caller
   and augment (hopefully) all drivers to handle this.
 
 New subdrivers:
 
 - Qualcomm PM8998 and PM8005 are supported in the SPMI pin
   control and GPIO driver.
 
 - Intel Ice Lake PCH (platform controller hub) support.
 
 - NXP (ex Freescale) i.MX8MQ support.
 
 - Berlin AS370 support.
 
 Improvements to drivers:
 
 - Support interrupts on the Ocelot pin controller.
 
 - Add SPI pins to the Uniphier driver.
 
 - Define a GPIO compatible per SoC in the Tegra driver.
 
 - Push Tegra initialization down in the initlevels.
 
 - Support external wakeup interrupts on the Exynos.
 
 - Add generic clocks pins to the meson driver.
 
 - Add USB and HSCIF pins for some Renesas PFC chips.
 
 - Suspend/resume support in the armada-37xx.
 
 - Interrupt support for the Actions Semiconductor S900 also
   known as "owl".
 
 - Correct the pin ordering in Cedarfork.
 
 - Debugfs output for INTF in the mcp23s08 driver
 
 - Avoid divisions in context save/restore in pinctrl-single.
 
 The rest is minor bug fixes or cleanups.
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Merge tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v4.19:

  Core changes:

   - Augment pinctrl_generic_add_group() and pinmux_generic_add_function()
     to return the selector for the added group/function to the caller
     and augment (hopefully) all drivers to handle this

  New subdrivers:

   - Qualcomm PM8998 and PM8005 are supported in the SPMI pin control
     and GPIO driver

   - Intel Ice Lake PCH (platform controller hub) support

   - NXP (ex Freescale) i.MX8MQ support

   - Berlin AS370 support

  Improvements to drivers:

   - Support interrupts on the Ocelot pin controller

   - Add SPI pins to the Uniphier driver

   - Define a GPIO compatible per SoC in the Tegra driver

   - Push Tegra initialization down in the initlevels

   - Support external wakeup interrupts on the Exynos

   - Add generic clocks pins to the meson driver

   - Add USB and HSCIF pins for some Renesas PFC chips

   - Suspend/resume support in the armada-37xx

   - Interrupt support for the Actions Semiconductor S900 also known as
     "owl"

   - Correct the pin ordering in Cedarfork

   - Debugfs output for INTF in the mcp23s08 driver

   - Avoid divisions in context save/restore in pinctrl-single

  The rest is minor bug fixes or cleanups"

* tag 'pinctrl-v4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (69 commits)
  pinctrl: nomadik: silence uninitialized variable warning
  pinctrl: axp209: Fix NULL pointer dereference after allocation
  pinctrl: samsung: Remove duplicated "wakeup" in printk
  pinctrl: ocelot: add support for interrupt controller
  pinctrl: intel: Don't shadow error code of gpiochip_lock_as_irq()
  pinctrl: berlin: fix 'pctrl->functions' allocation in berlin_pinctrl_build_state
  gpio: tegra: Move driver registration to subsys_init level
  pinctrl: tegra: Move drivers registration to arch_init level
  pinctrl: baytrail: actually print the apparently misconfigured pin
  MAINTAINERS: Replace Heikki as maintainer of Intel pinctrl
  pinctrl: freescale: off by one in imx1_pinconf_group_dbg_show()
  pinctrl: uniphier: add spi pin-mux settings
  pinctrl: cannonlake: Fix community ordering for H variant
  pinctrl: tegra: define GPIO compatible node per SoC
  pinctrl: intel: Do pin translation when lock IRQ
  pinctrl: imx: off by one in imx_pinconf_group_dbg_show()
  pinctrl: mediatek: include chained_irq.h header
  pinctrl/amd: only handle irq if it is pending and unmasked
  pinctrl/amd: fix gpio irq level in debugfs
  pinctrl: stm32: add syscfg mask parameter
  ...
This commit is contained in:
Linus Torvalds 2018-08-14 12:31:27 -07:00
parent 3860cae64c c2944a9a09
commit c6ed444fd6
99 changed files with 2936 additions and 302 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
View File

@ -19,6 +19,10 @@ Required Properties:
defines the interrupt number, the second encodes
the trigger flags described in
bindings/interrupt-controller/interrupts.txt
- interrupts: The interrupt outputs from the controller. There is one GPIO
interrupt per GPIO bank. The number of interrupts listed depends
on the number of GPIO banks on the SoC. The interrupts must be
ordered by bank, starting with bank 0.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@ -180,6 +184,12 @@ Example:
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
uart2-default: uart2-default {
pinmux {

3
Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
View File

@ -36,6 +36,8 @@ Optional properties:
- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
input-debounce, output-low, output-high.
- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for
high drive. The default value is low drive.
Example:
@ -66,6 +68,7 @@ Example:
pinmux = <PIN_PB0>,
<PIN_PB5>;
bias-pull-up;
atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
};
pinctrl_sdmmc1_default: sdmmc1_default {

3
Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt
View File

@ -23,7 +23,8 @@ Required properties:
"marvell,berlin2q-system-pinctrl",
"marvell,berlin4ct-avio-pinctrl",
"marvell,berlin4ct-soc-pinctrl",
"marvell,berlin4ct-system-pinctrl"
"marvell,berlin4ct-system-pinctrl",
"syna,as370-soc-pinctrl"
Required subnode-properties:
- groups: a list of strings describing the group names.

36
Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.txt Normal file
View File

@ -0,0 +1,36 @@
* Freescale IMX8MQ IOMUX Controller
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
Required properties:
- compatible: "fsl,imx8mq-iomuxc"
- reg: should contain the base physical address and size of the iomuxc
registers.
Required properties in sub-nodes:
- fsl,pins: each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
imx8mq-pinfunc.h under device tree source folder. The last integer CONFIG is
the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad
Reference Manual for detailed CONFIG settings.
Examples:
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x0 0x30330000 0x0 0x10000>;
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>;
};
};

6
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
View File

@ -10,6 +10,11 @@ Required properties:
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -67,6 +72,7 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&gsbi5_uart_default>;
gpio-ranges = <&msmgpio 0 0 90>;
gsbi5_uart_default: gsbi5_uart_default {
mux {

9
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
View File

@ -40,6 +40,14 @@ MSM8960 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -154,6 +162,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 147>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;

6
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
View File

@ -13,6 +13,11 @@ Required properties:
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -64,6 +69,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 100>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;

6
Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt
View File

@ -10,6 +10,11 @@ Required properties:
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -67,6 +72,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 0 69>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 32 0x4>;

9
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
View File

@ -40,6 +40,14 @@ IPQ8074 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -148,6 +156,7 @@ Example:
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 70>;
interrupt-controller;
#interrupt-cells = <2>;

9
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt
View File

@ -40,6 +40,14 @@ MDM9615 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -127,6 +135,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 88>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;

6
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.txt
View File

@ -10,6 +10,11 @@ Required properties:
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -62,6 +67,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 173>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;

9
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.txt
View File

@ -40,6 +40,14 @@ MSM8916 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -162,6 +170,7 @@ Example:
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 122>;
interrupt-controller;
#interrupt-cells = <2>;

9
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt
View File

@ -40,6 +40,14 @@ MSM8960 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -156,6 +164,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 152>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 16 0x4>;

6
Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
View File

@ -10,6 +10,11 @@ Required properties:
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt
Optional properties:
- gpio-reserved-ranges: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -87,6 +92,7 @@ Example:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 146>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;

9
Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt
View File

@ -42,6 +42,14 @@ MSM8994 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -160,6 +168,7 @@ Example:
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&msmgpio 0 0 146>;
interrupt-controller;
#interrupt-cells = <2>;

9
Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.txt
View File

@ -40,6 +40,14 @@ MSM8996 platform.
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- gpio-ranges:
Usage: required
Definition: see ../gpio/gpio.txt
- gpio-reserved-ranges:
Usage: optional
Definition: see ../gpio/gpio.txt
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
@ -180,6 +188,7 @@ Example:
reg = <0x01010000 0x300000>;
interrupts = <0 208 0>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 150>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;

6
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View File

@ -7,6 +7,7 @@ PMIC's from Qualcomm.
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,pm8005-gpio"
"qcom,pm8018-gpio"
"qcom,pm8038-gpio"
"qcom,pm8058-gpio"
@ -15,7 +16,7 @@ PMIC's from Qualcomm.
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pmi8994-gpio"
"qcom,pm8998-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8994-gpio"
@ -78,6 +79,7 @@ to specify in a pin configuration subnode:
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio1-gpio4 for pm8005
gpio1-gpio6 for pm8018
gpio1-gpio12 for pm8038
gpio1-gpio40 for pm8058
@ -86,7 +88,7 @@ to specify in a pin configuration subnode:
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio10 for pmi8994
gpio1-gpio26 for pm8998
gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994

11
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
View File

@ -145,8 +145,13 @@ A. External GPIO Interrupts: For supporting external gpio interrupts, the
B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
child node representing the external wakeup interrupt controller should be
included in the pin-controller device node. This child node should include
the following properties.
included in the pin-controller device node.
Only one pin-controller device node can include external wakeup interrupts
child node (in other words, only one External Wakeup Interrupts
pin-controller is supported).
This child node should include following properties:
- compatible: identifies the type of the external wakeup interrupt controller
The possible values are:
@ -156,6 +161,8 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
found on Samsung S3C2412 and S3C2413 SoCs,
- samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C64xx SoCs,
- samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller
found on Samsung S5Pv210 SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
- samsung,exynos7-wakeup-eint: represents wakeup interrupt controller

9
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
View File

@ -39,9 +39,10 @@ Optional properties:
- reset: : Reference to the reset controller
- interrupt-parent: phandle of the interrupt parent to which the external
GPIO interrupts are forwarded to.
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
which includes IRQ mux selection register, and the offset of the IRQ mux
selection register.
- st,syscfg: Should be phandle/offset/mask.
-The phandle to the syscon node which includes IRQ mux selection register.
-The offset of the IRQ mux selection register
-The field mask of IRQ mux, needed if different of 0xf.
- gpio-ranges: Define a dedicated mapping between a pin-controller and
a gpio controller. Format is <&phandle a b c> with:
-(phandle): phandle of pin-controller.
@ -55,6 +56,8 @@ Optional properties:
NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
have to use a "gpio-ranges" entry.
More details in Documentation/devicetree/bindings/gpio/gpio.txt.
- st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line
used to select GPIOs as interrupts).
Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>

2
MAINTAINERS
View File

@ -11263,7 +11263,7 @@ F: Documentation/devicetree/bindings/pinctrl/fsl,*
PIN CONTROLLER - INTEL
M: Mika Westerberg <mika.westerberg@linux.intel.com>
M: Heikki Krogerus <heikki.krogerus@linux.intel.com>
M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
S: Maintained
F: drivers/pinctrl/intel/

2
arch/arm/mach-exynos/suspend.c
View File

@ -272,7 +272,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
static void exynos_pm_set_wakeup_mask(void)
{
/* Set wake-up mask registers */
pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
pmu_raw_writel(exynos_get_eint_wake_mask(), EXYNOS_EINT_WAKEUP_MASK);
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}

2
drivers/gpio/gpio-tegra.c
View File

@ -720,4 +720,4 @@ static int __init tegra_gpio_init(void)
{
return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);
subsys_initcall(tegra_gpio_init);

9
drivers/pinctrl/Kconfig
View File

@ -161,10 +161,10 @@ config PINCTRL_MCP23S08
select REGMAP_SPI if SPI_MASTER
select GENERIC_PINCONF
help
SPI/I2C driver for Microchip MCP23S08/MCP23S17/MCP23008/MCP23017
I/O expanders.
This provides a GPIO interface supporting inputs and outputs.
The I2C versions of the chips can be used as interrupt-controller.
SPI/I2C driver for Microchip MCP23S08 / MCP23S17 / MCP23S18 /
MCP23008 / MCP23017 / MCP23018 I/O expanders.
This provides a GPIO interface supporting inputs and outputs and a
corresponding interrupt-controller.
config PINCTRL_OXNAS
bool
@ -332,6 +332,7 @@ config PINCTRL_OCELOT
depends on OF
depends on MSCC_OCELOT || COMPILE_TEST
select GPIOLIB
select GPIOLIB_IRQCHIP
select GENERIC_PINCONF
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS

1
drivers/pinctrl/actions/Kconfig
View File

@ -5,6 +5,7 @@ config PINCTRL_OWL
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
help
Say Y here to enable Actions Semi OWL pinctrl driver

270
drivers/pinctrl/actions/pinctrl-owl.c
View File

@ -13,6 +13,7 @@
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@ -45,6 +46,9 @@ struct owl_pinctrl {
struct clk *clk;
const struct owl_pinctrl_soc_data *soc;
void __iomem *base;
struct irq_chip irq_chip;
unsigned int num_irq;
unsigned int *irq;
};
static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
@ -701,10 +705,213 @@ static int owl_gpio_direction_output(struct gpio_chip *chip,
return 0;
}
static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
{
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
unsigned int offset, value, irq_type = 0;
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
/*
* Since the hardware doesn't support interrupts on both edges,
* emulate it in the software by setting the single edge
* interrupt and switching to the opposite edge while ACKing
* the interrupt
*/
if (owl_gpio_get(&pctrl->chip, gpio))
irq_type = OWL_GPIO_INT_EDGE_FALLING;
else
irq_type = OWL_GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_RISING:
irq_type = OWL_GPIO_INT_EDGE_RISING;
break;
case IRQ_TYPE_EDGE_FALLING:
irq_type = OWL_GPIO_INT_EDGE_FALLING;
break;
case IRQ_TYPE_LEVEL_HIGH:
irq_type = OWL_GPIO_INT_LEVEL_HIGH;
break;
case IRQ_TYPE_LEVEL_LOW:
irq_type = OWL_GPIO_INT_LEVEL_LOW;
break;
default:
break;
}
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
offset = (gpio < 16) ? 4 : 0;
value = readl_relaxed(gpio_base + port->intc_type + offset);
value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
value |= irq_type << ((gpio % 16) * 2);
writel_relaxed(value, gpio_base + port->intc_type + offset);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_mask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
unsigned int gpio = data->hwirq;
u32 val;
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
/* disable port interrupt if no interrupt pending bit is active */
val = readl_relaxed(gpio_base + port->intc_msk);
if (val == 0)
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_ENABLE, false);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_unmask(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
unsigned int gpio = data->hwirq;
u32 value;
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
/* enable port interrupt */
value = readl_relaxed(gpio_base + port->intc_ctl);
value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
writel_relaxed(value, gpio_base + port->intc_ctl);
/* enable GPIO interrupt */
owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void owl_gpio_irq_ack(struct irq_data *data)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
const struct owl_gpio_port *port;
void __iomem *gpio_base;
unsigned long flags;
unsigned int gpio = data->hwirq;
/*
* Switch the interrupt edge to the opposite edge of the interrupt
* which got triggered for the case of emulating both edges
*/
if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
if (owl_gpio_get(gc, gpio))
irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
else
irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
}
port = owl_gpio_get_port(pctrl, &gpio);
if (WARN_ON(port == NULL))
return;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->intc_ctl,
OWL_GPIO_CTLR_PENDING, true);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
irq_set_handler_locked(data, handle_level_irq);
else
irq_set_handler_locked(data, handle_edge_irq);
irq_set_type(pctrl, data->hwirq, type);
return 0;
}
static void owl_gpio_irq_handler(struct irq_desc *desc)
{
struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *domain = pctrl->chip.irq.domain;
unsigned int parent = irq_desc_get_irq(desc);
const struct owl_gpio_port *port;
void __iomem *base;
unsigned int pin, irq, offset = 0, i;
unsigned long pending_irq;
chained_irq_enter(chip, desc);
for (i = 0; i < pctrl->soc->nports; i++) {
port = &pctrl->soc->ports[i];
base = pctrl->base + port->offset;
/* skip ports that are not associated with this irq */
if (parent != pctrl->irq[i])
goto skip;
pending_irq = readl_relaxed(base + port->intc_pd);
for_each_set_bit(pin, &pending_irq, port->pins) {
irq = irq_find_mapping(domain, offset + pin);
generic_handle_irq(irq);
/* clear pending interrupt */
owl_gpio_update_reg(base + port->intc_pd, pin, true);
}
skip:
offset += port->pins;
}
chained_irq_exit(chip, desc);
}
static int owl_gpio_init(struct owl_pinctrl *pctrl)
{
struct gpio_chip *chip;
int ret;
struct gpio_irq_chip *gpio_irq;
int ret, i, j, offset;
chip = &pctrl->chip;
chip->base = -1;
@ -714,6 +921,35 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl)
chip->owner = THIS_MODULE;
chip->of_node = pctrl->dev->of_node;
pctrl->irq_chip.name = chip->of_node->name;
pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
gpio_irq = &chip->irq;
gpio_irq->chip = &pctrl->irq_chip;
gpio_irq->handler = handle_simple_irq;
gpio_irq->default_type = IRQ_TYPE_NONE;
gpio_irq->parent_handler = owl_gpio_irq_handler;
gpio_irq->parent_handler_data = pctrl;
gpio_irq->num_parents = pctrl->num_irq;
gpio_irq->parents = pctrl->irq;
gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
sizeof(*gpio_irq->map), GFP_KERNEL);
if (!gpio_irq->map)
return -ENOMEM;
for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
const struct owl_gpio_port *port = &pctrl->soc->ports[i];
for (j = 0; j < port->pins; j++)
gpio_irq->map[offset + j] = gpio_irq->parents[i];
offset += port->pins;
}
ret = gpiochip_add_data(&pctrl->chip, pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to register gpiochip\n");
@ -728,7 +964,7 @@ int owl_pinctrl_probe(struct platform_device *pdev,
{
struct resource *res;
struct owl_pinctrl *pctrl;
int ret;
int ret, i;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
@ -772,14 +1008,40 @@ int owl_pinctrl_probe(struct platform_device *pdev,
&owl_pinctrl_desc, pctrl);
if (IS_ERR(pctrl->pctrldev)) {
dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
return PTR_ERR(pctrl->pctrldev);
ret = PTR_ERR(pctrl->pctrldev);
goto err_exit;
}
ret = platform_irq_count(pdev);
if (ret < 0)
goto err_exit;
pctrl->num_irq = ret;
pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
sizeof(*pctrl->irq), GFP_KERNEL);
if (!pctrl->irq) {
ret = -ENOMEM;
goto err_exit;
}
for (i = 0; i < pctrl->num_irq ; i++) {
ret = platform_get_irq(pdev, i);
if (ret < 0)
goto err_exit;
pctrl->irq[i] = ret;
}
ret = owl_gpio_init(pctrl);
if (ret)
return ret;
goto err_exit;
platform_set_drvdata(pdev, pctrl);
return 0;
err_exit:
clk_disable_unprepare(pctrl->clk);
return ret;
}

22
drivers/pinctrl/actions/pinctrl-owl.h
View File

@ -29,6 +29,18 @@ enum owl_pinconf_drv {
OWL_PINCONF_DRV_12MA,
};
/* GPIO CTRL Bit Definition */
#define OWL_GPIO_CTLR_PENDING 0
#define OWL_GPIO_CTLR_ENABLE 1
#define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2
/* GPIO TYPE Bit Definition */
#define OWL_GPIO_INT_LEVEL_HIGH 0
#define OWL_GPIO_INT_LEVEL_LOW 1
#define OWL_GPIO_INT_EDGE_RISING 2
#define OWL_GPIO_INT_EDGE_FALLING 3
#define OWL_GPIO_INT_MASK 3
/**
* struct owl_pullctl - Actions pad pull control register
* @reg: offset to the pull control register
@ -121,6 +133,10 @@ struct owl_pinmux_func {
* @outen: offset of the output enable register.
* @inen: offset of the input enable register.
* @dat: offset of the data register.
* @intc_ctl: offset of the interrupt control register.
* @intc_pd: offset of the interrupt pending register.
* @intc_msk: offset of the interrupt mask register.
* @intc_type: offset of the interrupt type register.
*/
struct owl_gpio_port {
unsigned int offset;
@ -128,6 +144,10 @@ struct owl_gpio_port {
unsigned int outen;
unsigned int inen;
unsigned int dat;
unsigned int intc_ctl;
unsigned int intc_pd;
unsigned int intc_msk;
unsigned int intc_type;
};
/**
@ -140,7 +160,7 @@ struct owl_gpio_port {
* @ngroups: number of entries in @groups.
* @padinfo: array describing the pad info of this SoC.
* @ngpios: number of pingroups the driver should expose as GPIOs.
* @port: array describing all GPIO ports of this SoC.
* @ports: array describing all GPIO ports of this SoC.
* @nports: number of GPIO ports in this SoC.
*/
struct owl_pinctrl_soc_data {

19
drivers/pinctrl/actions/pinctrl-s900.c
View File

@ -1821,22 +1821,27 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = {
[SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
};
#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat) \
#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
_intc_ctl, _intc_pd, _intc_msk, _intc_type) \
[OWL_GPIO_PORT_##port] = { \
.offset = base, \
.pins = count, \
.outen = _outen, \
.inen = _inen, \
.dat = _dat, \
.intc_ctl = _intc_ctl, \
.intc_pd = _intc_pd, \
.intc_msk = _intc_msk, \
.intc_type = _intc_type, \
}
static const struct owl_gpio_port s900_gpio_ports[] = {
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8)
OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
};
static struct owl_pinctrl_soc_data s900_pinctrl_data = {

4
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View File

@ -95,7 +95,7 @@ static inline void aspeed_sig_desc_print_val(
*
* @desc: The signal descriptor of interest
* @enabled: True to query the enabled state, false to query disabled state
* @regmap: The IP block's regmap instance
* @map: The IP block's regmap instance
*
* Return: 1 if the descriptor's bitfield is configured to the state
* selected by @enabled, 0 if not, and less than zero if an unrecoverable
@ -594,7 +594,7 @@ static inline const struct aspeed_pin_config *find_pinconf_config(
/**
* @param: pinconf configuration parameter
* @arg: The supported argument for @param, or -1 if any value is supported
* @value: The register value to write to configure @arg for @param
* @val: The register value to write to configure @arg for @param
*
* The map is to be used in conjunction with the configuration array supplied
* by the driver implementation.

5
drivers/pinctrl/berlin/Kconfig
View File

@ -5,6 +5,11 @@ config PINCTRL_BERLIN
select PINMUX
select REGMAP_MMIO
config PINCTRL_AS370
bool "Synaptics as370 pin controller driver"
depends on OF
select PINCTRL_BERLIN
config PINCTRL_BERLIN_BG2
def_bool MACH_BERLIN_BG2
depends on OF

1
drivers/pinctrl/berlin/Makefile
View File

@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o
obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o
obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o
obj-$(CONFIG_PINCTRL_BERLIN_BG4CT) += berlin-bg4ct.o
obj-$(CONFIG_PINCTRL_AS370) += pinctrl-as370.o

14
drivers/pinctrl/berlin/berlin.c
View File

@ -216,10 +216,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
}
/* we will reallocate later */
pctrl->functions = devm_kcalloc(&pdev->dev,
max_functions,
sizeof(*pctrl->functions),
GFP_KERNEL);
pctrl->functions = kcalloc(max_functions,
sizeof(*pctrl->functions), GFP_KERNEL);
if (!pctrl->functions)
return -ENOMEM;
@ -257,8 +255,10 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
function++;
}
if (!found)
if (!found) {
kfree(pctrl->functions);
return -EINVAL;
}
if (!function->groups) {
function->groups =
@ -267,9 +267,11 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
sizeof(char *),
GFP_KERNEL);
if (!function->groups)
if (!function->groups) {
kfree(pctrl->functions);
return -ENOMEM;
}
}
groups = function->groups;
while (*groups)

368
drivers/pinctrl/berlin/pinctrl-as370.c Normal file
View File

@ -0,0 +1,368 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Synaptics AS370 pinctrl driver
*
* Copyright (C) 2018 Synaptics Incorporated
*
* Author: Jisheng Zhang <jszhang@kernel.org>
*/
#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "berlin.h"
static const struct berlin_desc_group as370_soc_pinctrl_groups[] = {
BERLIN_PINCTRL_GROUP("I2S1_BCLKIO", 0x0, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO0 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG0 */
BERLIN_PINCTRL_GROUP("I2S1_LRCKIO", 0x0, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO1 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG1 */
BERLIN_PINCTRL_GROUP("I2S1_DO0", 0x0, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 1P8V RSTB*/
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO0 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO2 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG2 */
BERLIN_PINCTRL_GROUP("I2S1_DO1", 0x0, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* 3P3V RSTB */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO1 */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO3 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG3 */
BERLIN_PINCTRL_GROUP("I2S1_DO2", 0x0, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* CORE RSTB */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO2 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm4"),
BERLIN_PINCTRL_FUNCTION(0x3, "gpio"), /* GPIO4 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG4 */
BERLIN_PINCTRL_GROUP("I2S1_DO3", 0x0, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm5"),
BERLIN_PINCTRL_FUNCTION(0x3, "spififib"), /* SPDIFIB */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG5 */
BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG6 */
BERLIN_PINCTRL_GROUP("I2S2_BCLKIO", 0x0, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO7 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG7 */
BERLIN_PINCTRL_GROUP("I2S2_LRCKIO", 0x0, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO8 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG8 */
BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x0, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO9 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG9 */
BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO10 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG10 */
BERLIN_PINCTRL_GROUP("I2S2_DI2", 0x4, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO11 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI2 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm6"),
BERLIN_PINCTRL_FUNCTION(0x3, "spdific"), /* SPDIFIC */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG11 */
BERLIN_PINCTRL_GROUP("I2S2_DI3", 0x4, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO12 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm7"),
BERLIN_PINCTRL_FUNCTION(0x3, "spdifia"), /* SPDIFIA */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG12 */
BERLIN_PINCTRL_GROUP("PDM_CLKO", 0x4, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO13 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* CLKO */
BERLIN_PINCTRL_FUNCTION(0x2, "i2s2"), /* MCLK */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG13 */
BERLIN_PINCTRL_GROUP("PDM_DI0", 0x4, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO14 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI0 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG14 */
BERLIN_PINCTRL_GROUP("PDM_DI1", 0x4, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI1 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG15 */
BERLIN_PINCTRL_GROUP("PDM_DI2", 0x4, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI2 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm4"),
BERLIN_PINCTRL_FUNCTION(0x3, "spdifid"), /* SPDIFID */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG16 */
BERLIN_PINCTRL_GROUP("PDM_DI3", 0x4, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */
BERLIN_PINCTRL_FUNCTION(0x1, "pdm"), /* DI3 */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm5"),
BERLIN_PINCTRL_FUNCTION(0x3, "spdifi"), /* SPDIFI */
BERLIN_PINCTRL_FUNCTION(0x4, "spdifo"), /* SPDIFO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG17 */
BERLIN_PINCTRL_GROUP("NAND_IO0", 0x4, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA0 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie0")), /* MDIO */
BERLIN_PINCTRL_GROUP("NAND_IO1", 0x4, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA1 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie0")), /* MDC */
BERLIN_PINCTRL_GROUP("NAND_IO2", 0x8, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO2 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA2 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie1")), /* MDIO */
BERLIN_PINCTRL_GROUP("NAND_IO3", 0x8, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO3 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* DATA3 */
BERLIN_PINCTRL_FUNCTION(0x4, "pcie1")), /* MDC */
BERLIN_PINCTRL_GROUP("NAND_IO4", 0x8, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO4 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA4 */
BERLIN_PINCTRL_GROUP("NAND_IO5", 0x8, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO5 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA5 */
BERLIN_PINCTRL_GROUP("NAND_IO6", 0x8, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO6 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA6 */
BERLIN_PINCTRL_GROUP("NAND_IO7", 0x8, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO7 */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc")), /* DATA7 */
BERLIN_PINCTRL_GROUP("NAND_ALE", 0x8, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm6"),
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO18 */
BERLIN_PINCTRL_GROUP("NAND_CLE", 0x8, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm7"),
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO19 */
BERLIN_PINCTRL_GROUP("NAND_WEn", 0x8, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO20 */
BERLIN_PINCTRL_GROUP("NAND_REn", 0x8, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* REn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO21 */
BERLIN_PINCTRL_GROUP("NAND_WPn", 0xc, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WPn */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* CLK */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO22 */
BERLIN_PINCTRL_GROUP("NAND_CEn", 0xc, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CEn */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* RSTn */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO23 */
BERLIN_PINCTRL_GROUP("NAND_RDY", 0xc, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* RDY */
BERLIN_PINCTRL_FUNCTION(0x1, "emmc"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO24 */
BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO25 */
BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), /* GPIO26 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm2")),
BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0xc, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio"), /* GPIO27 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm3")),
BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0xc, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */
BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO28 */
BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0xc, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO29 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm4")),
BERLIN_PINCTRL_GROUP("SPI1_SDO", 0xc, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO30 */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm5")),
BERLIN_PINCTRL_GROUP("SPI1_SDI", 0xc, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO31 */
BERLIN_PINCTRL_GROUP("USB0_DRV_VBUS", 0x10, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "usb0"), /* VBUS */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO32 */
BERLIN_PINCTRL_FUNCTION(0x3, "refclko")), /* 25M */
BERLIN_PINCTRL_GROUP("TW1_SCL", 0x10, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw1")), /* SCL */
BERLIN_PINCTRL_GROUP("TW1_SDA", 0x10, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw1")), /* SDA */
BERLIN_PINCTRL_GROUP("TW0_SCL", 0x10, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SCL */
BERLIN_PINCTRL_GROUP("TW0_SDA", 0x10, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */
BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SDA */
BERLIN_PINCTRL_GROUP("TMS", 0x10, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")),
BERLIN_PINCTRL_GROUP("TDI", 0x10, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm1")),
BERLIN_PINCTRL_GROUP("TDO", 0x10, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */
BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */
BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")),
BERLIN_PINCTRL_GROUP("PWM6", 0x10, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO40 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm6")),
BERLIN_PINCTRL_GROUP("PWM7", 0x10, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO41 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm7")),
BERLIN_PINCTRL_GROUP("PWM0", 0x14, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "por"), /* VDDCPUSOC RSTB */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm0"),
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO42 */
BERLIN_PINCTRL_GROUP("PWM1", 0x14, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO43 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm1")),
BERLIN_PINCTRL_GROUP("PWM2", 0x14, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm2")),
BERLIN_PINCTRL_GROUP("PWM3", 0x14, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm3")),
BERLIN_PINCTRL_GROUP("PWM4", 0x14, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm4")),
BERLIN_PINCTRL_GROUP("PWM5", 0x14, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO47 */
BERLIN_PINCTRL_FUNCTION(0x1, "pwm5")),
BERLIN_PINCTRL_GROUP("URT1_RTSn", 0x14, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO48 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RTSn */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm6"),
BERLIN_PINCTRL_FUNCTION(0x3, "tw1a"), /* SCL */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG0 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG18 */
BERLIN_PINCTRL_GROUP("URT1_CTSn", 0x14, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO49 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* CTSn */
BERLIN_PINCTRL_FUNCTION(0x2, "pwm7"),
BERLIN_PINCTRL_FUNCTION(0x3, "tw1a"), /* SDA */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG1 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG19 */
BERLIN_PINCTRL_GROUP("URT1_RXD", 0x14, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO50 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RXD */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG2 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG20 */
BERLIN_PINCTRL_GROUP("URT1_TXD", 0x14, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO51 */
BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* TXD */
BERLIN_PINCTRL_FUNCTION(0x4, "aio"), /* DBG3 */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG21 */
BERLIN_PINCTRL_GROUP("I2S3_DI", 0x18, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO52 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* DI */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG22 */
BERLIN_PINCTRL_GROUP("I2S3_DO", 0x18, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO53 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* DO */
BERLIN_PINCTRL_FUNCTION(0x5, "phy")), /* DBG23 */
BERLIN_PINCTRL_GROUP("I2S3_BCLKIO", 0x18, 0x3, 0x06,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO54 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3"), /* BCLKIO */
BERLIN_PINCTRL_FUNCTION(0x5, "clk")), /* DBG */
BERLIN_PINCTRL_GROUP("I2S3_LRCKIO", 0x18, 0x3, 0x09,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO55 */
BERLIN_PINCTRL_FUNCTION(0x1, "i2s3")), /* LRCKIO */
BERLIN_PINCTRL_GROUP("SD0_DAT0", 0x18, 0x3, 0x0c,
BERLIN_PINCTRL_FUNCTION(0x0, "cpupll"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT0 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO56 */
BERLIN_PINCTRL_GROUP("SD0_DAT1", 0x18, 0x3, 0x0f,
BERLIN_PINCTRL_FUNCTION(0x0, "syspll"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT1 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO57 */
BERLIN_PINCTRL_GROUP("SD0_CLK", 0x18, 0x3, 0x12,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO58 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0")), /* CLK */
BERLIN_PINCTRL_GROUP("SD0_DAT2", 0x18, 0x3, 0x15,
BERLIN_PINCTRL_FUNCTION(0x0, "mempll"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT2 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO59 */
BERLIN_PINCTRL_GROUP("SD0_DAT3", 0x18, 0x3, 0x18,
BERLIN_PINCTRL_FUNCTION(0x0, "apll0"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT3 */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO60 */
BERLIN_PINCTRL_GROUP("SD0_CMD", 0x18, 0x3, 0x1b,
BERLIN_PINCTRL_FUNCTION(0x0, "apll1"), /* OUT */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CMD */
BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), /* GPIO61 */
BERLIN_PINCTRL_GROUP("SD0_CDn", 0x1c, 0x3, 0x00,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO62 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm2")),
BERLIN_PINCTRL_GROUP("SD0_WP", 0x1c, 0x3, 0x03,
BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO63 */
BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */
BERLIN_PINCTRL_FUNCTION(0x3, "pwm3")),
};
static const struct berlin_pinctrl_desc as370_soc_pinctrl_data = {
.groups = as370_soc_pinctrl_groups,
.ngroups = ARRAY_SIZE(as370_soc_pinctrl_groups),
};
static const struct of_device_id as370_pinctrl_match[] = {
{
.compatible = "syna,as370-soc-pinctrl",
.data = &as370_soc_pinctrl_data,
},
{}
};
static int as370_pinctrl_probe(struct platform_device *pdev)
{
const struct of_device_id *match =
of_match_device(as370_pinctrl_match, &pdev->dev);
struct regmap_config *rmconfig;
struct regmap *regmap;
struct resource *res;
void __iomem *base;
rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
if (!rmconfig)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
rmconfig->reg_bits = 32,
rmconfig->val_bits = 32,
rmconfig->reg_stride = 4,
rmconfig->max_register = resource_size(res);
regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return berlin_pinctrl_probe_regmap(pdev, match->data, regmap);
}
static struct platform_driver as370_pinctrl_driver = {
.probe = as370_pinctrl_probe,
.driver = {
.name = "as370-pinctrl",
.of_match_table = as370_pinctrl_match,
},
};
builtin_platform_driver(as370_pinctrl_driver);

36
drivers/pinctrl/core.c
View File

@ -21,7 +21,6 @@
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/list.h>
#include <linux/sysfs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/consumer.h>
@ -617,6 +616,26 @@ struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
}
EXPORT_SYMBOL_GPL(pinctrl_generic_get_group);
static int pinctrl_generic_group_name_to_selector(struct pinctrl_dev *pctldev,
const char *function)
{
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
int ngroups = ops->get_groups_count(pctldev);
int selector = 0;
/* See if this pctldev has this group */
while (selector < ngroups) {
const char *gname = ops->get_group_name(pctldev, selector);
if (!strcmp(function, gname))
return selector;
selector++;
}
return -EINVAL;
}
/**
* pinctrl_generic_add_group() - adds a new pin group
* @pctldev: pin controller device
@ -631,6 +650,16 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
int *pins, int num_pins, void *data)
{
struct group_desc *group;
int selector;
if (!name)
return -EINVAL;
selector = pinctrl_generic_group_name_to_selector(pctldev, name);
if (selector >= 0)
return selector;
selector = pctldev->num_groups;
group = devm_kzalloc(pctldev->dev, sizeof(*group), GFP_KERNEL);
if (!group)
@ -641,12 +670,11 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
group->num_pins = num_pins;
group->data = data;
radix_tree_insert(&pctldev->pin_group_tree, pctldev->num_groups,
group);
radix_tree_insert(&pctldev->pin_group_tree, selector, group);
pctldev->num_groups++;
return 0;
return selector;
}
EXPORT_SYMBOL_GPL(pinctrl_generic_add_group);

6
drivers/pinctrl/core.h
View File

@ -218,12 +218,6 @@ int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
unsigned int group_selector);
static inline int
pinctrl_generic_remove_last_group(struct pinctrl_dev *pctldev)
{
return pinctrl_generic_remove_group(pctldev, pctldev->num_groups - 1);
}
#endif /* CONFIG_GENERIC_PINCTRL_GROUPS */
struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);

7
drivers/pinctrl/freescale/Kconfig
View File

@ -117,6 +117,13 @@ config PINCTRL_IMX7ULP
help
Say Y here to enable the imx7ulp pinctrl driver
config PINCTRL_IMX8MQ
bool "IMX8MQ pinctrl driver"
depends on SOC_IMX8MQ
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610

1
drivers/pinctrl/freescale/Makefile
View File

@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o

2
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -383,7 +383,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
const char *name;
int i, ret;
if (group > pctldev->num_groups)
if (group >= pctldev->num_groups)
return;
seq_puts(s, "\n");

2
drivers/pinctrl/freescale/pinctrl-imx1-core.c
View File

@ -429,7 +429,7 @@ static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
const char *name;
int i, ret;
if (group > info->ngroups)
if (group >= info->ngroups)
return;
seq_puts(s, "\n");

351
drivers/pinctrl/freescale/pinctrl-imx8mq.c Normal file
View File

@ -0,0 +1,351 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
* Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx8mq_pads {
MX8MQ_PAD_RESERVE0 = 0,
MX8MQ_PAD_RESERVE1 = 1,
MX8MQ_PAD_RESERVE2 = 2,
MX8MQ_PAD_RESERVE3 = 3,
MX8MQ_PAD_RESERVE4 = 4,
MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5,
MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6,
MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7,
MX8MQ_IOMUXC_POR_B_SNVSMIX = 8,
MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9,
MX8MQ_IOMUXC_GPIO1_IO00 = 10,
MX8MQ_IOMUXC_GPIO1_IO01 = 11,
MX8MQ_IOMUXC_GPIO1_IO02 = 12,
MX8MQ_IOMUXC_GPIO1_IO03 = 13,
MX8MQ_IOMUXC_GPIO1_IO04 = 14,
MX8MQ_IOMUXC_GPIO1_IO05 = 15,
MX8MQ_IOMUXC_GPIO1_IO06 = 16,
MX8MQ_IOMUXC_GPIO1_IO07 = 17,
MX8MQ_IOMUXC_GPIO1_IO08 = 18,
MX8MQ_IOMUXC_GPIO1_IO09 = 19,
MX8MQ_IOMUXC_GPIO1_IO10 = 20,
MX8MQ_IOMUXC_GPIO1_IO11 = 21,
MX8MQ_IOMUXC_GPIO1_IO12 = 22,
MX8MQ_IOMUXC_GPIO1_IO13 = 23,
MX8MQ_IOMUXC_GPIO1_IO14 = 24,
MX8MQ_IOMUXC_GPIO1_IO15 = 25,
MX8MQ_IOMUXC_ENET_MDC = 26,
MX8MQ_IOMUXC_ENET_MDIO = 27,
MX8MQ_IOMUXC_ENET_TD3 = 28,
MX8MQ_IOMUXC_ENET_TD2 = 29,
MX8MQ_IOMUXC_ENET_TD1 = 30,
MX8MQ_IOMUXC_ENET_TD0 = 31,
MX8MQ_IOMUXC_ENET_TX_CTL = 32,
MX8MQ_IOMUXC_ENET_TXC = 33,
MX8MQ_IOMUXC_ENET_RX_CTL = 34,
MX8MQ_IOMUXC_ENET_RXC = 35,
MX8MQ_IOMUXC_ENET_RD0 = 36,
MX8MQ_IOMUXC_ENET_RD1 = 37,
MX8MQ_IOMUXC_ENET_RD2 = 38,
MX8MQ_IOMUXC_ENET_RD3 = 39,
MX8MQ_IOMUXC_SD1_CLK = 40,
MX8MQ_IOMUXC_SD1_CMD = 41,
MX8MQ_IOMUXC_SD1_DATA0 = 42,
MX8MQ_IOMUXC_SD1_DATA1 = 43,
MX8MQ_IOMUXC_SD1_DATA2 = 44,
MX8MQ_IOMUXC_SD1_DATA3 = 45,
MX8MQ_IOMUXC_SD1_DATA4 = 46,
MX8MQ_IOMUXC_SD1_DATA5 = 47,
MX8MQ_IOMUXC_SD1_DATA6 = 48,
MX8MQ_IOMUXC_SD1_DATA7 = 49,
MX8MQ_IOMUXC_SD1_RESET_B = 50,
MX8MQ_IOMUXC_SD1_STROBE = 51,
MX8MQ_IOMUXC_SD2_CD_B = 52,
MX8MQ_IOMUXC_SD2_CLK = 53,
MX8MQ_IOMUXC_SD2_CMD = 54,
MX8MQ_IOMUXC_SD2_DATA0 = 55,
MX8MQ_IOMUXC_SD2_DATA1 = 56,
MX8MQ_IOMUXC_SD2_DATA2 = 57,
MX8MQ_IOMUXC_SD2_DATA3 = 58,
MX8MQ_IOMUXC_SD2_RESET_B = 59,
MX8MQ_IOMUXC_SD2_WP = 60,
MX8MQ_IOMUXC_NAND_ALE = 61,
MX8MQ_IOMUXC_NAND_CE0_B = 62,
MX8MQ_IOMUXC_NAND_CE1_B = 63,
MX8MQ_IOMUXC_NAND_CE2_B = 64,
MX8MQ_IOMUXC_NAND_CE3_B = 65,
MX8MQ_IOMUXC_NAND_CLE = 66,
MX8MQ_IOMUXC_NAND_DATA00 = 67,
MX8MQ_IOMUXC_NAND_DATA01 = 68,
MX8MQ_IOMUXC_NAND_DATA02 = 69,
MX8MQ_IOMUXC_NAND_DATA03 = 70,
MX8MQ_IOMUXC_NAND_DATA04 = 71,
MX8MQ_IOMUXC_NAND_DATA05 = 72,
MX8MQ_IOMUXC_NAND_DATA06 = 73,
MX8MQ_IOMUXC_NAND_DATA07 = 74,
MX8MQ_IOMUXC_NAND_DQS = 75,
MX8MQ_IOMUXC_NAND_RE_B = 76,
MX8MQ_IOMUXC_NAND_READY_B = 77,
MX8MQ_IOMUXC_NAND_WE_B = 78,
MX8MQ_IOMUXC_NAND_WP_B = 79,
MX8MQ_IOMUXC_SAI5_RXFS = 80,
MX8MQ_IOMUXC_SAI5_RXC = 81,
MX8MQ_IOMUXC_SAI5_RXD0 = 82,
MX8MQ_IOMUXC_SAI5_RXD1 = 83,
MX8MQ_IOMUXC_SAI5_RXD2 = 84,
MX8MQ_IOMUXC_SAI5_RXD3 = 85,
MX8MQ_IOMUXC_SAI5_MCLK = 86,
MX8MQ_IOMUXC_SAI1_RXFS = 87,
MX8MQ_IOMUXC_SAI1_RXC = 88,
MX8MQ_IOMUXC_SAI1_RXD0 = 89,
MX8MQ_IOMUXC_SAI1_RXD1 = 90,
MX8MQ_IOMUXC_SAI1_RXD2 = 91,
MX8MQ_IOMUXC_SAI1_RXD3 = 92,
MX8MQ_IOMUXC_SAI1_RXD4 = 93,
MX8MQ_IOMUXC_SAI1_RXD5 = 94,
MX8MQ_IOMUXC_SAI1_RXD6 = 95,
MX8MQ_IOMUXC_SAI1_RXD7 = 96,
MX8MQ_IOMUXC_SAI1_TXFS = 97,
MX8MQ_IOMUXC_SAI1_TXC = 98,
MX8MQ_IOMUXC_SAI1_TXD0 = 99,
MX8MQ_IOMUXC_SAI1_TXD1 = 100,
MX8MQ_IOMUXC_SAI1_TXD2 = 101,
MX8MQ_IOMUXC_SAI1_TXD3 = 102,
MX8MQ_IOMUXC_SAI1_TXD4 = 103,
MX8MQ_IOMUXC_SAI1_TXD5 = 104,
MX8MQ_IOMUXC_SAI1_TXD6 = 105,
MX8MQ_IOMUXC_SAI1_TXD7 = 106,
MX8MQ_IOMUXC_SAI1_MCLK = 107,
MX8MQ_IOMUXC_SAI2_RXFS = 108,
MX8MQ_IOMUXC_SAI2_RXC = 109,
MX8MQ_IOMUXC_SAI2_RXD0 = 110,
MX8MQ_IOMUXC_SAI2_TXFS = 111,
MX8MQ_IOMUXC_SAI2_TXC = 112,
MX8MQ_IOMUXC_SAI2_TXD0 = 113,
MX8MQ_IOMUXC_SAI2_MCLK = 114,
MX8MQ_IOMUXC_SAI3_RXFS = 115,
MX8MQ_IOMUXC_SAI3_RXC = 116,
MX8MQ_IOMUXC_SAI3_RXD = 117,
MX8MQ_IOMUXC_SAI3_TXFS = 118,
MX8MQ_IOMUXC_SAI3_TXC = 119,
MX8MQ_IOMUXC_SAI3_TXD = 120,
MX8MQ_IOMUXC_SAI3_MCLK = 121,
MX8MQ_IOMUXC_SPDIF_TX = 122,
MX8MQ_IOMUXC_SPDIF_RX = 123,
MX8MQ_IOMUXC_SPDIF_EXT_CLK = 124,
MX8MQ_IOMUXC_ECSPI1_SCLK = 125,
MX8MQ_IOMUXC_ECSPI1_MOSI = 126,
MX8MQ_IOMUXC_ECSPI1_MISO = 127,
MX8MQ_IOMUXC_ECSPI1_SS0 = 128,
MX8MQ_IOMUXC_ECSPI2_SCLK = 129,
MX8MQ_IOMUXC_ECSPI2_MOSI = 130,
MX8MQ_IOMUXC_ECSPI2_MISO = 131,
MX8MQ_IOMUXC_ECSPI2_SS0 = 132,
MX8MQ_IOMUXC_I2C1_SCL = 133,
MX8MQ_IOMUXC_I2C1_SDA = 134,
MX8MQ_IOMUXC_I2C2_SCL = 135,
MX8MQ_IOMUXC_I2C2_SDA = 136,
MX8MQ_IOMUXC_I2C3_SCL = 137,
MX8MQ_IOMUXC_I2C3_SDA = 138,
MX8MQ_IOMUXC_I2C4_SCL = 139,
MX8MQ_IOMUXC_I2C4_SDA = 140,
MX8MQ_IOMUXC_UART1_RXD = 141,
MX8MQ_IOMUXC_UART1_TXD = 142,
MX8MQ_IOMUXC_UART2_RXD = 143,
MX8MQ_IOMUXC_UART2_TXD = 144,
MX8MQ_IOMUXC_UART3_RXD = 145,
MX8MQ_IOMUXC_UART3_TXD = 146,
MX8MQ_IOMUXC_UART4_RXD = 147,
MX8MQ_IOMUXC_UART4_TXD = 148,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO06),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO07),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO08),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO09),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO10),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO11),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO12),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO13),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO14),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO15),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDIO),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TX_CTL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RX_CTL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CMD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA5),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA6),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA7),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_RESET_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_STROBE),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CD_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CMD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_RESET_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_WP),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_ALE),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE0_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE1_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE2_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE3_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CLE),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA00),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA01),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA02),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA03),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA04),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA05),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA06),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA07),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DQS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_RE_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_READY_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WE_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WP_B),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD5),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD6),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD7),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD1),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD2),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD3),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD5),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD6),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD7),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXD0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXFS),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXC),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_MCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_TX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_RX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_EXT_CLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MOSI),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MISO),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SS0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SCLK),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MOSI),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MISO),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SS0),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SCL),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SDA),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_TXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_RXD),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_TXD),
};
static const struct imx_pinctrl_soc_info imx8mq_pinctrl_info = {
.pins = imx8mq_pinctrl_pads,
.npins = ARRAY_SIZE(imx8mq_pinctrl_pads),
.gpr_compatible = "fsl,imx8mq-iomuxc-gpr",
};
static const struct of_device_id imx8mq_pinctrl_of_match[] = {
{ .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, },
{ /* sentinel */ }
};
static int imx8mq_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx8mq_pinctrl_info);
}
static struct platform_driver imx8mq_pinctrl_driver = {
.driver = {
.name = "imx8mq-pinctrl",
.of_match_table = of_match_ptr(imx8mq_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imx8mq_pinctrl_probe,
};
static int __init imx8mq_pinctrl_init(void)
{
return platform_driver_register(&imx8mq_pinctrl_driver);
}
arch_initcall(imx8mq_pinctrl_init);

12
drivers/pinctrl/intel/Kconfig
View File

@ -1,6 +1,6 @@
#
# SPDX-License-Identifier: GPL-2.0
# Intel pin control drivers
#
if (X86 || COMPILE_TEST)
config PINCTRL_BAYTRAIL
@ -90,6 +90,14 @@ config PINCTRL_GEMINILAKE
This pinctrl driver provides an interface that allows configuring
of Intel Gemini Lake SoC pins and using them as GPIOs.
config PINCTRL_ICELAKE
tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Ice Lake PCH pins and using them as GPIOs.
config PINCTRL_LEWISBURG
tristate "Intel Lewisburg pinctrl and GPIO driver"
depends on ACPI

1
drivers/pinctrl/intel/Makefile
View File

@ -10,5 +10,6 @@ obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o
obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o

17
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1,17 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Pinctrl GPIO driver for Intel Baytrail
* Copyright (c) 2012-2013, Intel Corporation.
*
* Copyright (c) 2012-2013, Intel Corporation
* Author: Mathias Nyman <mathias.nyman@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/kernel.h>
@ -1542,11 +1534,13 @@ static void byt_irq_unmask(struct irq_data *d)
switch (irqd_get_trigger_type(d)) {
case IRQ_TYPE_LEVEL_HIGH:
value |= BYT_TRIG_LVL;
/* fall through */
case IRQ_TYPE_EDGE_RISING:
value |= BYT_TRIG_POS;
break;
case IRQ_TYPE_LEVEL_LOW:
value |= BYT_TRIG_LVL;
/* fall through */
case IRQ_TYPE_EDGE_FALLING:
value |= BYT_TRIG_NEG;
break;
@ -1691,7 +1685,8 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
value = readl(reg);
if (value)
dev_err(&vg->pdev->dev,
"GPIO interrupt error, pins misconfigured\n");
"GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
base / 32, value);
}
}

5
drivers/pinctrl/intel/pinctrl-broxton.c
View File

@ -1,12 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Broxton SoC pinctrl/GPIO driver
*
* Copyright (C) 2015, 2016 Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>

13
drivers/pinctrl/intel/pinctrl-cannonlake.c
View File

@ -1,13 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Cannon Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
@ -447,12 +444,8 @@ static const struct intel_function cnlh_functions[] = {
static const struct intel_community cnlh_communities[] = {
CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
/*
* ACPI MMIO resources are returned in reverse order for
* communities 3 and 4.
*/
CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
CNL_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
CNL_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnlh_soc_data = {

97
drivers/pinctrl/intel/pinctrl-cedarfork.c
View File

@ -1,12 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Cedar Fork PCH pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
@ -240,51 +237,51 @@ static const struct pinctrl_pin_desc cdf_pins[] = {
PINCTRL_PIN(179, "GBE_GPIO10"),
PINCTRL_PIN(180, "GBE_GPIO11"),
PINCTRL_PIN(181, "GBE_GPIO12"),
PINCTRL_PIN(182, "SATA0_LED_N"),
PINCTRL_PIN(183, "SATA1_LED_N"),
PINCTRL_PIN(184, "SATA_PDETECT0"),
PINCTRL_PIN(185, "SATA_PDETECT1"),
PINCTRL_PIN(186, "SATA0_SDOUT"),
PINCTRL_PIN(187, "SATA1_SDOUT"),
PINCTRL_PIN(188, "SATA2_LED_N"),
PINCTRL_PIN(189, "SATA_PDETECT2"),
PINCTRL_PIN(190, "SATA2_SDOUT"),
PINCTRL_PIN(182, "PECI_SMB_DATA"),
PINCTRL_PIN(183, "SATA0_LED_N"),
PINCTRL_PIN(184, "SATA1_LED_N"),
PINCTRL_PIN(185, "SATA_PDETECT0"),
PINCTRL_PIN(186, "SATA_PDETECT1"),
PINCTRL_PIN(187, "SATA0_SDOUT"),
PINCTRL_PIN(188, "SATA1_SDOUT"),
PINCTRL_PIN(189, "SATA2_LED_N"),
PINCTRL_PIN(190, "SATA_PDETECT2"),
PINCTRL_PIN(191, "SATA2_SDOUT"),
/* EAST3 */
PINCTRL_PIN(191, "ESPI_IO0"),
PINCTRL_PIN(192, "ESPI_IO1"),
PINCTRL_PIN(193, "ESPI_IO2"),
PINCTRL_PIN(194, "ESPI_IO3"),
PINCTRL_PIN(195, "ESPI_CLK"),
PINCTRL_PIN(196, "ESPI_RST_N"),
PINCTRL_PIN(197, "ESPI_CS0_N"),
PINCTRL_PIN(198, "ESPI_ALRT0_N"),
PINCTRL_PIN(199, "ESPI_CS1_N"),
PINCTRL_PIN(200, "ESPI_ALRT1_N"),
PINCTRL_PIN(201, "ESPI_CLK_LOOPBK"),
PINCTRL_PIN(192, "ESPI_IO0"),
PINCTRL_PIN(193, "ESPI_IO1"),
PINCTRL_PIN(194, "ESPI_IO2"),
PINCTRL_PIN(195, "ESPI_IO3"),
PINCTRL_PIN(196, "ESPI_CLK"),
PINCTRL_PIN(197, "ESPI_RST_N"),
PINCTRL_PIN(198, "ESPI_CS0_N"),
PINCTRL_PIN(199, "ESPI_ALRT0_N"),
PINCTRL_PIN(200, "ESPI_CS1_N"),
PINCTRL_PIN(201, "ESPI_ALRT1_N"),
PINCTRL_PIN(202, "ESPI_CLK_LOOPBK"),
/* EAST0 */
PINCTRL_PIN(202, "SPI_CS0_N"),
PINCTRL_PIN(203, "SPI_CS1_N"),
PINCTRL_PIN(204, "SPI_MOSI_IO0"),
PINCTRL_PIN(205, "SPI_MISO_IO1"),
PINCTRL_PIN(206, "SPI_IO2"),
PINCTRL_PIN(207, "SPI_IO3"),
PINCTRL_PIN(208, "SPI_CLK"),
PINCTRL_PIN(209, "SPI_CLK_LOOPBK"),
PINCTRL_PIN(210, "SUSPWRDNACK"),
PINCTRL_PIN(211, "PMU_SUSCLK"),
PINCTRL_PIN(212, "ADR_COMPLETE"),
PINCTRL_PIN(213, "ADR_TRIGGER_N"),
PINCTRL_PIN(214, "PMU_SLP_S45_N"),
PINCTRL_PIN(215, "PMU_SLP_S3_N"),
PINCTRL_PIN(216, "PMU_WAKE_N"),
PINCTRL_PIN(217, "PMU_PWRBTN_N"),
PINCTRL_PIN(218, "PMU_RESETBUTTON_N"),
PINCTRL_PIN(219, "PMU_PLTRST_N"),
PINCTRL_PIN(220, "SUS_STAT_N"),
PINCTRL_PIN(221, "PMU_I2C_CLK"),
PINCTRL_PIN(222, "PMU_I2C_DATA"),
PINCTRL_PIN(223, "PECI_SMB_CLK"),
PINCTRL_PIN(224, "PECI_SMB_DATA"),
PINCTRL_PIN(203, "SPI_CS0_N"),
PINCTRL_PIN(204, "SPI_CS1_N"),
PINCTRL_PIN(205, "SPI_MOSI_IO0"),
PINCTRL_PIN(206, "SPI_MISO_IO1"),
PINCTRL_PIN(207, "SPI_IO2"),
PINCTRL_PIN(208, "SPI_IO3"),
PINCTRL_PIN(209, "SPI_CLK"),
PINCTRL_PIN(210, "SPI_CLK_LOOPBK"),
PINCTRL_PIN(211, "SUSPWRDNACK"),
PINCTRL_PIN(212, "PMU_SUSCLK"),
PINCTRL_PIN(213, "ADR_COMPLETE"),
PINCTRL_PIN(214, "ADR_TRIGGER_N"),
PINCTRL_PIN(215, "PMU_SLP_S45_N"),
PINCTRL_PIN(216, "PMU_SLP_S3_N"),
PINCTRL_PIN(217, "PMU_WAKE_N"),
PINCTRL_PIN(218, "PMU_PWRBTN_N"),
PINCTRL_PIN(219, "PMU_RESETBUTTON_N"),
PINCTRL_PIN(220, "PMU_PLTRST_N"),
PINCTRL_PIN(221, "SUS_STAT_N"),
PINCTRL_PIN(222, "PMU_I2C_CLK"),
PINCTRL_PIN(223, "PMU_I2C_DATA"),
PINCTRL_PIN(224, "PECI_SMB_CLK"),
PINCTRL_PIN(225, "PECI_SMB_ALRT_N"),
/* EMMC */
PINCTRL_PIN(226, "EMMC_CMD"),
@ -315,9 +312,9 @@ static const struct intel_padgroup cdf_community0_gpps[] = {
};
static const struct intel_padgroup cdf_community1_gpps[] = {
CDF_GPP(0, 168, 190), /* EAST2 */
CDF_GPP(1, 191, 201), /* EAST3 */
CDF_GPP(2, 202, 225), /* EAST0 */
CDF_GPP(0, 168, 191), /* EAST2 */
CDF_GPP(1, 192, 202), /* EAST3 */
CDF_GPP(2, 203, 225), /* EAST0 */
CDF_GPP(3, 226, 236), /* EMMC */
};

5
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Cherryview/Braswell pinctrl driver
*
@ -7,10 +8,6 @@
* This driver is based on the original Cherryview GPIO driver by
* Ning Li <ning.li@intel.com>
* Alan Cox <alan@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/dmi.h>

5
drivers/pinctrl/intel/pinctrl-denverton.c
View File

@ -1,12 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Denverton SoC pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>

5
drivers/pinctrl/intel/pinctrl-geminilake.c
View File

@ -1,12 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Gemini Lake SoC pinctrl/GPIO driver
*
* Copyright (C) 2017 Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>

436
drivers/pinctrl/intel/pinctrl-icelake.c Normal file
View File

@ -0,0 +1,436 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Ice Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2018, Intel Corporation
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Mika Westerberg <mika.westerberg@linux.intel.com>
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define ICL_PAD_OWN 0x020
#define ICL_PADCFGLOCK 0x080
#define ICL_HOSTSW_OWN 0x0b0
#define ICL_GPI_IE 0x110
#define ICL_GPP(r, s, e, g) \
{ \
.reg_num = (r), \
.base = (s), \
.size = ((e) - (s) + 1), \
.gpio_base = (g), \
}
#define ICL_NO_GPIO -1
#define ICL_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = ICL_PAD_OWN, \
.padcfglock_offset = ICL_PADCFGLOCK, \
.hostown_offset = ICL_HOSTSW_OWN, \
.ie_offset = ICL_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
/* Ice Lake-LP */
static const struct pinctrl_pin_desc icllp_pins[] = {
/* GPP_G */
PINCTRL_PIN(0, "SD3_CMD"),
PINCTRL_PIN(1, "SD3_D0"),
PINCTRL_PIN(2, "SD3_D1"),
PINCTRL_PIN(3, "SD3_D2"),
PINCTRL_PIN(4, "SD3_D3"),
PINCTRL_PIN(5, "SD3_CDB"),
PINCTRL_PIN(6, "SD3_CLK"),
PINCTRL_PIN(7, "SD3_WP"),
/* GPP_B */
PINCTRL_PIN(8, "CORE_VID_0"),
PINCTRL_PIN(9, "CORE_VID_1"),
PINCTRL_PIN(10, "VRALERTB"),
PINCTRL_PIN(11, "CPU_GP_2"),
PINCTRL_PIN(12, "CPU_GP_3"),
PINCTRL_PIN(13, "ISH_I2C0_SDA"),
PINCTRL_PIN(14, "ISH_I2C0_SCL"),
PINCTRL_PIN(15, "ISH_I2C1_SDA"),
PINCTRL_PIN(16, "ISH_I2C1_SCL"),
PINCTRL_PIN(17, "I2C5_SDA"),
PINCTRL_PIN(18, "I2C5_SCL"),
PINCTRL_PIN(19, "PMCALERTB"),
PINCTRL_PIN(20, "SLP_S0B"),
PINCTRL_PIN(21, "PLTRSTB"),
PINCTRL_PIN(22, "SPKR"),
PINCTRL_PIN(23, "GSPI0_CS0B"),
PINCTRL_PIN(24, "GSPI0_CLK"),
PINCTRL_PIN(25, "GSPI0_MISO"),
PINCTRL_PIN(26, "GSPI0_MOSI"),
PINCTRL_PIN(27, "GSPI1_CS0B"),
PINCTRL_PIN(28, "GSPI1_CLK"),
PINCTRL_PIN(29, "GSPI1_MISO"),
PINCTRL_PIN(30, "GSPI1_MOSI"),
PINCTRL_PIN(31, "SML1ALERTB"),
PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
/* GPP_A */
PINCTRL_PIN(34, "ESPI_IO_0"),
PINCTRL_PIN(35, "ESPI_IO_1"),
PINCTRL_PIN(36, "ESPI_IO_2"),
PINCTRL_PIN(37, "ESPI_IO_3"),
PINCTRL_PIN(38, "ESPI_CSB"),
PINCTRL_PIN(39, "ESPI_CLK"),
PINCTRL_PIN(40, "ESPI_RESETB"),
PINCTRL_PIN(41, "I2S2_SCLK"),
PINCTRL_PIN(42, "I2S2_SFRM"),
PINCTRL_PIN(43, "I2S2_TXD"),
PINCTRL_PIN(44, "I2S2_RXD"),
PINCTRL_PIN(45, "SATA_DEVSLP_2"),
PINCTRL_PIN(46, "SATAXPCIE_1"),
PINCTRL_PIN(47, "SATAXPCIE_2"),
PINCTRL_PIN(48, "USB2_OCB_1"),
PINCTRL_PIN(49, "USB2_OCB_2"),
PINCTRL_PIN(50, "USB2_OCB_3"),
PINCTRL_PIN(51, "DDSP_HPD_C"),
PINCTRL_PIN(52, "DDSP_HPD_B"),
PINCTRL_PIN(53, "DDSP_HPD_1"),
PINCTRL_PIN(54, "DDSP_HPD_2"),
PINCTRL_PIN(55, "I2S5_TXD"),
PINCTRL_PIN(56, "I2S5_RXD"),
PINCTRL_PIN(57, "I2S1_SCLK"),
PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
/* GPP_H */
PINCTRL_PIN(59, "SD_1P8_SEL"),
PINCTRL_PIN(60, "SD_PWR_EN_B"),
PINCTRL_PIN(61, "GPPC_H_2"),
PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
PINCTRL_PIN(63, "I2C2_SDA"),
PINCTRL_PIN(64, "I2C2_SCL"),
PINCTRL_PIN(65, "I2C3_SDA"),
PINCTRL_PIN(66, "I2C3_SCL"),
PINCTRL_PIN(67, "I2C4_SDA"),
PINCTRL_PIN(68, "I2C4_SCL"),
PINCTRL_PIN(69, "SRCCLKREQB_4"),
PINCTRL_PIN(70, "SRCCLKREQB_5"),
PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
PINCTRL_PIN(75, "DDPB_CTRLCLK"),
PINCTRL_PIN(76, "DDPB_CTRLDATA"),
PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
PINCTRL_PIN(78, "TIME_SYNC_0"),
PINCTRL_PIN(79, "IMGCLKOUT_1"),
PINCTRL_PIN(80, "IMGCLKOUT_2"),
PINCTRL_PIN(81, "IMGCLKOUT_3"),
PINCTRL_PIN(82, "IMGCLKOUT_4"),
/* GPP_D */
PINCTRL_PIN(83, "ISH_GP_0"),
PINCTRL_PIN(84, "ISH_GP_1"),
PINCTRL_PIN(85, "ISH_GP_2"),
PINCTRL_PIN(86, "ISH_GP_3"),
PINCTRL_PIN(87, "IMGCLKOUT_0"),
PINCTRL_PIN(88, "SRCCLKREQB_0"),
PINCTRL_PIN(89, "SRCCLKREQB_1"),
PINCTRL_PIN(90, "SRCCLKREQB_2"),
PINCTRL_PIN(91, "SRCCLKREQB_3"),
PINCTRL_PIN(92, "ISH_SPI_CSB"),
PINCTRL_PIN(93, "ISH_SPI_CLK"),
PINCTRL_PIN(94, "ISH_SPI_MISO"),
PINCTRL_PIN(95, "ISH_SPI_MOSI"),
PINCTRL_PIN(96, "ISH_UART0_RXD"),
PINCTRL_PIN(97, "ISH_UART0_TXD"),
PINCTRL_PIN(98, "ISH_UART0_RTSB"),
PINCTRL_PIN(99, "ISH_UART0_CTSB"),
PINCTRL_PIN(100, "ISH_GP_4"),
PINCTRL_PIN(101, "ISH_GP_5"),
PINCTRL_PIN(102, "I2S_MCLK"),
PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
/* GPP_F */
PINCTRL_PIN(104, "CNV_BRI_DT"),
PINCTRL_PIN(105, "CNV_BRI_RSP"),
PINCTRL_PIN(106, "CNV_RGI_DT"),
PINCTRL_PIN(107, "CNV_RGI_RSP"),
PINCTRL_PIN(108, "CNV_RF_RESET_B"),
PINCTRL_PIN(109, "EMMC_HIP_MON"),
PINCTRL_PIN(110, "CNV_PA_BLANKING"),
PINCTRL_PIN(111, "EMMC_CMD"),
PINCTRL_PIN(112, "EMMC_DATA0"),
PINCTRL_PIN(113, "EMMC_DATA1"),
PINCTRL_PIN(114, "EMMC_DATA2"),
PINCTRL_PIN(115, "EMMC_DATA3"),
PINCTRL_PIN(116, "EMMC_DATA4"),
PINCTRL_PIN(117, "EMMC_DATA5"),
PINCTRL_PIN(118, "EMMC_DATA6"),
PINCTRL_PIN(119, "EMMC_DATA7"),
PINCTRL_PIN(120, "EMMC_RCLK"),
PINCTRL_PIN(121, "EMMC_CLK"),
PINCTRL_PIN(122, "EMMC_RESETB"),
PINCTRL_PIN(123, "A4WP_PRESENT"),
/* vGPIO */
PINCTRL_PIN(124, "CNV_BTEN"),
PINCTRL_PIN(125, "CNV_WCEN"),
PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(136, "vUART0_TXD"),
PINCTRL_PIN(137, "vUART0_RXD"),
PINCTRL_PIN(138, "vUART0_CTS_B"),
PINCTRL_PIN(139, "vUART0_RTS_B"),
PINCTRL_PIN(140, "vISH_UART0_TXD"),
PINCTRL_PIN(141, "vISH_UART0_RXD"),
PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(148, "vI2S2_SCLK"),
PINCTRL_PIN(149, "vI2S2_SFRM"),
PINCTRL_PIN(150, "vI2S2_TXD"),
PINCTRL_PIN(151, "vI2S2_RXD"),
PINCTRL_PIN(152, "vSD3_CD_B"),
/* GPP_C */
PINCTRL_PIN(153, "SMBCLK"),
PINCTRL_PIN(154, "SMBDATA"),
PINCTRL_PIN(155, "SMBALERTB"),
PINCTRL_PIN(156, "SML0CLK"),
PINCTRL_PIN(157, "SML0DATA"),
PINCTRL_PIN(158, "SML0ALERTB"),
PINCTRL_PIN(159, "SML1CLK"),
PINCTRL_PIN(160, "SML1DATA"),
PINCTRL_PIN(161, "UART0_RXD"),
PINCTRL_PIN(162, "UART0_TXD"),
PINCTRL_PIN(163, "UART0_RTSB"),
PINCTRL_PIN(164, "UART0_CTSB"),
PINCTRL_PIN(165, "UART1_RXD"),
PINCTRL_PIN(166, "UART1_TXD"),
PINCTRL_PIN(167, "UART1_RTSB"),
PINCTRL_PIN(168, "UART1_CTSB"),
PINCTRL_PIN(169, "I2C0_SDA"),
PINCTRL_PIN(170, "I2C0_SCL"),
PINCTRL_PIN(171, "I2C1_SDA"),
PINCTRL_PIN(172, "I2C1_SCL"),
PINCTRL_PIN(173, "UART2_RXD"),
PINCTRL_PIN(174, "UART2_TXD"),
PINCTRL_PIN(175, "UART2_RTSB"),
PINCTRL_PIN(176, "UART2_CTSB"),
/* HVCMOS */
PINCTRL_PIN(177, "L_BKLTEN"),
PINCTRL_PIN(178, "L_BKLTCTL"),
PINCTRL_PIN(179, "L_VDDEN"),
PINCTRL_PIN(180, "SYS_PWROK"),
PINCTRL_PIN(181, "SYS_RESETB"),
PINCTRL_PIN(182, "MLK_RSTB"),
/* GPP_E */
PINCTRL_PIN(183, "SATAXPCIE_0"),
PINCTRL_PIN(184, "SPI1_IO_2"),
PINCTRL_PIN(185, "SPI1_IO_3"),
PINCTRL_PIN(186, "CPU_GP_0"),
PINCTRL_PIN(187, "SATA_DEVSLP_0"),
PINCTRL_PIN(188, "SATA_DEVSLP_1"),
PINCTRL_PIN(189, "GPPC_E_6"),
PINCTRL_PIN(190, "CPU_GP_1"),
PINCTRL_PIN(191, "SATA_LEDB"),
PINCTRL_PIN(192, "USB2_OCB_0"),
PINCTRL_PIN(193, "SPI1_CSB"),
PINCTRL_PIN(194, "SPI1_CLK"),
PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(197, "DDSP_HPD_A"),
PINCTRL_PIN(198, "ISH_GP_6"),
PINCTRL_PIN(199, "ISH_GP_7"),
PINCTRL_PIN(200, "DISP_MISC_4"),
PINCTRL_PIN(201, "DDP1_CTRLCLK"),
PINCTRL_PIN(202, "DDP1_CTRLDATA"),
PINCTRL_PIN(203, "DDP2_CTRLCLK"),
PINCTRL_PIN(204, "DDP2_CTRLDATA"),
PINCTRL_PIN(205, "DDPA_CTRLCLK"),
PINCTRL_PIN(206, "DDPA_CTRLDATA"),
/* JTAG */
PINCTRL_PIN(207, "JTAG_TDO"),
PINCTRL_PIN(208, "JTAGX"),
PINCTRL_PIN(209, "PRDYB"),
PINCTRL_PIN(210, "PREQB"),
PINCTRL_PIN(211, "CPU_TRSTB"),
PINCTRL_PIN(212, "JTAG_TDI"),
PINCTRL_PIN(213, "JTAG_TMS"),
PINCTRL_PIN(214, "JTAG_TCK"),
PINCTRL_PIN(215, "ITP_PMODE"),
/* GPP_R */
PINCTRL_PIN(216, "HDA_BCLK"),
PINCTRL_PIN(217, "HDA_SYNC"),
PINCTRL_PIN(218, "HDA_SDO"),
PINCTRL_PIN(219, "HDA_SDI_0"),
PINCTRL_PIN(220, "HDA_RSTB"),
PINCTRL_PIN(221, "HDA_SDI_1"),
PINCTRL_PIN(222, "I2S1_TXD"),
PINCTRL_PIN(223, "I2S1_RXD"),
/* GPP_S */
PINCTRL_PIN(224, "SNDW1_CLK"),
PINCTRL_PIN(225, "SNDW1_DATA"),
PINCTRL_PIN(226, "SNDW2_CLK"),
PINCTRL_PIN(227, "SNDW2_DATA"),
PINCTRL_PIN(228, "SNDW3_CLK"),
PINCTRL_PIN(229, "SNDW3_DATA"),
PINCTRL_PIN(230, "SNDW4_CLK"),
PINCTRL_PIN(231, "SNDW4_DATA"),
/* SPI */
PINCTRL_PIN(232, "SPI0_IO_2"),
PINCTRL_PIN(233, "SPI0_IO_3"),
PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
PINCTRL_PIN(236, "SPI0_TPM_CSB"),
PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(239, "SPI0_CLK"),
PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
};
static const struct intel_padgroup icllp_community0_gpps[] = {
ICL_GPP(0, 0, 7, 0), /* GPP_G */
ICL_GPP(1, 8, 33, 32), /* GPP_B */
ICL_GPP(2, 34, 58, 64), /* GPP_A */
};
static const struct intel_padgroup icllp_community1_gpps[] = {
ICL_GPP(0, 59, 82, 96), /* GPP_H */
ICL_GPP(1, 83, 103, 128), /* GPP_D */
ICL_GPP(2, 104, 123, 160), /* GPP_F */
ICL_GPP(3, 124, 152, 192), /* vGPIO */
};
static const struct intel_padgroup icllp_community4_gpps[] = {
ICL_GPP(0, 153, 176, 224), /* GPP_C */
ICL_GPP(1, 177, 182, ICL_NO_GPIO), /* HVCMOS */
ICL_GPP(2, 183, 206, 256), /* GPP_E */
ICL_GPP(3, 207, 215, ICL_NO_GPIO), /* JTAG */
};
static const struct intel_padgroup icllp_community5_gpps[] = {
ICL_GPP(0, 216, 223, 288), /* GPP_R */
ICL_GPP(1, 224, 231, 320), /* GPP_S */
ICL_GPP(2, 232, 240, ICL_NO_GPIO), /* SPI */
};
static const struct intel_community icllp_communities[] = {
ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
};
static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
static const struct intel_pingroup icllp_groups[] = {
PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
};
static const char * const icllp_spi0_groups[] = { "spi0_grp" };
static const char * const icllp_spi1_groups[] = { "spi1_grp" };
static const char * const icllp_spi2_groups[] = { "spi2_grp" };
static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
static const char * const icllp_uart0_groups[] = { "uart0_grp" };
static const char * const icllp_uart1_groups[] = { "uart1_grp" };
static const char * const icllp_uart2_groups[] = { "uart2_grp" };
static const struct intel_function icllp_functions[] = {
FUNCTION("spi0", icllp_spi0_groups),
FUNCTION("spi1", icllp_spi1_groups),
FUNCTION("spi2", icllp_spi2_groups),
FUNCTION("i2c0", icllp_i2c0_groups),
FUNCTION("i2c1", icllp_i2c1_groups),
FUNCTION("i2c2", icllp_i2c2_groups),
FUNCTION("i2c3", icllp_i2c3_groups),
FUNCTION("i2c4", icllp_i2c4_groups),
FUNCTION("uart0", icllp_uart0_groups),
FUNCTION("uart1", icllp_uart1_groups),
FUNCTION("uart2", icllp_uart2_groups),
};
static const struct intel_pinctrl_soc_data icllp_soc_data = {
.pins = icllp_pins,
.npins = ARRAY_SIZE(icllp_pins),
.groups = icllp_groups,
.ngroups = ARRAY_SIZE(icllp_groups),
.functions = icllp_functions,
.nfunctions = ARRAY_SIZE(icllp_functions),
.communities = icllp_communities,
.ncommunities = ARRAY_SIZE(icllp_communities),
};
static int icl_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &icllp_soc_data);
}
static const struct dev_pm_ops icl_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
{ "INT3455" },
{ },
};
MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
static struct platform_driver icl_pinctrl_driver = {
.probe = icl_pinctrl_probe,
.driver = {
.name = "icelake-pinctrl",
.acpi_match_table = icl_pinctrl_acpi_match,
.pm = &icl_pinctrl_pm_ops,
},
};
module_platform_driver(icl_pinctrl_driver);
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");

37
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -1,13 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel pinctrl/GPIO core driver.
*
* Copyright (C) 2015, Intel Corporation
* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
* Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
@ -875,6 +872,36 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
return -EINVAL;
}
static int intel_gpio_irq_reqres(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int pin;
int ret;
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
if (pin >= 0) {
ret = gpiochip_lock_as_irq(gc, pin);
if (ret) {
dev_err(pctrl->dev, "unable to lock HW IRQ %d for IRQ\n",
pin);
return ret;
}
}
return 0;
}
static void intel_gpio_irq_relres(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
int pin;
pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
if (pin >= 0)
gpiochip_unlock_as_irq(gc, pin);
}
static void intel_gpio_irq_ack(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@ -1090,6 +1117,8 @@ static irqreturn_t intel_gpio_irq(int irq, void *data)
static struct irq_chip intel_gpio_irqchip = {
.name = "intel-gpio",
.irq_request_resources = intel_gpio_irq_reqres,
.irq_release_resources = intel_gpio_irq_relres,
.irq_enable = intel_gpio_irq_enable,
.irq_ack = intel_gpio_irq_ack,
.irq_mask = intel_gpio_irq_mask,

5
drivers/pinctrl/intel/pinctrl-intel.h
View File

@ -1,13 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Core pinctrl/GPIO driver for Intel GPIO controllers
*
* Copyright (C) 2015, Intel Corporation
* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
* Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef PINCTRL_INTEL_H

5
drivers/pinctrl/intel/pinctrl-lewisburg.c
View File

@ -1,12 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Lewisburg pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>

5
drivers/pinctrl/intel/pinctrl-merrifield.c
View File

@ -1,12 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Merrifield SoC pinctrl driver
*
* Copyright (C) 2016, Intel Corporation
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/bitops.h>

5
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -1,13 +1,10 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Intel Sunrisepoint PCH pinctrl/GPIO driver
*
* Copyright (C) 2015, Intel Corporation
* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
* Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>

1
drivers/pinctrl/mediatek/mtk-eint.c
View File

@ -13,6 +13,7 @@
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>

5
drivers/pinctrl/mediatek/pinctrl-mt7622.c
View File

@ -1263,6 +1263,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
MTK_DISABLE);
if (err)
goto err;
/* else: fall through */
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_SLEW_RATE:
reg = (param == PIN_CONFIG_SLEW_RATE) ?
@ -1537,7 +1538,7 @@ static int mtk_build_groups(struct mtk_pinctrl *hw)
err = pinctrl_generic_add_group(hw->pctrl, group->name,
group->pins, group->num_pins,
group->data);
if (err) {
if (err < 0) {
dev_err(hw->dev, "Failed to register group %s\n",
group->name);
return err;
@ -1558,7 +1559,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw)
func->group_names,
func->num_group_names,
func->data);
if (err) {
if (err < 0) {
dev_err(hw->dev, "Failed to register function %s\n",
func->name);
return err;

9
drivers/pinctrl/meson/pinctrl-meson-axg.c
View File

@ -672,6 +672,9 @@ static const unsigned int jtag_ao_tdo_pins[] = {GPIOAO_4};
static const unsigned int jtag_ao_clk_pins[] = {GPIOAO_5};
static const unsigned int jtag_ao_tms_pins[] = {GPIOAO_7};
/* gen_clk */
static const unsigned int gen_clk_ee_pins[] = {GPIOAO_13};
static struct meson_pmx_group meson_axg_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0),
GPIO_GROUP(GPIOAO_1),
@ -718,6 +721,7 @@ static struct meson_pmx_group meson_axg_aobus_groups[] = {
GROUP(jtag_ao_tdo, 4),
GROUP(jtag_ao_clk, 4),
GROUP(jtag_ao_tms, 4),
GROUP(gen_clk_ee, 4),
};
static const char * const gpio_periphs_groups[] = {
@ -947,6 +951,10 @@ static const char * const tdmb_groups[] = {
"tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3",
};
static const char * const gen_clk_ee_groups[] = {
"gen_clk_ee",
};
static struct meson_pmx_func meson_axg_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
@ -992,6 +1000,7 @@ static struct meson_pmx_func meson_axg_aobus_functions[] = {
FUNCTION(pwm_ao_c),
FUNCTION(pwm_ao_d),
FUNCTION(jtag_ao),
FUNCTION(gen_clk_ee),
};
static struct meson_bank meson_axg_periphs_banks[] = {

8
drivers/pinctrl/meson/pinctrl-meson-gxbb.c
View File

@ -243,6 +243,8 @@ static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 };
static const unsigned int spdif_out_y_pins[] = { GPIOY_12 };
static const unsigned int gen_clk_out_pins[] = { GPIOY_15 };
static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
MESON_PIN(GPIOAO_0),
MESON_PIN(GPIOAO_1),
@ -453,6 +455,7 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GROUP(i2s_out_ch45_y, 1, 6),
GROUP(i2s_out_ch67_y, 1, 7),
GROUP(spdif_out_y, 1, 9),
GROUP(gen_clk_out, 6, 15),
/* Bank Z */
GROUP(eth_mdio, 6, 1),
@ -706,6 +709,10 @@ static const char * const spdif_out_groups[] = {
"spdif_out_y",
};
static const char * const gen_clk_out_groups[] = {
"gen_clk_out",
};
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
@ -790,6 +797,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(hdmi_i2c),
FUNCTION(i2s_out),
FUNCTION(spdif_out),
FUNCTION(gen_clk_out),
};
static struct meson_pmx_func meson_gxbb_aobus_functions[] = {

118
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View File

@ -80,6 +80,18 @@ struct armada_37xx_pmx_func {
unsigned int ngroups;
};
struct armada_37xx_pm_state {
u32 out_en_l;
u32 out_en_h;
u32 out_val_l;
u32 out_val_h;
u32 irq_en_l;
u32 irq_en_h;
u32 irq_pol_l;
u32 irq_pol_h;
u32 selection;
};
struct armada_37xx_pinctrl {
struct regmap *regmap;
void __iomem *base;
@ -94,6 +106,7 @@ struct armada_37xx_pinctrl {
unsigned int ngroups;
struct armada_37xx_pmx_func *funcs;
unsigned int nfuncs;
struct armada_37xx_pm_state pm;
};
#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
@ -996,6 +1009,110 @@ static int armada_37xx_pinctrl_register(struct platform_device *pdev,
return 0;
}
#if defined(CONFIG_PM)
static int armada_3700_pinctrl_suspend(struct device *dev)
{
struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
/* Save GPIO state */
regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
&info->pm.out_val_h);
info->pm.irq_en_l = readl(info->base + IRQ_EN);
info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
info->pm.irq_pol_l = readl(info->base + IRQ_POL);
info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
/* Save pinctrl state */
regmap_read(info->regmap, SELECTION, &info->pm.selection);
return 0;
}
static int armada_3700_pinctrl_resume(struct device *dev)
{
struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
struct gpio_chip *gc;
struct irq_domain *d;
int i;
/* Restore GPIO state */
regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
info->pm.out_en_h);
regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
info->pm.out_val_h);
/*
* Input levels may change during suspend, which is not monitored at
* that time. GPIOs used for both-edge IRQs may not be synchronized
* anymore with their polarities (rising/falling edge) and must be
* re-configured manually.
*/
gc = &info->gpio_chip;
d = gc->irq.domain;
for (i = 0; i < gc->ngpio; i++) {
u32 irq_bit = BIT(i % GPIO_PER_REG);
u32 mask, *irq_pol, input_reg, virq, type, level;
if (i < GPIO_PER_REG) {
mask = info->pm.irq_en_l;
irq_pol = &info->pm.irq_pol_l;
input_reg = INPUT_VAL;
} else {
mask = info->pm.irq_en_h;
irq_pol = &info->pm.irq_pol_h;
input_reg = INPUT_VAL + sizeof(u32);
}
if (!(mask & irq_bit))
continue;
virq = irq_find_mapping(d, i);
type = irq_get_trigger_type(virq);
/*
* Synchronize level and polarity for both-edge irqs:
* - a high input level expects a falling edge,
* - a low input level exepects a rising edge.
*/
if ((type & IRQ_TYPE_SENSE_MASK) ==
IRQ_TYPE_EDGE_BOTH) {
regmap_read(info->regmap, input_reg, &level);
if ((*irq_pol ^ level) & irq_bit)
*irq_pol ^= irq_bit;
}
}
writel(info->pm.irq_en_l, info->base + IRQ_EN);
writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
writel(info->pm.irq_pol_l, info->base + IRQ_POL);
writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
/* Restore pinctrl state */
regmap_write(info->regmap, SELECTION, info->pm.selection);
return 0;
}
/*
* Since pinctrl is an infrastructure module, its resume should be issued prior
* to other IO drivers.
*/
static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
.suspend_late = armada_3700_pinctrl_suspend,
.resume_early = armada_3700_pinctrl_resume,
};
#define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
#else
#define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
#endif /* CONFIG_PM */
static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
{
.compatible = "marvell,armada3710-sb-pinctrl",
@ -1049,6 +1166,7 @@ static struct platform_driver armada_37xx_pinctrl_driver = {
.driver = {
.name = "armada-37xx-pinctrl",
.of_match_table = armada_37xx_pinctrl_of_match,
.pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
},
};

11
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -101,15 +101,16 @@ static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
reg += offset / 8;
ret = abx500_get_register_interruptible(pct->dev,
AB8500_MISC, reg, &val);
*bit = !!(val & BIT(pos));
if (ret < 0)
if (ret < 0) {
dev_err(pct->dev,
"%s read reg =%x, offset=%x failed (%d)\n",
__func__, reg, offset, ret);
return ret;
}
*bit = !!(val & BIT(pos));
return 0;
}
static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,

17
drivers/pinctrl/pinctrl-amd.c
View File

@ -247,16 +247,16 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
ACTIVE_LEVEL_MASK;
interrupt_enable = "interrupt is enabled|";
if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
!(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
active_level = "Active low|";
else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&
!(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
if (level == ACTIVE_LEVEL_HIGH)
active_level = "Active high|";
else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))
else if (level == ACTIVE_LEVEL_LOW)
active_level = "Active low|";
else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
level == ACTIVE_LEVEL_BOTH)
active_level = "Active on both|";
else
active_level = "Unknown Active level|";
@ -552,7 +552,8 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
/* Each status bit covers four pins */
for (i = 0; i < 4; i++) {
regval = readl(regs + i);
if (!(regval & PIN_IRQ_PENDING))
if (!(regval & PIN_IRQ_PENDING) ||
!(regval & BIT(INTERRUPT_MASK_OFF)))
continue;
irq = irq_find_mapping(gc->irq.domain, irqnr + i);
generic_handle_irq(irq);

4
drivers/pinctrl/pinctrl-amd.h
View File

@ -54,6 +54,10 @@
#define ACTIVE_LEVEL_MASK 0x3UL
#define DRV_STRENGTH_SEL_MASK 0x3UL
#define ACTIVE_LEVEL_HIGH 0x0UL
#define ACTIVE_LEVEL_LOW 0x1UL
#define ACTIVE_LEVEL_BOTH 0x2UL
#define DB_TYPE_NO_DEBOUNCE 0x0UL
#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL

46
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <dt-bindings/pinctrl/at91.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
/* FIXME: needed for gpio_to_irq(), get rid of this */
@ -49,6 +50,8 @@
#define ATMEL_PIO_IFSCEN_MASK BIT(13)
#define ATMEL_PIO_OPD_MASK BIT(14)
#define ATMEL_PIO_SCHMITT_MASK BIT(15)
#define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
#define ATMEL_PIO_DRVSTR_OFFSET 16
#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
@ -75,6 +78,9 @@
#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
/* Custom pinconf parameters */
#define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
struct atmel_pioctrl_data {
unsigned nbanks;
};
@ -139,6 +145,10 @@ static const char * const atmel_functions[] = {
"GPIO", "A", "B", "C", "D", "E", "F", "G"
};
static const struct pinconf_generic_params atmel_custom_bindings[] = {
{"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
};
/* --- GPIO --- */
static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
unsigned int bank, unsigned int reg)
@ -692,6 +702,11 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
return -EINVAL;
arg = 1;
break;
case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
if (!(res & ATMEL_PIO_DRVSTR_MASK))
return -EINVAL;
arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
break;
default:
return -ENOTSUPP;
}
@ -777,6 +792,18 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
ATMEL_PIO_SODR);
}
break;
case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
switch (arg) {
case ATMEL_PIO_DRVSTR_LO:
case ATMEL_PIO_DRVSTR_ME:
case ATMEL_PIO_DRVSTR_HI:
conf &= (~ATMEL_PIO_DRVSTR_MASK);
conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
break;
default:
dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
}
break;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter: %u\n",
@ -816,6 +843,19 @@ static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, "%s ", "open-drain");
if (conf & ATMEL_PIO_SCHMITT_MASK)
seq_printf(s, "%s ", "schmitt");
if (conf & ATMEL_PIO_DRVSTR_MASK) {
switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
case ATMEL_PIO_DRVSTR_ME:
seq_printf(s, "%s ", "medium-drive");
break;
case ATMEL_PIO_DRVSTR_HI:
seq_printf(s, "%s ", "high-drive");
break;
/* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
default:
seq_printf(s, "%s ", "low-drive");
}
}
}
static const struct pinconf_ops atmel_confops = {
@ -931,10 +971,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "unable to get atmel pinctrl resource\n");
return -EINVAL;
}
atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
if (IS_ERR(atmel_pioctrl->reg_base))
return -EINVAL;
@ -958,6 +994,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev)
return -ENOMEM;
atmel_pinctrl_desc.pins = pin_desc;
atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
/* One pin is one group since a pin can achieve all functions. */
group_names = devm_kcalloc(dev,

26
drivers/pinctrl/pinctrl-axp209.c
View File

@ -316,7 +316,7 @@ static const struct pinctrl_ops axp20x_pctrl_ops = {
.get_group_pins = axp20x_group_pins,
};
static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
unsigned int mask_len,
struct axp20x_pinctrl_function *func,
const struct pinctrl_pin_desc *pins)
@ -331,18 +331,22 @@ static void axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
func->groups = devm_kcalloc(dev,
ngroups, sizeof(const char *),
GFP_KERNEL);
if (!func->groups)
return -ENOMEM;
group = func->groups;
for_each_set_bit(bit, &mask_cpy, mask_len) {
*group = pins[bit].name;
group++;
}
}
return 0;
}
static void axp20x_build_funcs_groups(struct platform_device *pdev)
static int axp20x_build_funcs_groups(struct platform_device *pdev)
{
struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
int i, pin, npins = pctl->desc->npins;
int i, ret, pin, npins = pctl->desc->npins;
pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
@ -366,13 +370,19 @@ static void axp20x_build_funcs_groups(struct platform_device *pdev)
pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
}
axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
npins, &pctl->funcs[AXP20X_FUNC_LDO],
pctl->desc->pins);
if (ret)
return ret;
axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
npins, &pctl->funcs[AXP20X_FUNC_ADC],
pctl->desc->pins);
if (ret)
return ret;
return 0;
}
static const struct of_device_id axp20x_pctl_match[] = {
@ -424,7 +434,11 @@ static int axp20x_pctl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pctl);
axp20x_build_funcs_groups(pdev);
ret = axp20x_build_funcs_groups(pdev);
if (ret) {
dev_err(&pdev->dev, "failed to build groups\n");
return ret;
}
pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
if (!pctrl_desc)

2
drivers/pinctrl/pinctrl-gemini.c
View File

@ -1696,6 +1696,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
.name = "gmii_gmac0_grp",
.pins = gmii_gmac0_3516_pins,
.num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
.mask = GEMINI_GMAC_IOSEL_MASK,
.driving_mask = GENMASK(17, 16),
},
{
@ -1703,6 +1704,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
.pins = gmii_gmac1_3516_pins,
.num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
/* Bring out RGMII on the GMAC1 pins */
.mask = GEMINI_GMAC_IOSEL_MASK,
.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
.driving_mask = GENMASK(19, 18),
},

2
drivers/pinctrl/pinctrl-mcp23s08.c
View File

@ -666,7 +666,7 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
* can be used to fix state for MCP23xxx, that temporary
* lost its power supply.
*/
#define MCP23S08_CONFIG_REGS 8
#define MCP23S08_CONFIG_REGS 7
static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp)
{
int cached[MCP23S08_CONFIG_REGS];

104
drivers/pinctrl/pinctrl-ocelot.c
View File

@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@ -132,7 +133,7 @@ OCELOT_P(0, SG0, NONE, NONE);
OCELOT_P(1, SG0, NONE, NONE);
OCELOT_P(2, SG0, NONE, NONE);
OCELOT_P(3, SG0, NONE, NONE);
OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI);
OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
OCELOT_P(6, UART, TWI_SCL_M, NONE);
OCELOT_P(7, UART, TWI_SCL_M, NONE);
@ -427,11 +428,98 @@ static const struct gpio_chip ocelot_gpiolib_chip = {
.owner = THIS_MODULE,
};
static void ocelot_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio), 0);
}
static void ocelot_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio),
BIT(gpio));
}
static void ocelot_irq_ack(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
regmap_write_bits(info->map, OCELOT_GPIO_INTR, BIT(gpio), BIT(gpio));
}
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
static struct irq_chip ocelot_eoi_irqchip = {
.name = "gpio",
.irq_mask = ocelot_irq_mask,
.irq_eoi = ocelot_irq_ack,
.irq_unmask = ocelot_irq_unmask,
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
.irq_set_type = ocelot_irq_set_type,
};
static struct irq_chip ocelot_irqchip = {
.name = "gpio",
.irq_mask = ocelot_irq_mask,
.irq_ack = ocelot_irq_ack,
.irq_unmask = ocelot_irq_unmask,
.irq_set_type = ocelot_irq_set_type,
};
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
{
type &= IRQ_TYPE_SENSE_MASK;
if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
if (type & IRQ_TYPE_LEVEL_HIGH)
irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
handle_fasteoi_irq, NULL);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
handle_edge_irq, NULL);
return 0;
}
static void ocelot_irq_handler(struct irq_desc *desc)
{
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int reg = 0, irq;
unsigned long irqs;
regmap_read(info->map, OCELOT_GPIO_INTR_IDENT, &reg);
if (!reg)
return;
chained_irq_enter(parent_chip, desc);
irqs = reg;
for_each_set_bit(irq, &irqs, OCELOT_PINS) {
generic_handle_irq(irq_linear_revmap(chip->irq.domain, irq));
}
chained_irq_exit(parent_chip, desc);
}
static int ocelot_gpiochip_register(struct platform_device *pdev,
struct ocelot_pinctrl *info)
{
struct gpio_chip *gc;
int ret;
int ret, irq;
info->gpio_chip = ocelot_gpiolib_chip;
@ -446,7 +534,17 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
if (ret)
return ret;
/* TODO: this can be used as an irqchip but no board is using that */
irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
if (irq <= 0)
return irq;
ret = gpiochip_irqchip_add(gc, &ocelot_irqchip, 0, handle_edge_irq,
IRQ_TYPE_NONE);
if (ret)
return ret;
gpiochip_set_chained_irqchip(gc, &ocelot_irqchip, irq,
ocelot_irq_handler);
return 0;
}

20
drivers/pinctrl/pinctrl-rza1.c
View File

@ -1006,6 +1006,7 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
const char *grpname;
const char **fngrps;
int ret, npins;
int gsel, fsel;
npins = rza1_dt_node_pin_count(np);
if (npins < 0) {
@ -1055,18 +1056,19 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
fngrps[0] = grpname;
mutex_lock(&rza1_pctl->mutex);
ret = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
NULL);
if (ret) {
if (gsel < 0) {
mutex_unlock(&rza1_pctl->mutex);
return ret;
return gsel;
}
ret = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
mux_confs);
if (ret)
if (fsel < 0) {
ret = fsel;
goto remove_group;
mutex_unlock(&rza1_pctl->mutex);
}
dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
grpname, npins);
@ -1083,15 +1085,15 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
*num_maps = 1;
mutex_unlock(&rza1_pctl->mutex);
return 0;
remove_function:
mutex_lock(&rza1_pctl->mutex);
pinmux_generic_remove_last_function(pctldev);
pinmux_generic_remove_function(pctldev, fsel);
remove_group:
pinctrl_generic_remove_last_group(pctldev);
pinctrl_generic_remove_group(pctldev, gsel);
mutex_unlock(&rza1_pctl->mutex);
dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",

117
drivers/pinctrl/pinctrl-single.c
View File

@ -747,38 +747,44 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
/**
* pcs_add_function() - adds a new function to the function list
* @pcs: pcs driver instance
* @np: device node of the mux entry
* @fcn: new function allocated
* @name: name of the function
* @vals: array of mux register value pairs used by the function
* @nvals: number of mux register value pairs
* @pgnames: array of pingroup names for the function
* @npgnames: number of pingroup names
*
* Caller must take care of locking.
*/
static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
struct device_node *np,
static int pcs_add_function(struct pcs_device *pcs,
struct pcs_function **fcn,
const char *name,
struct pcs_func_vals *vals,
unsigned nvals,
unsigned int nvals,
const char **pgnames,
unsigned npgnames)
unsigned int npgnames)
{
struct pcs_function *function;
int res;
int selector;
function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
if (!function)
return NULL;
return -ENOMEM;
function->vals = vals;
function->nvals = nvals;
res = pinmux_generic_add_function(pcs->pctl, name,
selector = pinmux_generic_add_function(pcs->pctl, name,
pgnames, npgnames,
function);
if (res)
return NULL;
if (selector < 0) {
devm_kfree(pcs->dev, function);
*fcn = NULL;
} else {
*fcn = function;
}
return function;
return selector;
}
/**
@ -979,8 +985,8 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
{
const char *name = "pinctrl-single,pins";
struct pcs_func_vals *vals;
int rows, *pins, found = 0, res = -ENOMEM, i;
struct pcs_function *function;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
struct pcs_function *function = NULL;
rows = pinctrl_count_index_with_args(np, name);
if (rows <= 0) {
@ -1030,21 +1036,25 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
}
pgnames[0] = np->name;
function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
if (!function) {
res = -ENOMEM;
mutex_lock(&pcs->mutex);
fsel = pcs_add_function(pcs, &function, np->name, vals, found,
pgnames, 1);
if (fsel < 0) {
res = fsel;
goto free_pins;
}
res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (res < 0)
gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (gsel < 0) {
res = gsel;
goto free_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
if (PCS_HAS_PINCONF) {
if (PCS_HAS_PINCONF && function) {
res = pcs_parse_pinconf(pcs, np, function, map);
if (res)
goto free_pingroups;
@ -1052,15 +1062,17 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
} else {
*num_maps = 1;
}
mutex_unlock(&pcs->mutex);
return 0;
free_pingroups:
pinctrl_generic_remove_last_group(pcs->pctl);
pinctrl_generic_remove_group(pcs->pctl, gsel);
*num_maps = 1;
free_function:
pinmux_generic_remove_last_function(pcs->pctl);
pinmux_generic_remove_function(pcs->pctl, fsel);
free_pins:
mutex_unlock(&pcs->mutex);
devm_kfree(pcs->dev, pins);
free_vals:
@ -1077,9 +1089,9 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
{
const char *name = "pinctrl-single,bits";
struct pcs_func_vals *vals;
int rows, *pins, found = 0, res = -ENOMEM, i;
int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
int npins_in_row;
struct pcs_function *function;
struct pcs_function *function = NULL;
rows = pinctrl_count_index_with_args(np, name);
if (rows <= 0) {
@ -1166,15 +1178,19 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
}
pgnames[0] = np->name;
function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
if (!function) {
res = -ENOMEM;
mutex_lock(&pcs->mutex);
fsel = pcs_add_function(pcs, &function, np->name, vals, found,
pgnames, 1);
if (fsel < 0) {
res = fsel;
goto free_pins;
}
res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (res < 0)
gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
if (gsel < 0) {
res = gsel;
goto free_function;
}
(*map)->type = PIN_MAP_TYPE_MUX_GROUP;
(*map)->data.mux.group = np->name;
@ -1186,14 +1202,17 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
}
*num_maps = 1;
mutex_unlock(&pcs->mutex);
return 0;
free_pingroups:
pinctrl_generic_remove_last_group(pcs->pctl);
pinctrl_generic_remove_group(pcs->pctl, gsel);
*num_maps = 1;
free_function:
pinmux_generic_remove_last_function(pcs->pctl);
pinmux_generic_remove_function(pcs->pctl, fsel);
free_pins:
mutex_unlock(&pcs->mutex);
devm_kfree(pcs->dev, pins);
free_vals:
@ -1598,19 +1617,19 @@ static int pcs_save_context(struct pcs_device *pcs)
switch (pcs->width) {
case 64:
regsl = (u64 *)pcs->saved_vals;
for (i = 0; i < pcs->size / mux_bytes; i++)
regsl[i] = pcs->read(pcs->base + i * mux_bytes);
regsl = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
*regsl++ = pcs->read(pcs->base + i);
break;
case 32:
regsw = (u32 *)pcs->saved_vals;
for (i = 0; i < pcs->size / mux_bytes; i++)
regsw[i] = pcs->read(pcs->base + i * mux_bytes);
regsw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
*regsw++ = pcs->read(pcs->base + i);
break;
case 16:
regshw = (u16 *)pcs->saved_vals;
for (i = 0; i < pcs->size / mux_bytes; i++)
regshw[i] = pcs->read(pcs->base + i * mux_bytes);
regshw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
*regshw++ = pcs->read(pcs->base + i);
break;
}
@ -1628,19 +1647,19 @@ static void pcs_restore_context(struct pcs_device *pcs)
switch (pcs->width) {
case 64:
regsl = (u64 *)pcs->saved_vals;
for (i = 0; i < pcs->size / mux_bytes; i++)
pcs->write(regsl[i], pcs->base + i * mux_bytes);
regsl = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
pcs->write(*regsl++, pcs->base + i);
break;
case 32:
regsw = (u32 *)pcs->saved_vals;
for (i = 0; i < pcs->size / mux_bytes; i++)
pcs->write(regsw[i], pcs->base + i * mux_bytes);
regsw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
pcs->write(*regsw++, pcs->base + i);
break;
case 16:
regshw = (u16 *)pcs->saved_vals;
for (i = 0; i < pcs->size / mux_bytes; i++)
pcs->write(regshw[i], pcs->base + i * mux_bytes);
regshw = pcs->saved_vals;
for (i = 0; i < pcs->size; i += mux_bytes)
pcs->write(*regshw++, pcs->base + i);
break;
}
}

17
drivers/pinctrl/pinmux.c
View File

@ -22,7 +22,6 @@
#include <linux/err.h>
#include <linux/list.h>
#include <linux/string.h>
#include <linux/sysfs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/pinctrl/machine.h>
@ -308,7 +307,6 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
selector++;
}
dev_err(pctldev->dev, "function '%s' not supported\n", function);
return -EINVAL;
}
@ -775,6 +773,16 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
void *data)
{
struct function_desc *function;
int selector;
if (!name)
return -EINVAL;
selector = pinmux_func_name_to_selector(pctldev, name);
if (selector >= 0)
return selector;
selector = pctldev->num_functions;
function = devm_kzalloc(pctldev->dev, sizeof(*function), GFP_KERNEL);
if (!function)
@ -785,12 +793,11 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
function->num_group_names = num_groups;
function->data = data;
radix_tree_insert(&pctldev->pin_function_tree, pctldev->num_functions,
function);
radix_tree_insert(&pctldev->pin_function_tree, selector, function);
pctldev->num_functions++;
return 0;
return selector;
}
EXPORT_SYMBOL_GPL(pinmux_generic_add_function);

7
drivers/pinctrl/pinmux.h
View File

@ -150,13 +150,6 @@ int pinmux_generic_add_function(struct pinctrl_dev *pctldev,
int pinmux_generic_remove_function(struct pinctrl_dev *pctldev,
unsigned int selector);
static inline int
pinmux_generic_remove_last_function(struct pinctrl_dev *pctldev)
{
return pinmux_generic_remove_function(pctldev,
pctldev->num_functions - 1);
}
void pinmux_generic_free_functions(struct pinctrl_dev *pctldev);
#else

14
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -250,22 +250,30 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
/* Convert register value to pinconf value */
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
arg = arg == MSM_NO_PULL;
if (arg != MSM_NO_PULL)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = arg == MSM_PULL_DOWN;
if (arg != MSM_PULL_DOWN)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
if (pctrl->soc->pull_no_keeper)
return -ENOTSUPP;
arg = arg == MSM_KEEPER;
if (arg != MSM_KEEPER)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (pctrl->soc->pull_no_keeper)
arg = arg == MSM_PULL_UP_NO_KEEPER;
else
arg = arg == MSM_PULL_UP;
if (!arg)
return -EINVAL;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
arg = msm_regval_to_drive(arg);

32
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -390,31 +390,47 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
switch (param) {
case PIN_CONFIG_DRIVE_PUSH_PULL:
arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_DRIVE_OPEN_SOURCE:
arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
if (pad->pullup != PMIC_GPIO_PULL_DOWN)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_UP:
arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
if (pad->pullup != PMIC_GPIO_PULL_UP_30)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
arg = !pad->is_enabled;
if (pad->is_enabled)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_POWER_SOURCE:
arg = pad->power_source;
break;
case PIN_CONFIG_INPUT_ENABLE:
arg = pad->input_enabled;
if (!pad->input_enabled)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_OUTPUT:
arg = pad->out_value;

16
drivers/pinctrl/samsung/pinctrl-exynos-arm.c
View File

@ -616,16 +616,22 @@ static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5260_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5260_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
},
};
@ -842,30 +848,40 @@ static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
.eint_gpio_init = exynos_eint_gpio_init,
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 1 data */
.pin_banks = exynos5420_pin_banks1,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 2 data */
.pin_banks = exynos5420_pin_banks2,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 3 data */
.pin_banks = exynos5420_pin_banks3,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos5420_retention_data,
}, {
/* pin-controller instance 4 data */
.pin_banks = exynos5420_pin_banks4,
.nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.retention_data = &exynos4_audio_retention_data,
},
};

68
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@ -25,6 +25,7 @@
#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/soc/samsung/exynos-pmu.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <dt-bindings/pinctrl/samsung.h>
@ -37,6 +38,8 @@ struct exynos_irq_chip {
u32 eint_con;
u32 eint_mask;
u32 eint_pend;
u32 eint_wake_mask_value;
u32 eint_wake_mask_reg;
};
static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
@ -215,6 +218,7 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = {
.eint_con = EXYNOS_GPIO_ECON_OFFSET,
.eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
.eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
/* eint_wake_mask_value not used */
};
static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
@ -330,6 +334,8 @@ u32 exynos_get_eint_wake_mask(void)
static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
@ -339,6 +345,7 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
exynos_eint_wake_mask |= bit;
else
exynos_eint_wake_mask &= ~bit;
our_chip->eint_wake_mask_value = exynos_eint_wake_mask;
return 0;
}
@ -346,6 +353,25 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = {
.chip = {
.name = "s5pv210_wkup_irq_chip",
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
.irq_set_type = exynos_irq_set_type,
.irq_set_wake = exynos_wkup_irq_set_wake,
.irq_request_resources = exynos_irq_request_resources,
.irq_release_resources = exynos_irq_release_resources,
},
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
.eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED,
/* Only difference with exynos4210_wkup_irq_chip: */
.eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK,
};
static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
.chip = {
.name = "exynos4210_wkup_irq_chip",
@ -360,6 +386,8 @@ static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = {
.eint_con = EXYNOS_WKUP_ECON_OFFSET,
.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
.eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED,
.eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK,
};
static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
@ -376,10 +404,14 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = {
.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
.eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
.eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED,
.eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK,
};
/* list of external wakeup controllers supported */
static const struct of_device_id exynos_wkup_irq_ids[] = {
{ .compatible = "samsung,s5pv210-wakeup-eint",
.data = &s5pv210_wkup_irq_chip },
{ .compatible = "samsung,exynos4210-wakeup-eint",
.data = &exynos4210_wkup_irq_chip },
{ .compatible = "samsung,exynos7-wakeup-eint",
@ -542,6 +574,27 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
return 0;
}
static void
exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata,
struct exynos_irq_chip *irq_chip)
{
struct regmap *pmu_regs;
if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) {
dev_warn(drvdata->dev,
"No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n");
return;
}
pmu_regs = drvdata->retention_ctrl->priv;
dev_info(drvdata->dev,
"Setting external wakeup interrupt mask: 0x%x\n",
irq_chip->eint_wake_mask_value);
regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg,
irq_chip->eint_wake_mask_value);
}
static void exynos_pinctrl_suspend_bank(
struct samsung_pinctrl_drv_data *drvdata,
struct samsung_pin_bank *bank)
@ -564,11 +617,24 @@ static void exynos_pinctrl_suspend_bank(
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
{
struct samsung_pin_bank *bank = drvdata->pin_banks;
struct exynos_irq_chip *irq_chip = NULL;
int i;
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
if (bank->eint_type == EINT_TYPE_GPIO)
exynos_pinctrl_suspend_bank(drvdata, bank);
else if (bank->eint_type == EINT_TYPE_WKUP) {
if (!irq_chip) {
irq_chip = bank->irq_chip;
exynos_pinctrl_set_eint_wakeup_mask(drvdata,
irq_chip);
} else if (bank->irq_chip != irq_chip) {
dev_warn(drvdata->dev,
"More than one external wakeup interrupt chip configured (bank: %s). This is not supported by hardware nor by driver.\n",
bank->name);
}
}
}
}
static void exynos_pinctrl_resume_bank(

11
drivers/pinctrl/samsung/pinctrl-samsung.h
View File

@ -223,6 +223,13 @@ struct samsung_retention_data {
* interrupts for the controller.
* @eint_wkup_init: platform specific callback to setup the external wakeup
* interrupts for the controller.
* @suspend: platform specific suspend callback, executed during pin controller
* device suspend, see samsung_pinctrl_suspend()
* @resume: platform specific resume callback, executed during pin controller
* device suspend, see samsung_pinctrl_resume()
*
* External wakeup interrupts must define at least eint_wkup_init,
* retention_data and suspend in order for proper suspend/resume to work.
*/
struct samsung_pin_ctrl {
const struct samsung_pin_bank_data *pin_banks;
@ -255,6 +262,10 @@ struct samsung_pin_ctrl {
* @pin_base: starting system wide pin number.
* @nr_pins: number of pins supported by the controller.
* @retention_ctrl: retention control runtime data.
* @suspend: platform specific suspend callback, executed during pin controller
* device suspend, see samsung_pinctrl_suspend()
* @resume: platform specific resume callback, executed during pin controller
* device suspend, see samsung_pinctrl_resume()
*/
struct samsung_pinctrl_drv_data {
struct list_head node;

333
drivers/pinctrl/sh-pfc/pfc-r8a77965.c
View File

@ -1758,6 +1758,263 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
};
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
};
static const unsigned int hscif0_data_mux[] = {
HRX0_MARK, HTX0_MARK,
};
static const unsigned int hscif0_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 12),
};
static const unsigned int hscif0_clk_mux[] = {
HSCK0_MARK,
};
static const unsigned int hscif0_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
};
static const unsigned int hscif0_ctrl_mux[] = {
HRTS0_N_MARK, HCTS0_N_MARK,
};
/* - HSCIF1 ----------------------------------------------------------------- */
static const unsigned int hscif1_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
};
static const unsigned int hscif1_data_a_mux[] = {
HRX1_A_MARK, HTX1_A_MARK,
};
static const unsigned int hscif1_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int hscif1_clk_a_mux[] = {
HSCK1_A_MARK,
};
static const unsigned int hscif1_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
};
static const unsigned int hscif1_ctrl_a_mux[] = {
HRTS1_N_A_MARK, HCTS1_N_A_MARK,
};
static const unsigned int hscif1_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
};
static const unsigned int hscif1_data_b_mux[] = {
HRX1_B_MARK, HTX1_B_MARK,
};
static const unsigned int hscif1_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(5, 0),
};
static const unsigned int hscif1_clk_b_mux[] = {
HSCK1_B_MARK,
};
static const unsigned int hscif1_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
};
static const unsigned int hscif1_ctrl_b_mux[] = {
HRTS1_N_B_MARK, HCTS1_N_B_MARK,
};
/* - HSCIF2 ----------------------------------------------------------------- */
static const unsigned int hscif2_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
};
static const unsigned int hscif2_data_a_mux[] = {
HRX2_A_MARK, HTX2_A_MARK,
};
static const unsigned int hscif2_clk_a_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 10),
};
static const unsigned int hscif2_clk_a_mux[] = {
HSCK2_A_MARK,
};
static const unsigned int hscif2_ctrl_a_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
};
static const unsigned int hscif2_ctrl_a_mux[] = {
HRTS2_N_A_MARK, HCTS2_N_A_MARK,
};
static const unsigned int hscif2_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
};
static const unsigned int hscif2_data_b_mux[] = {
HRX2_B_MARK, HTX2_B_MARK,
};
static const unsigned int hscif2_clk_b_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 21),
};
static const unsigned int hscif2_clk_b_mux[] = {
HSCK2_B_MARK,
};
static const unsigned int hscif2_ctrl_b_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
};
static const unsigned int hscif2_ctrl_b_mux[] = {
HRTS2_N_B_MARK, HCTS2_N_B_MARK,
};
static const unsigned int hscif2_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
};
static const unsigned int hscif2_data_c_mux[] = {
HRX2_C_MARK, HTX2_C_MARK,
};
static const unsigned int hscif2_clk_c_pins[] = {
/* SCK */
RCAR_GP_PIN(6, 24),
};
static const unsigned int hscif2_clk_c_mux[] = {
HSCK2_C_MARK,
};
static const unsigned int hscif2_ctrl_c_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
};
static const unsigned int hscif2_ctrl_c_mux[] = {
HRTS2_N_C_MARK, HCTS2_N_C_MARK,
};
/* - HSCIF3 ----------------------------------------------------------------- */
static const unsigned int hscif3_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
};
static const unsigned int hscif3_data_a_mux[] = {
HRX3_A_MARK, HTX3_A_MARK,
};
static const unsigned int hscif3_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 22),
};
static const unsigned int hscif3_clk_mux[] = {
HSCK3_MARK,
};
static const unsigned int hscif3_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
};
static const unsigned int hscif3_ctrl_mux[] = {
HRTS3_N_MARK, HCTS3_N_MARK,
};
static const unsigned int hscif3_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
};
static const unsigned int hscif3_data_b_mux[] = {
HRX3_B_MARK, HTX3_B_MARK,
};
static const unsigned int hscif3_data_c_pins[] = {
/* RX, TX */
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
};
static const unsigned int hscif3_data_c_mux[] = {
HRX3_C_MARK, HTX3_C_MARK,
};
static const unsigned int hscif3_data_d_pins[] = {
/* RX, TX */
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
};
static const unsigned int hscif3_data_d_mux[] = {
HRX3_D_MARK, HTX3_D_MARK,
};
/* - HSCIF4 ----------------------------------------------------------------- */
static const unsigned int hscif4_data_a_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
};
static const unsigned int hscif4_data_a_mux[] = {
HRX4_A_MARK, HTX4_A_MARK,
};
static const unsigned int hscif4_clk_pins[] = {
/* SCK */
RCAR_GP_PIN(1, 11),
};
static const unsigned int hscif4_clk_mux[] = {
HSCK4_MARK,
};
static const unsigned int hscif4_ctrl_pins[] = {
/* RTS, CTS */
RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
};
static const unsigned int hscif4_ctrl_mux[] = {
HRTS4_N_MARK, HCTS4_N_MARK,
};
static const unsigned int hscif4_data_b_pins[] = {
/* RX, TX */
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
};
static const unsigned int hscif4_data_b_mux[] = {
HRX4_B_MARK, HTX4_B_MARK,
};
/* - I2C -------------------------------------------------------------------- */
static const unsigned int i2c1_a_pins[] = {
/* SDA, SCL */
@ -3169,6 +3426,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(du_oddf),
SH_PFC_PIN_GROUP(du_cde),
SH_PFC_PIN_GROUP(du_disp),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
SH_PFC_PIN_GROUP(hscif1_data_a),
SH_PFC_PIN_GROUP(hscif1_clk_a),
SH_PFC_PIN_GROUP(hscif1_ctrl_a),
SH_PFC_PIN_GROUP(hscif1_data_b),
SH_PFC_PIN_GROUP(hscif1_clk_b),
SH_PFC_PIN_GROUP(hscif1_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data_a),
SH_PFC_PIN_GROUP(hscif2_clk_a),
SH_PFC_PIN_GROUP(hscif2_ctrl_a),
SH_PFC_PIN_GROUP(hscif2_data_b),
SH_PFC_PIN_GROUP(hscif2_clk_b),
SH_PFC_PIN_GROUP(hscif2_ctrl_b),
SH_PFC_PIN_GROUP(hscif2_data_c),
SH_PFC_PIN_GROUP(hscif2_clk_c),
SH_PFC_PIN_GROUP(hscif2_ctrl_c),
SH_PFC_PIN_GROUP(hscif3_data_a),
SH_PFC_PIN_GROUP(hscif3_clk),
SH_PFC_PIN_GROUP(hscif3_ctrl),
SH_PFC_PIN_GROUP(hscif3_data_b),
SH_PFC_PIN_GROUP(hscif3_data_c),
SH_PFC_PIN_GROUP(hscif3_data_d),
SH_PFC_PIN_GROUP(hscif4_data_a),
SH_PFC_PIN_GROUP(hscif4_clk),
SH_PFC_PIN_GROUP(hscif4_ctrl),
SH_PFC_PIN_GROUP(hscif4_data_b),
SH_PFC_PIN_GROUP(i2c1_a),
SH_PFC_PIN_GROUP(i2c1_b),
SH_PFC_PIN_GROUP(i2c2_a),
@ -3379,6 +3664,49 @@ static const char * const du_groups[] = {
"du_disp",
};
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
"hscif0_ctrl",
};
static const char * const hscif1_groups[] = {
"hscif1_data_a",
"hscif1_clk_a",
"hscif1_ctrl_a",
"hscif1_data_b",
"hscif1_clk_b",
"hscif1_ctrl_b",
};
static const char * const hscif2_groups[] = {
"hscif2_data_a",
"hscif2_clk_a",
"hscif2_ctrl_a",
"hscif2_data_b",
"hscif2_clk_b",
"hscif2_ctrl_b",
"hscif2_data_c",
"hscif2_clk_c",
"hscif2_ctrl_c",
};
static const char * const hscif3_groups[] = {
"hscif3_data_a",
"hscif3_clk",
"hscif3_ctrl",
"hscif3_data_b",
"hscif3_data_c",
"hscif3_data_d",
};
static const char * const hscif4_groups[] = {
"hscif4_data_a",
"hscif4_clk",
"hscif4_ctrl",
"hscif4_data_b",
};
static const char * const i2c1_groups[] = {
"i2c1_a",
"i2c1_b",
@ -3651,6 +3979,11 @@ static const char * const usb30_groups[] = {
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(du),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif4),
SH_PFC_FUNCTION(i2c1),
SH_PFC_FUNCTION(i2c2),
SH_PFC_FUNCTION(i2c6),

69
drivers/pinctrl/sh-pfc/pfc-r8a77990.c
View File

@ -277,7 +277,7 @@
#define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB1_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
@ -1082,7 +1082,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_GPSR(IP11_27_24, USB1_ID),
PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
PINMUX_IPSR_GPSR(IP11_31_28, RX1),
PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
@ -1784,6 +1784,53 @@ static const unsigned int scif_clk_b_mux[] = {
SCIF_CLK_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_a_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
};
static const unsigned int usb0_a_mux[] = {
USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
};
static const unsigned int usb0_b_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
};
static const unsigned int usb0_b_mux[] = {
USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
};
static const unsigned int usb0_id_pins[] = {
/* ID */
RCAR_GP_PIN(5, 0)
};
static const unsigned int usb0_id_mux[] = {
USB0_ID_MARK,
};
/* - USB30 ------------------------------------------------------------------ */
static const unsigned int usb30_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
};
static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
static const unsigned int usb30_id_pins[] = {
/* ID */
RCAR_GP_PIN(5, 0),
};
static const unsigned int usb30_id_mux[] = {
USB3HS0_ID_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(avb_link),
SH_PFC_PIN_GROUP(avb_magic),
@ -1837,6 +1884,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif5_data_c),
SH_PFC_PIN_GROUP(scif_clk_a),
SH_PFC_PIN_GROUP(scif_clk_b),
SH_PFC_PIN_GROUP(usb0_a),
SH_PFC_PIN_GROUP(usb0_b),
SH_PFC_PIN_GROUP(usb0_id),
SH_PFC_PIN_GROUP(usb30),
SH_PFC_PIN_GROUP(usb30_id),
};
static const char * const avb_groups[] = {
@ -1933,6 +1985,17 @@ static const char * const scif_clk_groups[] = {
"scif_clk_b",
};
static const char * const usb0_groups[] = {
"usb0_a",
"usb0_b",
"usb0_id",
};
static const char * const usb30_groups[] = {
"usb30",
"usb30_id",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(avb),
SH_PFC_FUNCTION(i2c1),
@ -1948,6 +2011,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif5),
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb30),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

43
drivers/pinctrl/stm32/pinctrl-stm32.c
View File

@ -46,6 +46,8 @@
#define STM32_GPIO_PINS_PER_BANK 16
#define STM32_GPIO_IRQ_LINE 16
#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
@ -73,6 +75,7 @@ struct stm32_gpio_bank {
struct fwnode_handle *fwnode;
struct irq_domain *domain;
u32 bank_nr;
u32 bank_ioport_nr;
};
struct stm32_pinctrl {
@ -298,7 +301,7 @@ static int stm32_gpio_domain_activate(struct irq_domain *d,
struct stm32_gpio_bank *bank = d->host_data;
struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
return 0;
}
@ -638,6 +641,11 @@ static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
}
range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
if (!range) {
dev_err(pctl->dev, "No gpio range defined.\n");
return -EINVAL;
}
bank = gpiochip_get_data(range->gc);
pin = stm32_gpio_pin(g->pin);
@ -806,11 +814,17 @@ static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
unsigned int pin, enum pin_config_param param,
enum pin_config_param arg)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset, ret = 0;
range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
if (!range) {
dev_err(pctl->dev, "No gpio range defined.\n");
return -EINVAL;
}
bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
@ -892,6 +906,9 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
bool val;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range)
return;
bank = gpiochip_get_data(range->gc);
offset = stm32_gpio_pin(pin);
@ -948,6 +965,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
struct device_node *np)
{
struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
int bank_ioport_nr;
struct pinctrl_gpio_range *range = &bank->range;
struct of_phandle_args args;
struct device *dev = pctl->dev;
@ -998,12 +1016,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
pinctrl_add_gpio_range(pctl->pctl_dev,
&pctl->banks[bank_nr].range);
}
if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
bank_ioport_nr = bank_nr;
bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip.ngpio = npins;
bank->gpio_chip.of_node = np;
bank->gpio_chip.parent = dev;
bank->bank_nr = bank_nr;
bank->bank_ioport_nr = bank_ioport_nr;
spin_lock_init(&bank->lock);
/* create irq hierarchical domain */
@ -1033,6 +1056,7 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
struct device *dev = &pdev->dev;
struct regmap *rm;
int offset, ret, i;
int mask, mask_width;
parent = of_irq_find_parent(np);
if (!parent)
@ -1052,12 +1076,21 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
if (ret)
return ret;
ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
if (ret)
mask = SYSCFG_IRQMUX_MASK;
mask_width = fls(mask);
for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
struct reg_field mux;
mux.reg = offset + (i / 4) * 4;
mux.lsb = (i % 4) * 4;
mux.msb = mux.lsb + 3;
mux.lsb = (i % 4) * mask_width;
mux.msb = mux.lsb + mask_width - 1;
dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
i, mux.reg, mux.lsb, mux.msb);
pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
if (IS_ERR(pctl->irqmux[i]))
@ -1166,7 +1199,7 @@ int stm32_pctl_probe(struct platform_device *pdev)
return PTR_ERR(pctl->pctl_dev);
}
for_each_child_of_node(np, child)
for_each_available_child_of_node(np, child)
if (of_property_read_bool(child, "gpio-controller"))
banks++;
@ -1179,7 +1212,7 @@ int stm32_pctl_probe(struct platform_device *pdev)
if (!pctl->banks)
return -ENOMEM;
for_each_child_of_node(np, child) {
for_each_available_child_of_node(np, child) {
if (of_property_read_bool(child, "gpio-controller")) {
ret = stm32_gpiolib_register_bank(pctl, child);
if (ret)

6
drivers/pinctrl/tegra/pinctrl-tegra.c
View File

@ -629,12 +629,12 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
}
}
static bool gpio_node_has_range(void)
static bool gpio_node_has_range(const char *compatible)
{
struct device_node *np;
bool has_prop = false;
np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
np = of_find_compatible_node(NULL, NULL, compatible);
if (!np)
return has_prop;
@ -728,7 +728,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
tegra_pinctrl_clear_parked_bits(pmx);
if (!gpio_node_has_range())
if (!gpio_node_has_range(pmx->soc->gpio_compatible))
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
platform_set_drvdata(pdev, pmx);

1
drivers/pinctrl/tegra/pinctrl-tegra.h
View File

@ -189,6 +189,7 @@ struct tegra_pingroup {
*/
struct tegra_pinctrl_soc_data {
unsigned ngpios;
const char *gpio_compatible;
const struct pinctrl_pin_desc *pins;
unsigned npins;
struct tegra_function *functions;

8
drivers/pinctrl/tegra/pinctrl-tegra114.c
View File

@ -1839,6 +1839,7 @@ static const struct tegra_pingroup tegra114_groups[] = {
static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra30-gpio",
.pins = tegra114_pins,
.npins = ARRAY_SIZE(tegra114_pins),
.functions = tegra114_functions,
@ -1867,4 +1868,9 @@ static struct platform_driver tegra114_pinctrl_driver = {
},
.probe = tegra114_pinctrl_probe,
};
builtin_platform_driver(tegra114_pinctrl_driver);
static int __init tegra114_pinctrl_init(void)
{
return platform_driver_register(&tegra114_pinctrl_driver);
}
arch_initcall(tegra114_pinctrl_init);

8
drivers/pinctrl/tegra/pinctrl-tegra124.c
View File

@ -2051,6 +2051,7 @@ static const struct tegra_pingroup tegra124_groups[] = {
static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra30-gpio",
.pins = tegra124_pins,
.npins = ARRAY_SIZE(tegra124_pins),
.functions = tegra124_functions,
@ -2079,4 +2080,9 @@ static struct platform_driver tegra124_pinctrl_driver = {
},
.probe = tegra124_pinctrl_probe,
};
builtin_platform_driver(tegra124_pinctrl_driver);
static int __init tegra124_pinctrl_init(void)
{
return platform_driver_register(&tegra124_pinctrl_driver);
}
arch_initcall(tegra124_pinctrl_init);

8
drivers/pinctrl/tegra/pinctrl-tegra20.c
View File

@ -2221,6 +2221,7 @@ static const struct tegra_pingroup tegra20_groups[] = {
static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra20-gpio",
.pins = tegra20_pins,
.npins = ARRAY_SIZE(tegra20_pins),
.functions = tegra20_functions,
@ -2276,4 +2277,9 @@ static struct platform_driver tegra20_pinctrl_driver = {
},
.probe = tegra20_pinctrl_probe,
};
builtin_platform_driver(tegra20_pinctrl_driver);
static int __init tegra20_pinctrl_init(void)
{
return platform_driver_register(&tegra20_pinctrl_driver);
}
arch_initcall(tegra20_pinctrl_init);

8
drivers/pinctrl/tegra/pinctrl-tegra210.c
View File

@ -1553,6 +1553,7 @@ static const struct tegra_pingroup tegra210_groups[] = {
static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra30-gpio",
.pins = tegra210_pins,
.npins = ARRAY_SIZE(tegra210_pins),
.functions = tegra210_functions,
@ -1581,4 +1582,9 @@ static struct platform_driver tegra210_pinctrl_driver = {
},
.probe = tegra210_pinctrl_probe,
};
builtin_platform_driver(tegra210_pinctrl_driver);
static int __init tegra210_pinctrl_init(void)
{
return platform_driver_register(&tegra210_pinctrl_driver);
}
arch_initcall(tegra210_pinctrl_init);

8
drivers/pinctrl/tegra/pinctrl-tegra30.c
View File

@ -2474,6 +2474,7 @@ static const struct tegra_pingroup tegra30_groups[] = {
static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
.ngpios = NUM_GPIOS,
.gpio_compatible = "nvidia,tegra30-gpio",
.pins = tegra30_pins,
.npins = ARRAY_SIZE(tegra30_pins),
.functions = tegra30_functions,
@ -2502,4 +2503,9 @@ static struct platform_driver tegra30_pinctrl_driver = {
},
.probe = tegra30_pinctrl_probe,
};
builtin_platform_driver(tegra30_pinctrl_driver);
static int __init tegra30_pinctrl_init(void)
{
return platform_driver_register(&tegra30_pinctrl_driver);
}
arch_initcall(tegra30_pinctrl_init);

10
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
View File

@ -517,6 +517,10 @@ static const int i2c4_muxvals[] = {1, 1};
static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
15, 16, 17};
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {56, 57, 58, 59};
static const int spi0_muxvals[] = {0, 0, 0, 0};
static const unsigned spi1_pins[] = {169, 170, 171, 172};
static const int spi1_muxvals[] = {1, 1, 1, 1};
static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17};
static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
@ -596,6 +600,8 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
@ -632,6 +638,8 @@ static const char * const i2c1_groups[] = {"i2c1"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const i2c4_groups[] = {"i2c4"};
static const char * const nand_groups[] = {"nand"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0"};
@ -657,6 +665,8 @@ static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

20
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
View File

@ -606,6 +606,14 @@ static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */
static const unsigned spi0_pins[] = {56, 57, 58, 59};
static const int spi0_muxvals[] = {0, 0, 0, 0};
static const unsigned spi1_pins[] = {169, 170, 171, 172};
static const int spi1_muxvals[] = {1, 1, 1, 1};
static const unsigned spi2_pins[] = {86, 87, 88, 89};
static const int spi2_muxvals[] = {1, 1, 1, 1};
static const unsigned spi3_pins[] = {74, 75, 76, 77};
static const int spi3_muxvals[] = {1, 1, 1, 1};
static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17};
static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
@ -685,6 +693,10 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c4),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(spi2),
UNIPHIER_PINCTRL_GROUP(spi3),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
@ -722,6 +734,10 @@ static const char * const i2c3_groups[] = {"i2c3"};
static const char * const i2c4_groups[] = {"i2c4"};
static const char * const nand_groups[] = {"nand"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const spi2_groups[] = {"spi2"};
static const char * const spi3_groups[] = {"spi3"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0"};
@ -751,6 +767,10 @@ static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c4),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(spi2),
UNIPHIER_PINMUX_FUNCTION(spi3),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

5
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View File

@ -576,6 +576,8 @@ static const unsigned nand_cs1_pins[] = {22, 23};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {135, 136, 137, 138};
static const int spi0_muxvals[] = {12, 12, 12, 12};
static const unsigned system_bus_pins[] = {16, 17, 18, 19, 20, 165, 166, 167,
168, 169, 170, 171, 172, 173};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1,
@ -640,6 +642,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
@ -667,6 +670,7 @@ static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs0",
"system_bus_cs1",
@ -690,6 +694,7 @@ static const struct uniphier_pinmux_function uniphier_ld4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

10
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View File

@ -769,6 +769,10 @@ static const unsigned nand_cs1_pins[] = {37, 38};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {199, 200, 201, 202};
static const int spi0_muxvals[] = {8, 8, 8, 8};
static const unsigned spi1_pins[] = {93, 94, 95, 96};
static const int spi1_muxvals[] = {1, 1, 1, 1};
static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -851,6 +855,8 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
@ -882,6 +888,8 @@ static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1",
"system_bus_cs2",
@ -907,6 +915,8 @@ static const struct uniphier_pinmux_function uniphier_ld6b_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

10
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View File

@ -1050,6 +1050,10 @@ static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
327};
static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {199, 200, 201, 202};
static const int spi0_muxvals[] = {11, 11, 11, 11};
static const unsigned spi1_pins[] = {195, 196, 197, 198, 235, 238, 239};
static const int spi1_muxvals[] = {11, 11, 11, 11, 11, 11, 11};
static const unsigned system_bus_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -1138,6 +1142,8 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(sd1),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
@ -1171,6 +1177,8 @@ static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const sd1_groups[] = {"sd1"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs0",
"system_bus_cs1",
@ -1202,6 +1210,8 @@ static const struct uniphier_pinmux_function uniphier_pro4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(sd1),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

15
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View File

@ -818,6 +818,12 @@ static const unsigned nand_cs1_pins[] = {26, 27};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {120, 121, 122, 123};
static const int spi0_muxvals[] = {0, 0, 0, 0};
static const unsigned spi1_pins[] = {134, 139, 85, 86};
static const int spi1_muxvals[] = {1, 1, 1, 1};
static const unsigned spi2_pins[] = {55, 56, 57, 58, 82, 83, 84};
static const int spi2_muxvals[] = {0, 0, 0, 0, 1, 1, 1};
static const unsigned system_bus_pins[] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
14, 15, 16, 17};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -904,6 +910,9 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c5c),
UNIPHIER_PINCTRL_GROUP(i2c6),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(spi2),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
@ -934,6 +943,9 @@ static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const spi2_groups[] = {"spi2"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs0",
"system_bus_cs1",
@ -961,6 +973,9 @@ static const struct uniphier_pinmux_function uniphier_pro5_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(spi2),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

10
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View File

@ -778,6 +778,10 @@ static const unsigned nand_cs1_pins[] = {37, 38};
static const int nand_cs1_muxvals[] = {8, 8};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
static const unsigned spi0_pins[] = {199, 200, 201, 202};
static const int spi0_muxvals[] = {8, 8, 8, 8};
static const unsigned spi1_pins[] = {93, 94, 95, 96};
static const int spi1_muxvals[] = {1, 1, 1, 1};
static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13};
static const int system_bus_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
@ -861,6 +865,8 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
@ -897,6 +903,8 @@ static const char * const i2c5_groups[] = {"i2c5"};
static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"};
@ -928,6 +936,8 @@ static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

10
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
View File

@ -808,6 +808,10 @@ static const unsigned int nand_pins[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned int sd_pins[] = {43, 44, 45, 46, 47, 48, 49, 50, 51};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {100, 101, 102, 103};
static const int spi0_muxvals[] = {0, 0, 0, 0};
static const unsigned spi1_pins[] = {112, 113, 114, 115};
static const int spi1_muxvals[] = {2, 2, 2, 2};
static const unsigned int system_bus_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14};
static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -886,6 +890,8 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c3),
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(spi1),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
@ -913,6 +919,8 @@ static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const spi1_groups[] = {"spi1"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"};
@ -936,6 +944,8 @@ static const struct uniphier_pinmux_function uniphier_pxs3_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(spi1),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

5
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View File

@ -504,6 +504,8 @@ static const unsigned nand_cs1_pins[] = {22, 23};
static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned spi0_pins[] = {118, 119, 120, 121};
static const int spi0_muxvals[] = {3, 3, 3, 3};
static const unsigned system_bus_pins[] = {136, 137, 138, 139, 140, 141, 142,
143, 144, 145, 146, 147, 148, 149};
static const int system_bus_muxvals[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1,
@ -570,6 +572,7 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(spi0),
UNIPHIER_PINCTRL_GROUP(system_bus),
UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
@ -598,6 +601,7 @@ static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const spi0_groups[] = {"spi0"};
static const char * const system_bus_groups[] = {"system_bus",
"system_bus_cs1",
"system_bus_cs2",
@ -622,6 +626,7 @@ static const struct uniphier_pinmux_function uniphier_sld8_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(spi0),
UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),

4
include/dt-bindings/pinctrl/at91.h
View File

@ -39,4 +39,8 @@
#define AT91_PERIPH_C 3
#define AT91_PERIPH_D 4
#define ATMEL_PIO_DRVSTR_LO 1
#define ATMEL_PIO_DRVSTR_ME 2
#define ATMEL_PIO_DRVSTR_HI 3
#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */

7
include/dt-bindings/pinctrl/samsung.h
View File

@ -1,14 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Samsung's Exynos pinctrl bindings
*
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Author: Krzysztof Kozlowski <krzk@kernel.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
*/
#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__

3
include/linux/pinctrl/pinconf.h
View File

@ -28,7 +28,8 @@ struct seq_file;
* is not available on this controller this should return -ENOTSUPP
* and if it is available but disabled it should return -EINVAL
* @pin_config_set: configure an individual pin
* @pin_config_group_get: get configurations for an entire pin group
* @pin_config_group_get: get configurations for an entire pin group; should
* return -ENOTSUPP and -EINVAL using the same rules as pin_config_get.
* @pin_config_group_set: configure all pins in a group
* @pin_config_dbg_parse_modify: optional debugfs to modify a pin configuration
* @pin_config_dbg_show: optional debugfs display hook that will provide

8
include/linux/soc/samsung/exynos-regs-pmu.h
View File

@ -42,7 +42,9 @@
#define EXYNOS_SWRESET 0x0400
#define S5P_WAKEUP_STAT 0x0600
#define S5P_EINT_WAKEUP_MASK 0x0604
/* Value for EXYNOS_EINT_WAKEUP_MASK disabling all external wakeup interrupts */
#define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
#define EXYNOS_EINT_WAKEUP_MASK 0x0604
#define S5P_WAKEUP_MASK 0x0608
#define S5P_WAKEUP_MASK2 0x0614
@ -180,6 +182,9 @@
#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8)
#define S5P_CORE_AUTOWAKEUP_EN (1 << 31)
/* Only for S5Pv210 */
#define S5PV210_EINT_WAKEUP_MASK 0xC004
/* Only for EXYNOS4210 */
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154
#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174
@ -641,6 +646,7 @@
| EXYNOS5420_KFC_USE_STANDBY_WFI3)
/* For EXYNOS5433 */
#define EXYNOS5433_EINT_WAKEUP_MASK (0x060C)
#define EXYNOS5433_USBHOST30_PHY_CONTROL (0x0728)
#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028)
#define EXYNOS5433_PAD_RETENTION_MMC2_OPTION (0x30C8)