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clk: rockchip: rk3368: fix cpuclk core dividers 

Similar to commit 9880d4277f ("clk: rockchip: fix rk3288 cpuclk core
dividers") it seems the cpuclk dividers are one to high on the rk3368
as well.

And again similar to the previous fix, we opt to make the divider list
contain the values to be written to use the same paradigm for them on all
supported socs.

Fixes: 3536c97a52 ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Heiko Stuebner 2016-01-19 10:09:22 +01:00
parent 535ebd428a
commit c6d5fe2ca8
1 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/clk/rockchip/clk-rk3368.c
View File

@ -218,29 +218,29 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
}
static struct rockchip_cpuclk_rate_table rk3368_cpuclkb_rates[] __initdata = {
RK3368_CPUCLKB_RATE(1512000000, 2, 6, 6),
RK3368_CPUCLKB_RATE(1488000000, 2, 5, 5),
RK3368_CPUCLKB_RATE(1416000000, 2, 5, 5),
RK3368_CPUCLKB_RATE(1200000000, 2, 4, 4),
RK3368_CPUCLKB_RATE(1008000000, 2, 4, 4),
RK3368_CPUCLKB_RATE( 816000000, 2, 3, 3),
RK3368_CPUCLKB_RATE( 696000000, 2, 3, 3),
RK3368_CPUCLKB_RATE( 600000000, 2, 2, 2),
RK3368_CPUCLKB_RATE( 408000000, 2, 2, 2),
RK3368_CPUCLKB_RATE( 312000000, 2, 2, 2),
RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
RK3368_CPUCLKB_RATE( 696000000, 1, 2, 2),
RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
};
static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
RK3368_CPUCLKL_RATE(1512000000, 2, 7, 7),
RK3368_CPUCLKL_RATE(1488000000, 2, 6, 6),
RK3368_CPUCLKL_RATE(1416000000, 2, 6, 6),
RK3368_CPUCLKL_RATE(1200000000, 2, 5, 5),
RK3368_CPUCLKL_RATE(1008000000, 2, 5, 5),
RK3368_CPUCLKL_RATE( 816000000, 2, 4, 4),
RK3368_CPUCLKL_RATE( 696000000, 2, 3, 3),
RK3368_CPUCLKL_RATE( 600000000, 2, 3, 3),
RK3368_CPUCLKL_RATE( 408000000, 2, 2, 2),
RK3368_CPUCLKL_RATE( 312000000, 2, 2, 2),
RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
RK3368_CPUCLKL_RATE( 696000000, 1, 2, 2),
RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
};
static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {