tg3: Whitespace, constant, and comment updates
This patch fixes whitespace errors, preprocessor definition placement oddities and updates comments. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -142,6 +142,8 @@
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#define TG3_RX_JMB_BUFF_RING_SIZE \
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(sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
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#define TG3_RSS_MIN_NUM_MSIX_VECS 2
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/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
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@ -152,6 +154,8 @@
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#define TG3_NUM_TEST 6
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#define TG3_FW_UPDATE_TIMEOUT_SEC 5
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#define FIRMWARE_TG3 "tigon/tg3.bin"
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#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
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#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
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@ -167,8 +171,6 @@ MODULE_FIRMWARE(FIRMWARE_TG3);
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MODULE_FIRMWARE(FIRMWARE_TG3TSO);
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MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
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#define TG3_RSS_MIN_NUM_MSIX_VECS 2
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static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
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module_param(tg3_debug, int, 0);
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MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
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@ -651,6 +653,7 @@ static void tg3_enable_ints(struct tg3 *tp)
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tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
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for (i = 0; i < tp->irq_cnt; i++) {
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struct tg3_napi *tnapi = &tp->napi[i];
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tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
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if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
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tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
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@ -4211,6 +4214,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
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tp->serdes_counter--;
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return;
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}
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if (!netif_carrier_ok(tp->dev) &&
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(tp->link_config.autoneg == AUTONEG_ENABLE)) {
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u32 bmcr;
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@ -4519,8 +4523,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
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struct tg3 *tp = tnapi->tp;
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struct tg3_rx_buffer_desc *src_desc, *dest_desc;
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struct ring_info *src_map, *dest_map;
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int dest_idx;
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struct tg3_rx_prodring_set *spr = &tp->prodring[0];
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int dest_idx;
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switch (opaque_key) {
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case RXD_OPAQUE_RING_STD:
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@ -4981,7 +4985,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
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if (unlikely(work_done >= budget))
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break;
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/* tp->last_tag is used in tg3_restart_ints() below
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/* tp->last_tag is used in tg3_int_reenable() below
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* to tell the hw how much work has been processed,
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* so we must read it before checking for more work.
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*/
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@ -5496,7 +5500,6 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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struct netdev_queue *txq;
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unsigned int i, last;
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txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
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tnapi = &tp->napi[skb_get_queue_mapping(skb)];
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
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@ -5700,7 +5703,6 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
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struct netdev_queue *txq;
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unsigned int i, last;
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txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
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tnapi = &tp->napi[skb_get_queue_mapping(skb)];
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
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@ -6013,7 +6015,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
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}
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}
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/* Initialize tx/rx rings for packet processing.
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/* Initialize rx rings for packet processing.
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*
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* The chip has been shut down and the driver detached from
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* the networking, so no interrupts or new tx packets will
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@ -8491,8 +8493,8 @@ static void tg3_timer(unsigned long __opaque)
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
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FWCMD_NICDRV_ALIVE3);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
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/* 5 seconds timeout */
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
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TG3_FW_UPDATE_TIMEOUT_SEC);
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tg3_generate_fw_event(tp);
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}
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@ -12003,7 +12005,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
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if ((page_off == 0) || (i == 0))
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if (page_off == 0 || i == 0)
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nvram_cmd |= NVRAM_CMD_FIRST;
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if (page_off == (tp->nvram_pagesize - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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@ -252,7 +252,7 @@
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/* 0x94 --> 0x98 unused */
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#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
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#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
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/* 0xa0 --> 0xb8 unused */
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/* 0xa8 --> 0xb8 unused */
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#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
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#define DUAL_MAC_CTRL_CH_MASK 0x00000003
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#define DUAL_MAC_CTRL_ID 0x00000004
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