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tile: set ARCH_KMALLOC_MINALIGN 

Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.

Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
FUJITA Tomonori 2010-06-30 11:10:08 +09:00 committed by Chris Metcalf
parent 4b2bf4b3fc
commit c6673cb54d
1 changed files with 8 additions and 0 deletions
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8
arch/tile/include/asm/cache.h
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@ -31,6 +31,14 @@
#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
/*
* TILE-Gx is fully coherents so we don't need to define
* ARCH_KMALLOC_MINALIGN.
*/
#ifndef __tilegx__
#define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES
#endif
/* use the cache line size for the L2, which is where it counts */ /* use the cache line size for the L2, which is where it counts */
#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
#define SMP_CACHE_BYTES L2_CACHE_BYTES #define SMP_CACHE_BYTES L2_CACHE_BYTES