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s390: optimize control register update 

It is less expensive to update control registers 0 and 2 with two
individual stctg/lctlg instructions as with a single one that spans
control register 0, 1 and 2.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Martin Schwidefsky 2013-12-03 14:57:18 +01:00
parent 1c182a6280
commit c63badebfe
1 changed files with 12 additions and 11 deletions
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23
arch/s390/kernel/ptrace.c
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@ -56,25 +56,26 @@ void update_cr_regs(struct task_struct *task)
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
/* Take care of the enable/disable of transactional execution. */ /* Take care of the enable/disable of transactional execution. */
if (MACHINE_HAS_TE) { if (MACHINE_HAS_TE) {
unsigned long cr[3], cr_new[3]; unsigned long cr, cr_new;
__ctl_store(cr, 0, 2); __ctl_store(cr, 0, 0);
cr_new[1] = cr[1];
/* Set or clear transaction execution TXC bit 8. */ /* Set or clear transaction execution TXC bit 8. */
cr_new = cr | (1UL << 55);
if (task->thread.per_flags & PER_FLAG_NO_TE) if (task->thread.per_flags & PER_FLAG_NO_TE)
cr_new[0] = cr[0] & ~(1UL << 55); cr_new &= ~(1UL << 55);
else if (cr_new != cr)
cr_new[0] = cr[0] | (1UL << 55); __ctl_load(cr, 0, 0);
/* Set or clear transaction execution TDC bits 62 and 63. */ /* Set or clear transaction execution TDC bits 62 and 63. */
cr_new[2] = cr[2] & ~3UL; __ctl_store(cr, 2, 2);
cr_new = cr & ~3UL;
if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND) { if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND) {
if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND_TEND) if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND_TEND)
cr_new[2] |= 1UL; cr_new |= 1UL;
else else
cr_new[2] |= 2UL; cr_new |= 2UL;
} }
if (memcmp(&cr_new, &cr, sizeof(cr))) if (cr_new != cr)
__ctl_load(cr_new, 0, 2); __ctl_load(cr_new, 2, 2);
} }
#endif #endif
/* Copy user specified PER registers */ /* Copy user specified PER registers */